Detailed Action
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of Umezaki - U.S. Patent No. 12,300,192 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because:
The instant application claim is broader in every aspect than the patent claim and is therefore an obvious variant thereof.
Current Application – Claim 6
U.S. Patent 12,300,192 B2 – Claim 1
A semiconductor device comprising:
a gate driver comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same polarity,
A semiconductor device comprising: a gate driver comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same polarity,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor, and
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor.
wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the sixth transistor and the other of the source and the drain of the eighth transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to a gate of the seventh transistor,
wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the third transistor and the one of the source and the drain of the fourth transistor,
wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, the one of the source and the drain of the fifth transistor, and the one of the source and the drain of the sixth transistor,
wherein a gate of the fifth transistor is electrically connected to the one of the source and the drain of the seventh transistor and the one of the source and the drain of the eighth transistor,
wherein a gate of the sixth transistor is electrically connected to a gate of the eighth transistor,
wherein the gate of the sixth transistor is electrically connected to a fifth wiring,
wherein the first wiring is configured to output an output signal,
wherein the second wiring is configured to be supplied with a clock signal, and
wherein the third wiring is configured to be supplied with a potential.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim(s) 6 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Sasaki et al (PGPUB 2005/0185752 A1).
As to claim 6, Sasaki (Fig. 4) teaches, a semiconductor device (liquid crystal display device, ¶ 32) comprising:
a gate driver (scan line driver circuit 21, ¶ 33) comprising a first transistor (second transistor T2), a second transistor (first transistor T1), a third transistor (seventh transistor T7), a fourth transistor (eighth transistor T8), a fifth transistor (sixth transistor T6), a sixth transistor (third transistor T3), a seventh transistor (fourth transistor T4), and an eighth transistor (fifth transistor T5)(Fig. 4),
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same polarity (Fig. 4: i.e. all transistors are shown as P-type transistor, ¶ 60),
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor (Fig. 4: i.e. upper terminal of T1 and lower terminal of T2 are connected),
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor (Fig. 4: i.e. upper terminal of T8 and lower terminal of T7 are connected),
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor (Fig. 4: i.e. upper terminal of t3 and lower terminal of T6 are connected), and
wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor (Fig. 4: i.e. upper terminal of T5 and lower terminal of T4 are connected).
Allowable Subject Matter
Claims 2-5 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant’s invention regards the shift register structure that comprises first flip-flop circuit F and first transfer circuit T for each stage of gate driver as shown in Fig. 2. The structure of the flip-flop circuit and the transfer circuit are shown in Fig. 4. The claim specifically recites the limitation that refer to the following features while requiring all of the limitations already presented in claims 2 and 4.
wherein the other one of the source and the drain of the third transistor is electrically connected to a gate of the third transistor (transistor 401)
wherein the other of the source and the drain of the seventh transistor is electrically connected to a gate of the seventh transistor (transistor 405)
wherein a gate of the second transistor is electrically connected to a gate of the fourth transistor, the one of the source and the drain of the fifth transistor, and the one of the source and the drain of the sixth transistor (Transistor 404 connects to gate of transistor 402 and transistors 407/408).
wherein a gate of the sixth transistor is electrically connected to the fifth wiring, wherein a gate of the eighth transistor is electrically connected to the fifth wiring (transistors 406 and 408).
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623