DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 2-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US Pub: 2005/0104836 A1).
As to claim 1, Lin discloses a scanning signal line drive circuit configured to drive a plurality of scanning signal lines arranged in a display portion of a display device (i.e. as seen in figure 3a and 6, Lin shows element 10 scanning driver being integrated on the TFT type LCD display where the display pixel area 1 is arranged along the G1 … Gn scanning signal lines) (see Fig. 6, 3a, [0043-0046]), the scanning signal line drive circuit comprising:
a plurality of unit circuits connected in cascade to form a shift register (i.e. the shift register as demonstrated in figure 5a is said to be part of the display driving system of figure 6) (see Fig. 5a, 6, [0034-0046]), wherein each unit circuit is configured to determine a state of the unit circuit based on a set signal and a reset signal provided as input signals (i.e. as seen in figure 5a the shift register of Lin uses the SR set reset design) (see Fig. 5a, [0034-0042]), and includes an internal node configured to selectively hold voltages of first and second logic levels indicating states of each unit circuit (i.e. the internode Q as seen in figure 3A which serves as the control node) (see Fig. 3a) (see Fig. 3a, [0028-0031]), a set circuit configured to apply a voltage of the first logic level to the internal node when the set signal is active (i.e. the set circuit is the circuit as seen in figure 3a including P3 and P1 which allows the IN set input to apply a voltage VDD to the internal node Q) (see Fig. 3a, [0028-0031]), and a reset circuit configured to apply a voltage of the second logic level to the internal node when the reset signal is active (i.e. the reset circuit is the circuit shown in figure 3a which include P4 and P2 which apply a second logic level as the reset function in the SR register node implies) (see Fig. 3a, [0028-0031]), the reset circuit includes a reset transistor including a drain terminal connected to the internal node (i.e. the transistor P4 has a drain terminal that is connected to internal node Q via P2 and P5) (see Fig. 3a, [0028-0031]), a source terminal, and a gate terminal to which the reset signal is supplied (i.e. P4 is gate connected to RESET signal line) (see Fig. 3a, [0028-0031]), and the shift register is configured such that, in each unit circuit, a voltage signal is supplied to the source terminal of the reset transistor as a reset state voltage signal (i.e. as seen in figure 3a and 5a the SR register of Lin is designed to function in the waveform state of figure 3B which allow the SR register to properly store states) (see Fig. 3a, 3b, 5a, [0028-0042]), the voltage signal maintaining an active voltage level corresponding to an active state of the reset signal when the reset signal changes from an inactive state to an active state (i.e. as seen in figure 3b the voltage signal is maintained in the state) (see Fig. 3a 3b, [0028-0032]), and changing from the active voltage level to the second logic level before the reset signal changes from the active state to the inactive state (i.e. as seen in figure 3b the state table shows that change in the output from active level of high to the second level during the reset signal change from high to low) (see Fig. 3b, [0032]).
As to claim 6, Lin teaches the scanning signal line drive circuit according to claim 1, wherein the set circuit includes a transistor of a diode connection configuration including a drain terminal and a gate terminal that are supplied with the set signal and including a source terminal connected to the internal node (i.e. as seen in figure 3A the transistor P3 is diode connected and apply control to the internal node Q) (see Fig. 3A, [0028-0031]).
As to claim 7, Lin teaches the scanning signal line drive circuit according to claim 1, wherein the reset transistor is a thin film transistor (i.e. the transistor of Lin are all said to be TFT in structure) (see Fig. 3a, [0028]).
As to claim 8, Lin teaches the scanning signal line drive circuit according to claim 7, wherein the reset transistor is a thin film transistor including a channel layer formed of an oxide semiconductor (i.e. as seen in figure 3A the transistor of Lin is said to be of MOS design with is a metal oxide type with channel layer formed of an oxide semiconductor) (see Fig. 3a, [0028]).
As to claim 9, Lin teaches a display device comprising the scanning signal line drive circuit according to claim 1, wherein the scanning signal line drive circuit and the display portion are integrally formed on an identical substrate (i.e. as seen in figure 6 embodiment Lin the TFT integrated type of display substrate design shows that the circuitry and display area are of identical TFT implementation where a singular base substrate is applied) (see Fig. 6, [0043-0046]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The prior art Enami (US Patent 10,199,001 B2) is cited to teach another type of TFT display with active control elements in figure 1-3 embodiments. The prior art Nishi et al. (US Pub: 2022/0189409 A1) is cited to teach integrate TFT display with scanning line control as seen in figure 1-6 embodiments.
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/CALVIN C MA/Primary Examiner, Art Unit 2693 January 24, 2026