DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 2-10, 12-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1, 11, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bae et al. (US Pub: 2024/0221633 A1).
As to claim 1, Bae discloses a sub-pixel (i.e. as seen in figure 1-2 the subpixel of the OLED display is demonstrated by figure 2 embodiment which shows a subpixel of the display of figure 1) (see Fig. 1-2, [0058-0063]) comprising:
a first transistor (i.e. element DRT) connected between a first node (i.e. element N3), receiving a first power voltage (i.e. the first power voltage is EVDD which is connected to the DRT transistor) (see Fig. 2, [0058-0069]), and a second node (i.e. element N2 node as seen in figure 2), including a control electrode connected to a third node (i.e. the control element is the gate of DRT which is connected to N1 which is the third node) (see Fig. 2), and generating a driving current (i.e. the transistor DRT is connected to the ED OLED display element with the driving current) (see Fig. 2, [0058-0069]);
a second transistor (i.e. the element SCT which has the Vdata connection) (see Fig. 2) providing a data voltage to the third node in response to a first gate signal (i.e. the first gate signal is the SCAN SCL signal which provide the data voltage Vdata to the N1 third node) (see Fig. 2, [0058-0069]);
a third transistor providing a ground voltage to the second node in response to a second gate signal (i.e. the third transistor is the transistor SENT which is connected to the GND ground voltage via the capacitor Crvl) (see Fig. 2, [0070]); and
a light emitting element emitting light by receiving the driving current (i.e. the element ED) (see Fig. 2), and including a first electrode connected to the second node (i.e. the N2 node is connected to the electrode of ED display diode) (see Fig. 2) and a second electrode receiving a second power voltage (i.e. the EVss is the second power voltage) (see Fig. 2, [0058-0070]), wherein the third transistor is configured as an NMOS transistor (i.e. the transistor of figure 2 is said to be a NMOS type design) (see [0117]).
As to claim 11, Bae teaches a display device (i.e. as seen in figure 1 the subpixel of the OLED display is demonstrated by figure 1 embodiment which shows the display of figure 1) (see Fig. 1, [0035-0036]) comprising:
a display panel including a sub-pixel (i.e. as seen in figure 1-2 the subpixel of the OLED display is demonstrated by figure 2 embodiment which shows a subpixel of the display of figure 1) (see Fig. 1-2, [0058-0063]); and
a display panel driver configured to drive the display panel (i.e. the driving element 140 which is the display controller for controlling the display panel DA) (see Fig. 1, [0034-0037]), wherein the sub-pixel comprises:
a first transistor (i.e. element DRT) connected between a first node, receiving a first power voltage, and a second node, including a control electrode connected to a third node, and generating a driving current (i.e. the transistor DRT is connected to the ED OLED display element with the driving current) (see Fig. 2, [0058-0069]);
a second transistor (i.e. the element SCT which has the Vdata connection) (see Fig. 2) providing a data voltage to the third node in response to a first gate signal (i.e. the first gate signal is the SCAN SCL signal which provide the data voltage Vdata to the N1 third node) (see Fig. 2, [0058-0069]);
a third transistor providing a ground voltage to the second node in response to a second gate signal (i.e. the third transistor is the transistor SENT which is connected to the GND ground voltage via the capacitor Crvl) (see Fig. 2, [0070]); and
a light emitting element emitting light by receiving the driving current (i.e. the element ED) (see Fig. 2), and including a first electrode connected to the second node and a second electrode receiving a second power voltage (i.e. the EVss is the second power voltage) (see Fig. 2, [0058-0070]), wherein the third transistor is configured as an NMOS transistor (i.e. the transistor of figure 2 is said to be a NMOS type design) (see [0117]).
As to claim 20, Bae teaches an electronic device(i.e. as seen in figure 1 the subpixel of the OLED display is demonstrated by figure 1 embodiment which shows the display of figure 1) (see Fig. 1, [0035-0036]) comprising:
a display device including a display panel including a sub-pixel (i.e. as seen in figure 1-2 the subpixel of the OLED display is demonstrated by figure 2 embodiment which shows a subpixel of the display of figure 1) (see Fig. 1-2, [0058-0063]); and
a display panel driver configured to drive the display panel, wherein the sub-pixel (i.e. the driving element 140 which is the display controller for controlling the display panel DA) (see Fig. 1, [0034-0037]) comprises:
a first transistor (i.e. element DRT) connected between a first node, receiving a first power voltage, and a second node, including a control electrode connected to a third node, and generating a driving current (i.e. the transistor DRT is connected to the ED OLED display element with the driving current) (see Fig. 2, [0058-0069]);
a second transistor (i.e. the element SCT which has the Vdata connection) (see Fig. 2) providing a data voltage to the third node in response to a first gate signal (i.e. the first gate signal is the SCAN SCL signal which provide the data voltage Vdata to the N1 third node) (see Fig. 2, [0058-0069]);
a third transistor providing a ground voltage to the second node in response to a second gate signal (i.e. the third transistor is the transistor SENT which is connected to the GND ground voltage via the capacitor Crvl) (see Fig. 2, [0070]); and
a light emitting element emitting light by receiving the driving current (i.e. the element ED) (see Fig. 2), and including a first electrode connected to the second node and a second electrode receiving a second power voltage (i.e. the EVss is the second power voltage) (see Fig. 2, [0058-0070]), wherein the third transistor is configured as an NMOS transistor (i.e. the transistor of figure 2 is said to be a NMOS type design) (see [0117]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art Wei et al. (US Pub: 2024/0185779 A1) is cited to teach another type of display control system with three transistor design as seen in figures 1-5 embodiments.
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/CALVIN C MA/Primary Examiner, Art Unit 2693 March 10, 2026