Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-12 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2023/0018546 A1, hereinafter “Kim”).
As to claim 1, Kim (Fig. 9A) discloses a pixel (110) comprising:
a first transistor (T9) having a first electrode connected to a third node (B), a second electrode connected to a second node (D), and a gate electrode connected to a first node (node between gate of T9 and T6);
a second transistor (T6) having a first electrode connected to a fourth node (node E), a second electrode connected to the second node (electrically connected through T5, node D), and a gate electrode connected to a first emission control line (Vcomp(n));
a third transistor (T2) having a first electrode connected to the fourth node (node E; electrically connected through C1, T3 and T6), a second electrode connected to a data line (VPM_R/G/B), and a gate electrode connected to a scan line (SP(n));
a fourth transistor (T3) having a first electrode connected to a sixth power line (Vref), a second electrode connected to the third node (node B), and a gate electrode connected to a second emission control line (Vini(n));
a fifth transistor (T5) having a first electrode connected to the third node (electrically connected through T9 to node B), a second electrode connected to a fifth node (node between T5 and T3), and a gate electrode connected to the second emission control line (Vini(n));
a sixth transistor (T4) having a first electrode connected to the fifth node (electrically through T8 and T6), a second electrode connected to a sixth node (node between T4 and VDD_PWM), and a gate electrode connected to the second emission control line (Vini(n));
a seventh transistor (T11) having a first electrode connected to a pixel power line (VSS), a second electrode connected to the fifth node (electrically connected through T14, T13 and T6), and a gate electrode connected to the scan line (SP(n));
an eighth transistor (T13) having a first electrode connected to a first power line (VCC_R/G/B; para. 0122), a second electrode connected to the sixth node (electrically connected through T8 and T4), and a gate electrode connected to the fifth node (electrically connected through T3);
a first capacitor (C3) connected between the first node (node between gate of T9 and T6) and the fourth node (node E, when T5 is turned off);
a second capacitor (C2) connected between the first power line (electrically through T10, T14, T11) and the fifth node (electrically through T8 and T6 to node between T5 and T3);
a third capacitor (C1) connected between the fourth node (node E) and a seventh power line (Sweep); and
a light emitting element (120) connected between the sixth node (electrically connected through T15, T14, T13, T8 and T4 to node between T4 and VDD_PWM) and a second power line (VSS).
The above rejection also stands for the similar devices of claim 8 and claim 20.
As to claim 2, Kim discloses the pixel according to claim 1, wherein each of the first to fourth transistors, the sixth transistor, and the seventh transistor includes an oxide semiconductor layer, and each of the fifth transistor and the eighth transistor includes a silicon semiconductor layer (Para. 0152).
The above rejection also stands for the similar device of claim 9.
As to claim 3, Kim (9A) discloses the pixel according to claim 1, further comprising:
a ninth transistor (T4) having a first electrode connected to the fifth node (electrically connected through T8 and T6 to node between T5 and T3), a second electrode connected to a third power line (VDD_PWM), and a gate electrode connected to an initialization line (Vini(n)).
The above rejection also stands for the similar device of claim 10.
As to claim 4, Kim (Fig. 9A) discloses the pixel according to claim 3, further comprising:
a tenth transistor (T15) having a first electrode connected to a first electrode of the light emitting element (120), a second electrode connected to a fourth power line (VDD_PAM), and a gate electrode connected to a control line (Emi(n)).
The above rejection also stands for the similar device of claim 11.
As to claim 5, Kim (Fig. 9A) discloses the pixel according to claim 4, further comprising:
an eleventh transistor (T12) having a first electrode connected to a fifth power line (VDD_PAM), a second electrode connected to the first node (connected through gate of T6 to node between gate of T9 and T6), and a gate electrode connected to the initialization line (Emi(n)).
The above rejection also stands for the similar device of claim 12.
Allowable Subject Matter
Claims 6-7 and 13-19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Kim et al. (US 2021/0210003 A1) discloses three capacitors in a pixel circuit (Fig. 12).
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BIPIN GYAWALI
Examiner
Art Unit 2625
/BIPIN GYAWALI/ Examiner, Art Unit 2625