DETAILED ACTION
Status of Application
Claims 1-20 are pending in the instant application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6, 9-10, 14-16 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park (US 20250104649 A1).
Regarding claim 1, Park teaches an emission driving circuit comprising: a pull-up controller configured to transmit a first voltage to a first pull-up control node in response to an input signal, (Para 195. Fig. 6A and 6B. 6B shows a stage of an emission driving circuit. T14 is the first pull-up controller. Para 197. T14 transmits VEH to Q11)
to control a voltage of a second pull-up control node in response to a voltage of the first pull-up control node and a clock signal, (Para 197. Fig. 6B. QB1 gets ECLK based on voltage at Q11 and ECLK)
and to transmit a second voltage to a third pull-up control node in response to the voltage of the second pull-up control node; (Para 197. Fig. 6B. T16 transmit second voltage VEH to QB1 to change the voltage of voltage of the second pull-up control node to a VEH at a third pull-up control node. So the second pull up control node is also the third pull up control node)
a pull-down controller configured to transmit the input signal to a second pull-down control node in response to the input signal and the clock signal; (Para 197-198. Fig. 6B. T13 transfer input signal EVST to Q12, then transfer to Q1 which is the pull down node through TA which is the pull down controller.)
and an output circuit configured to output an emission signal from an output node in response to a voltage of the third pull-up control node and a voltage of the second pull-down control node. (Para 197. Fig. 6B. The (1-1)-st gate transistor T11 may pull up an output terminal in response to a signal of a Q1 node, and the (1-2)-nd gate transistor T12 may pull down an output terminal in response to a signal of a QB1 node. So the output Em is based on the voltage of the third pull-down control node and a voltage of the second pull-down control node.)
Regarding claim 2, Park already teaches the emission driving circuit of claim 1, and Park further teaches wherein the pull-up controller includes: a first transistor including a first gate electrode configured to receive the input signal, a first electrode configured to receive the first voltage, and a second electrode connected to the first pull-up control node; (Fig. 6B. Para 197. T14 with gate to receive input signal EVST, first electrode to receive VEH, and the second electrode connected to Q11)
a second transistor including a first gate electrode connected to the first pull-up control node, a first electrode connected to the second pull-up control node, and a second electrode configured to receive the clock signal; (Fig. 6B. Para 197. T15 with gate electrode connected to Q11, a first electrode connected to QB1, and a second electrode configured to receive the clock signal ECLK)
a third transistor including a first gate electrode connected to the second pull-up control node, a first electrode connected to the third pull-up control node, and a second electrode configured to receive the second voltage; (Fig. 6B. Para 197. T16 with gate indirectly connected to second pull-up node QB1, and a first electrode connected to the third pull-up control node QB!, and a second electrode configured to receive the second voltage ECLK before its changed over to VEH after T16 is turned on)
and a first capacitor including a first electrode connected to the first pull-up control node, and a second electrode configured to receive the clock signal. (Fig. 6B. CC1 connected to ECLK and Q11)
Regarding claim 6, Park already teaches the emission driving circuit of claim 1, and Park further teaches wherein the output circuit includes: an eighth transistor including a first gate electrode connected to the third pull-up control node, a first electrode configured to receive the first voltage, and a second electrode connected to the output node; (Para 197. Fig. 6B. T12 connected to QB1, a first electrode configured to receive the first voltage VEH, and a second electrode connected to the output node EM[n]
a ninth transistor including a first gate electrode connected to the second pull- down control node, a first electrode connected to the output node, and a second electrode configured to receive the second voltage; and a third capacitor including a first electrode connected to the second pull-down control node, and a second electrode connected to the output node. (Para 197. Fig. 6B. T11 connected to second pull-down control node Q1. a first electrode connected to the output node EM[n], and a second electrode configured to receive the second voltage through T12)
Regarding claim 9, Park teaches a display device comprising: a display panel; (Para 42. Fig. 1 shows display panel 100)
a scan driver configured to output a scan signal to a scan line of the display panel; (Para 62-64. Fig. 1 Scan driver 320)
a data driver configured to output a data voltage to a data line of the display panel; (Para 67. Fig. 1. Data driver 400)
and an emission driver including an emission driving circuit configured to output an emission signal to an emission line of the display panel, (Para 62-64. Fig. 1. Emission driver 310)
wherein the emission driving circuit includes: a pull-up controller configured to transmit a first voltage to a first pull-up control node in response to an input signal, (Para 195. Fig. 6A and 6B. 6B shows a stage of an emission driving circuit. T14 is the first pull-up controller. Para 197. T14 transmits VEH to Q11)
to control a voltage of a second pull-up control node in response to a voltage of the first pull-up control node and a clock signal, (Para 197. Fig. 6B. QB1 gets ECLK based on voltage at Q11 and ECLK)
and to transmit a second voltage to a third pull-up control node in response to the voltage of the second pull-up control node; (Para 197. Fig. 6B. T16 transmit second voltage VEH to QB1 to change the voltage of voltage of the second pull-up control node to a VEH at a third pull-up control node. So the second pull up control node is also the third pull up control node)
a pull-down controller configured to transmit the input signal to a second pull- down control node in response to the input signal and the clock signal; (Para 197-198. Fig. 6B. T13 transfer input signal EVST to Q12, then transfer to Q1 which is the pull down node through TA which is the pull down controller.)
and an output circuit configured to output the emission signal from an output node in response to a voltage of the third pull-up control node and a voltage of the second pull-down control node. (Para 197. Fig. 6B. The (1-1)-st gate transistor T11 may pull up an output terminal in response to a signal of a Q1 node, and the (1-2)-nd gate transistor T12 may pull down an output terminal in response to a signal of a QB1 node. So the output Em is based on the voltage of the third pull-down control node and a voltage of the second pull-down control node.)
Regarding claim 10, refer to rejection for claim 2.
Regarding claim 14, refer to rejection for claim 6.
Regarding claim 15, Park teaches an electronic device comprising: a processor configured to output a control signal and input image data; (Para 53. a personal computer providing output the controller)
a display panel; (Para 42. Fig. 1 shows display panel 100)
a scan driver configured to output a scan signal to a scan line of the display panel; (Para 62-64. Fig. 1 Scan driver 320)
a data driver configured to output a data voltage to a data line of the display panel; (Para 67. Fig. 1. Data driver 400)
an emission driver including an emission driving circuit configured to output an emission signal to an emission line of the display panel; (Para 62-64. Fig. 1. Emission driver 310)
and a controller configured to control the scan driver, the data driver, and the emission driver based on the control signal and the input image data, (Para 51. Fig. 1. Controller 200)
wherein the emission driving circuit includes: a pull-up controller configured to transmit a first voltage to a first pull-up control node in response to an input signal, (Para 195. Fig. 6A and 6B. 6B shows a stage of an emission driving circuit. T14 is the first pull-up controller. Para 197. T14 transmits VEH to Q11)
to control a voltage of a second pull-up control node in response to a voltage of the first pull-up control node and a clock signal, (Para 197. Fig. 6B. QB1 gets ECLK based on voltage at Q11 and ECLK)
and to transmit a second voltage to a third pull-up control node in response to the voltage of the second pull-up control node; (Para 197. Fig. 6B. T16 transmit second voltage VEH to QB1 to change the voltage of voltage of the second pull-up control node to a VEH at a third pull-up control node. So the second pull up control node is also the third pull up control node)
a pull-down controller configured to transmit the input signal to a second pull-down control node in response to the input signal and the clock signal; (Para 197-198. Fig. 6B. T13 transfer input signal EVST to Q12, then transfer to Q1 which is the pull down node through TA which is the pull down controller.)
and an output circuit configured to output the emission signal from an output node in response to a voltage of the third pull-up control node and a voltage of the second pull- down control node. (Para 197. Fig. 6B. The (1-1)-st gate transistor T11 may pull up an output terminal in response to a signal of a Q1 node, and the (1-2)-nd gate transistor T12 may pull down an output terminal in response to a signal of a QB1 node. So the output Em is based on the voltage of the third pull-down control node and a voltage of the second pull-down control node.)
Regarding claim 16, refer to rejection for claim 2.
Regarding claim 20, refer to rejection for claim 6.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20250104649 A1), further in view of Kimura et al. (US 20230298517 A1).
Regarding claim 7, Park already teaches the emission driving circuit of claim 1, However Park does not teach at least one transistor of a plurality of transistors included in the emission driving circuit includes a first gate electrode and a second gate electrode.
However Kimura teaches one transistor includes a first gate electrode and a second gate electrode. (Para 160, 164. Fig. 1A shows MN4 with front and back gates.)
Therefore it would have been obvious to one with ordinary skill, before the effective filing date of the invention, to modify Park with Kimura to teach at least one transistor of a plurality of transistors included in the emission driving circuit includes a first gate electrode and a second gate electrode in order to improve device performance by reducing leakage current with a dual gate transistor configuration.
Regarding claim 8, Park and Kimura already teach the emission driving circuit of claim 7,
And Kimura further teaches wherein the second gate electrode of the at least one transistor is connected to the first gate electrode of the at least one transistor. (Para 160, 164. Fig. 1A. The gates are connected through the transistor body)
Allowable Subject Matter
Claims 3-5, 11-13 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HANG LIN whose telephone number is (571)270-7596. The examiner can normally be reached Monday-Friday, 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae can be reached at 571-272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HANG LIN/Primary Examiner, Art Unit 2626