DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final communication in response to communication filed 5/7/25
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 8, 10, 16 rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chong et al 7200769.
With respect to claim 8, figure 7 and 11 of Chong et al. disclose a method, comprising:
Generating [751] a feedback signal [Upndwn] according to a first clock signal [System CLK];
Adding [couter760] a logic value of the feedback signal to an accumulated value [Up down counter];
Adjusting [count to control] a controlling signal [Ctl[5:0]]] according to the accumulated value;
Generating [706] a first enable signal [CLKIN] according to the first clock signal; and
delaying [710,720,730,740] the first enable signal according to the controlling signal.
With respect to claim 10, figure 7 and 11 of Chong et al. disclose the method of claim 8, further comprising:
Generating a second enable signal [Delayed clock] according to the first clock signal; and
aligning [phase detector 750] a first edge of the first clock signal [System CLK] with a second edge of the second enable signal [Delayed clock].
With respect to claim 16, figure 7 and 11 of Chong et al. disclose a device, comprising:
a dividing circuit [706] configured to receive a first clock signal [system CLK] to generate a first enable signal [CLKIN];
a delaying circuit [710,720,730, 740] configured to receive the first enable signal to generate a second enable signal [Delayed clock]; and
a gating circuit [770, fig. 11] configured to receive the first clock signal to generate a third
enable signal [top input 1122], and comprising:
a first logic element [1122] configured to receive each of the first clock signal [by way of 1117 and ] and
the third enable signal, to output a gated clock signal [CLKOUT].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 6-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11909399. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims describe different combinations of the same subject matter with slightly different language.
Claim 1 is disclosed by claims 1, 5, and 16.
Claim 2 is disclosed by claims 4 and 5.
Claim 3 is disclosed by claims 20.
Claim 6 is disclosed by claims 3, 6, and 7.
Claim 7 is disclosed by claims 13-15, 17-19.
Claim 8 is disclosed by claims 11 and 13.
Claim 9 is disclosed by claims 1, 12, 16, 20
Claim 10 is disclosed by claims 1, 3, 9-12, and 16.
Claim 11 is disclosed by claims 7, 13, 15, and 20.
Claim 12 is disclosed by claims 6, 7, 13, 15.
Claim 13 is disclosed by claims 6-9, 11, 17, 20.
Claim 14 is disclosed by claims 9, 13-15, 19.
Claim 15 is disclosed by claims 15 and 19.
Claim 16 is disclosed by claims 1-3, 6, 8-11, 13-20
Claims 1-4, 6-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12323151. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims describe different combinations of the same subject matter with slightly different language.
Claim 1 is disclosed by claims 2, 3, 4. Providing a clock to a processor is an intended use.
Claim 2 is disclosed by claims 1,5,6,10-14, and 16
Claim 3 is disclosed by claims 4 and 8.
Claim 4 is disclosed by claims 1, 3, 4, and 6.
Claim 6 is disclosed by claims 5, 16, 13, 16,17, and 19.
Claim 7 is disclosed by claims 12-14 and 16.
Claim 8 is disclosed by claims 5,6, 10-14 16-20.
Claim 9 is disclosed by claims 1, 2, 4 and 9.
Claim 10 is disclosed by claims 7 and 8.
Claim 11 is disclosed by claims 11 and 12.
Claim 12 is disclosed by claims 12, and 14-16.
Claim 13 is disclosed by claims 1, 5, 13, and 16-18.
Claim 14 is disclosed by claims 12 and 14.
Claim 15 is disclosed by claims 12 and 15.
Claim 16 is disclose by claims 1, 2, 4, 5, 8, 9, and 16-20
Claim 17 is disclosed by claims 3 and 4.
Claim 18 is disclosed by claims 1,3, 6.
Claim 19 is disclosed by claims 5 and 6.
Claim 20 is disclosed by claims 13-17, 19.
Claim 5 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12323151 and 11909399 in view of Desoli et al. 20200310758.
With respect to Claim 5 the above claims is disclose the circuit except for the logic element being and “AND” logic gate.
However, figure 40 of Desoli et al. discloses a gated clock arrangement as claimed and seen in the current applicant using an “AND” logic gate to produce the gated clock signal.
It would have been obvious to one skilled in the art before the effective filing date to use an “AND” logic element for the gated clock as it’s a known technique in the art.
Allowable Subject Matter
Claims 1-7 are allowed upon filing a terminal disclaimer.
Claims 9, 11-15, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. A terminal disclaimer is required.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached on 571-270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN JAGER/
Primary Examiner, Art Unit 2842
7/11/26
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