DETAILED ACTION
Claims 1-7 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/7/25 has been considered by the examiner.
Drawings
The drawings were received on 5/7/25. These drawings are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0025936 to Morikawa.
As per claim 1, Morikawa substantially teaches the claimed controller (Figure 6 and 8 element 202), configured to perform a serial communication (Paragraph [0020, 0022]) with a target (Figure 6, 8 element 111), comprising: an arithmetic circuit (Fig 3 element 201 CPU) configured to calculate a CRC value of a signal sequence including an address of the target, an address of a storage circuit of the target, and a write data when the controller performs data writing to the storage circuit (Paragraph [0042]); and a communication circuit (main control ASIC 202) configured to transmit the address of the target, the address of the storage circuit, the write data, and the CRC value to the target (Paragraph [0065]) , wherein the arithmetic circuit is configured to hold (temporary storage unit) a calculation value during a calculation when a positive acknowledgment is returned (Paragraph [0051] ACK) from the target (Paragraph [0067]).
While the prior art does not use the specific terms used in the claim language such as target the elements 203 and 111 of figure 3 are the intended recipient of the message being sent. Although the prior art is not specific as to where the CRC is actually calculated it is clearly stated that the CRC is being calculated. Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application that these would be functionally equivalent (Paragraphs [0044] and [0050]).
As per claim 6, Morikawa substantially teaches the elements of claim 1 and further teaches communication system, comprising the controller of Claim 1 and the target, wherein the target is configured to verify whether there is an error in the address of the target, the address of the storage circuit, and the write data received by the target using the CRC value (Paragraph [0053] performs a CRC-based error detection like when performing an ordinary write operation in FIG. 6. The slave station transmits the ACK command or the NACK command to the main station according to the result of the error detection. Based on the received command, the main station determines whether the communication has succeeded or failed).
Therefore, since the received data contains data and address with CRC protection (Fig 8) it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application to have used the CRC appended to the signal to detect errors in any data sent with the CRC including the address.
Claim(s) 2, is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0025936 to Morikawa in view of JP 2010016751 A to Yamamoto (machine translation provided by applicant).
As per claim 2 Morikawa substantially teaches the elements of claim 1 and
the target and the controller are connected via a first signal line (See figures 6 and 8),
However, Morikawa fails to mention the clock in the disclosed circuitry. In an analogous art Yamamoto teaches (CRC arithmetic circuit is constituted having a logic circuit that calculates a CRC code from transmission data through parallel processing based upon a predetermined arithmetic expression derived by analyzing an arithmetic step of calculating the CRC code from the transmission data through serial processing) a clock signal output from the controller and a second signal line configured to send a serial data signal synchronized with the clock signal, and the arithmetic circuit is configured to receive the serial data signal (Paragraph [0029], “The output control block 306 is a means for reading out the data stored in the FIFO block 305 in parallel, 8 bits at a time, based on the second clock signal FCLK, and outputting this to the CPU as an image pickup signal DATA. The output control block also transfers a frame synchronization signal … and a third clock signal PCLK … to the CPU in addition to the image signal DATA.) Therefore, it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application to have used the clock synchronization with the data of Yamamoto with the circuit of Morikawa as suggested by Yamamoto in order to prevent transmission errors (Paragraph [0002]).
Allowable Subject Matter
Claims 3-5 and 7 are allowable over the prior arts.
The following is a statement of reasons for the indication of allowable subject matter: The present invention pertains to detection of errors in a communication system.
The claimed invention (claim 3 as the independent claim) recites in part:
“…an arithmetic circuit configured to calculate a CRC value of a signal sequence including an address of the target, an address of a storage circuit of the target, and a read data when the controller performs data reading from the storage circuit; and
a communication circuit configured to transmit the read data and the CRC value to the controller, wherein the arithmetic circuit includes a first arithmetic circuit and a second arithmetic circuit,
the first arithmetic circuit and the second arithmetic circuit are each configured to perform CRC calculations on the received signal sequence,
the first arithmetic circuit is configured to perform a reset operation at a start condition of the serial communication, and
the second arithmetic circuit is configured to receive a calculation value during a calculation performed by the first arithmetic circuit at a timing when the target returns a positive acknowledgment to the address of the target that was first received, and to avoid a reset operation at the start condition of the serial communication.”
The prior arts of record teach:
US 2018/0203759 to Shaffer et al. teach detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code.
US 2010/0188972 to Knapp CRC checksum field could provide error protection for a message in the current data frame. The network controller in the sending node computes the checksum for the length field, the address field, and the data field, and sends the result in the CRC field. Any receiving node computes another checksum for the same fields and compares the result with the value in the received CRC field. If they are the same, the message has been received properly.
However, the prior arts fail to teach the claimed specifics of:
“…a communication circuit configured to transmit the read data and the CRC value to the controller, wherein the arithmetic circuit includes a first arithmetic circuit and a second arithmetic circuit,
the first arithmetic circuit and the second arithmetic circuit are each configured to perform CRC calculations on the received signal sequence,
the first arithmetic circuit is configured to perform a reset operation at a start condition of the serial communication, and
the second arithmetic circuit is configured to receive a calculation value during a calculation performed by the first arithmetic circuit at a timing when the target returns a positive acknowledgment to the address of the target that was first received, and to avoid a reset operation at the start condition of the serial communication.”
As such, modification of the prior arts of record can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior arts. Therefore, it is not clear that one of ordinary skill in the art at the time of the invention would have made the necessary modifications to the prior arts of record to encompass the limitations set forth in the present claims. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate or render obvious the combined specifics of the claimed invention. Hence, claims 3-5 and 7 are allowable over the prior arts of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA H BRITT whose telephone number is (571)272-3815. The examiner can normally be reached Monday - Thursday 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CYNTHIA H. BRITT
Primary Examiner
Art Unit 2111
/CYNTHIA BRITT/Primary Examiner, Art Unit 2111
Prosecution Insights