Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/23/2025 in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 13-27, and 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Brandt et al. (US Pat. Pub. 20210216235; hereinafter referred to as Brandt) in view of Kimmery et al. (US Pat. Pub. 20070022244; hereinafter referred to as Kimmery).
As per claims 1, 16, and 20:
Brandt teaches a memory system (Brandt par. 0017, computing system 100), method (Brandt par. 0044, method 300), and non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors (Brandt par. 0060, non-transitory machine-readable storage medium) to:
one or more memory devices (Brandt par. 0020, memory devices 130); and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to (Brandt par. 0024, controller 115 with processor coupled to memory devices 130):
initiate a first background scan of a first plurality of memory cells of the memory system at a first start time of a first scheduled window for performing one background scan of a plurality of background scans the first scheduled window having a fixed duration (Brandt par. 0023, 0039-0040, start a scan operation on a plurality of memory cells, wherein interval value 122 describes the duration of the scan operation);
Brandt does not explicitly disclose to determine whether a first duration to perform the first background scan is greater than or less than the fixed duration and initiate a second background scan for a second plurality of memory cells of the memory system after determining whether the first duration is greater than or less than the fixed duration. However, Kimmery discloses determine whether a first duration to perform the first background scan is greater than or less than the fixed duration (Kimmery par. 0023, determine an error-scrub access is less than a time interval) and initiate a second background scan for a second plurality of memory cells of the memory system after determining whether the first duration is greater than or less than the fixed duration (Kimmery par. 0023, start a second error-scrub access after determining a first error-scrub access is less than the time interval).
Brandt and Kimmery are analogous arts because they are in the same field of endeavor of memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kimmery’s starting a second error-scrub access operation after a first error-scrub access is less than a time interval to the memory system, method, and non-transitory computer-readable medium of Brandt. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it reduces access latency for applications accessing the memory device (Kimmery par. 0031).
As per claims 2, 17, and 21:
Brandt and Kimmery further teach the memory system of claim 1, the method of claim 16, and the non-transitory computer-readable medium of claim 20 wherein the processing circuitry is further configured to cause the memory system to: initiate a timer based at least in part on determining that the first duration is less than the fixed duration, a value of the timer being based at least in part on a difference between the fixed duration and the first duration (Kimmery par. 0023, initiate a pause, wherein the pause time interval is the difference between the error-scrub access and the time interval), wherein the second background scan is initiated after the timer expires (Kimmery par. 0023, the second error-scrub access starts after the pause).
As per claims 3, 18, and 22:
Brandt and Kimmery further teach the memory system of claim 2, the method of claim 17, and the non-transitory computer-readable medium of claim 21 wherein the processing circuitry is further configured to cause the memory system to: determine that the timer expires, wherein the second background scan is initiated after the timer expires (Kimmery par. 0023, the second error-scrub access starts after the pause).
As per claims 4 and 19:
Brandt and Kimmery further teach the memory system of claim 2 and the method of claim 17, wherein the second background scan is initiated at a second start time of a second scheduled window that occurs after the timer expires, the second scheduled window having the fixed duration (Kimmery par. 0023, second error-scrub access starts at a second start time after the pause. Please note the error-scrub accesses are distributed throughout the time interval, thus each having a fixed duration as stated in Kimmery par. 0023).
As per claim 13:
Brandt and Kimmery further teach the memory system of claim 1, wherein the processing circuitry is further configured to cause the memory system to:
determine the fixed duration for performing background scans based at least in part on a scan instance time for performing background scans of each memory cell of the memory system (Brandt par. 0032, interval 122 represents amount of time to lapse for initiating scan operations).
As per claim 14:
Brandt and Kimmery further teach the memory system of claim 1, wherein the first background scan comprises scanning the first plurality of memory cells for correctable errors (Brandt par. 0011, scan operations are used to decode data to correct any errors).
As per claim 15:
Brandt and Kimmery further teach the memory system of claim 1, wherein the memory system comprises a quad-level cell (QLC) memory system (Brandt par. 0022, memory devices 130 include quad-level cells).
As per claims 23 and 29:
Brandt teaches a memory system (Brandt par. 0017, computing system 100), and a method (Brandt par. 0044, method 300), comprising:
one or more memory devices (Brandt par. 0020, memory devices 130); and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to (Brandt par. 0024, controller 115 with processor coupled to memory devices 130):
initiate, at a first start time, a first background scan of a first plurality of memory cells of the memory system, the first start time associated with a first scheduled window having a fixed duration that is based at least in part on a time for performing a plurality of background scans (Brandt par. 0023, 0039-0040, start a scan operation on a plurality of memory cells, wherein interval value 122 describes the duration of the scan operation).
Brandt does not explicitly disclose initiate, at a second start time after the first scheduled window, a second background scan for a second plurality of memory cells of the memory system, wherein the second start time is associated with expiration of a timer or completion of the first background scan based at least in part on whether a first duration for performing the first background scan is greater than or less than the fixed duration. However, Kimmery discloses initiate, at a second start time after the first scheduled window, a second background scan for a second plurality of memory cells of the memory system, wherein the second start time is associated with expiration of a timer or completion of the first background scan (Kimmery par. 0023, start a second error-scrub access after determining a first error-scrub access is less than the time interval or a pause timer) based at least in part on whether a first duration for performing the first background scan is greater than or less than the fixed duration (Kimmery par. 0023, determine an error-scrub access is less than a time interval).
Brandt and Kimmery are analogous arts because they are in the same field of endeavor of memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Kimmery’s starting a second error-scrub access operation after a first error-scrub access is less than a time interval to the memory system and method of Brandt. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it reduces access latency for applications accessing the memory device (Kimmery par. 0031).
As per claims 24 and 30:
Brandt and Kimmery further teach the memory system of claim 23 and the method of claim 29, wherein the processing circuitry is further configured to cause the memory system to: initiate the timer based at least in part on determining that the first duration is less than the fixed duration, a value of the timer based at least in part on a difference between the fixed duration and the first duration, (Kimmery par. 0023, initiate a pause, wherein the pause time interval is the difference between the error-scrub access and the time interval), wherein the second start time is after the timer expires (Kimmery par. 0023, the second error-scrub access starts after the pause).
As per claim 25:
Brandt and Kimmery further teach the memory system of claim 24, wherein the processing circuitry is further configured to cause the memory system to:
determine that the timer expires, wherein the second background scan is initiated after the timer expires (Kimmery par. 0023, the second error-scrub access starts after the pause).
As per claim 26:
Brandt and Kimmery further teach the memory system of claim 24, wherein the second start time is associated with a second scheduled window that occurs after the first scheduled window, the second scheduled window having the fixed duration (Kimmery par. 0023, second error-scrub access starts at a second start time after the pause. Please note the error-scrub accesses are distributed throughout the time interval, thus each having a fixed duration as stated in Kimmery par. 0023).
Claims 5 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Brandt-Kimmery in further view of Cordero et al. (US Pat. Pub. 20140334225; hereinafter referred to as Cordero).
As per claim 5:
Brandt and Kimmery teach the memory system of claim 1.
Brandt and Kimmery do not explicitly disclose wherein, to determine whether the first duration is greater than or less than the fixed duration, the processing circuitry is configured to cause the memory system to: determine that the first duration is greater than the fixed duration, wherein the second background scan is initiated after the first background scan is complete based at least in part on determining that the first duration is greater than the fixed duration. However, Cordero discloses wherein, to determine whether the first duration is greater than or less than the fixed duration, the processing circuitry is configured to cause the memory system to: determine that the first duration is greater than the fixed duration (Cordero par. 0033, refresh cycle is outside of a refresh time threshold, wherein it is interpreted that the cycle is greater than the threshold), wherein the second background scan is initiated after the first background scan is complete based at least in part on determining that the first duration is greater than the fixed duration (Cordero par. 0033, a high priority refresh is requested after determining the refresh cycle is outside of a refresh time threshold).
Brandt, Kimmery, and Cordero are analogous arts because they are in the same field of endeavor of memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cordero’s starting an operation after a comparison of time thresholds with the memory system of Brandt-Kimmery because the claimed invention uses a known design incentive and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it would allow for the scan cadence to be maintained.
As per claim 27:
Brandt and Kimmery teach the memory system of claim 23.
Brandt and Kimmery do not explicitly disclose wherein, to determine whether the first duration is greater than or less than the fixed duration, the processing circuitry is configured to cause the memory system to: determine that the first duration is greater than the fixed duration, wherein the second start time is after the first background scan is complete based at least in part on determining that the first duration is greater than the fixed duration. However, Cordero discloses wherein, to determine whether the first duration is greater than or less than the fixed duration, the processing circuitry is configured to cause the memory system to: determine that the first duration is greater than the fixed duration (Cordero par. 0033, refresh cycle is outside of a refresh time threshold, wherein it is interpreted that the cycle is greater than the threshold), wherein the second start time is after the first background scan is complete based at least in part on determining that the first duration is greater than the fixed duration (Cordero par. 0033, a high priority refresh is requested after determining the refresh cycle is outside of a refresh time threshold).
Brandt, Kimmery, and Cordero are analogous arts because they are in the same field of endeavor of memory devices. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Cordero’s starting an operation after a comparison of time thresholds with the memory system of Brandt-Kimmery because the claimed invention uses a known design incentive and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since it would allow for the scan cadence to be maintained.
Allowable Subject Matter
Claims 6-12 and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The additional prior arts not made of record and have not been relied upon are considered pertinent to applicant’s disclosure as follows:
Schuh et al. (US Pat. Pub. 20230251779) discloses a determination that a memory component subjected to a background data integrity scan does not satisfy a threshold. Schuh further discloses that the background data integrity scan is delayed when an activity threshold is not met.
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/JEFFREY ANDREW YANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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