DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 02/13/2025. Claims 1-22 are pending in the Application, of which Claims 1, 9 and 17 are independent.
Continuity Priority information
The present Application 19204228 filed 05/09/2025 Claims Priority from Provisional Application 63652537 filed 05/28/2024.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 9 and 17, 6, 8, 14, 16, 22, the limitation “generate a second set of bits based at in part on inputting the first set of bits into an error correction encoder” is indefinite. It is unclear how one is able to generate a second set of bits by partially inputting a first set of bits.
Claims 1, 9 and 17, the limitation “wherein the meta data bits are stored in at least a portion of the first memory space” is indefinite, because the term “in at least a portion” fails to clearly define the memory space.
Any Claims not specifically mentioned above are also rejected due to their dependency on a rejected claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suh et al. (PgPub. US 20240126438) Pub. Date: 2024-04-18.
Regarding independent Claims 1 and 17, Suh discloses methods, and devices for memory systems that support metadata, comprising:
processing circuitry coupled with the one or more memory devices; [0035] FIG. 1 illustrates an apparatus 100 incorporating a host 110, memories 150, and channels 190 coupling the host 110 and the memories 150.
the memory system to receive a write command associated with a first set of bits, comprising data bits and meta data bits;
FIG. 3A. [0055] A write command issued by the host to the memory device of method 300 causes the memory device to perform operations, at block 302, of the memory device receiving data from the host via at least one data connection into a first plurality of registers. For example, data may be stored in data registers 182A-K by processing signals received over the data DQ[0:7] channel.
Additionally, at block 304, the memory device receives metadata from the host via at least one non-data connection into a second plurality of registers. For example, metadata may be stored in the metadata registers 181A-N by processing signals received over the non-data read strobe RDQS channel.
generate a second set of bits based at in part on inputting the first set of bits into an error correction encoder, store the second set of bits in a memory array of the memory system, wherein the memory array comprises a first memory space allocated for meta data and a second memory space allocated for data.
FIG. 2B illustrates apparatus 100 having the host 110, the memory 150, and the channel 190. [0051] For example, in a write operation, the link ECC encoder 136 may generate a link ECC associated with a block of data to be written (e.g., write data) into the memory 150. The host 110 may provide the write data to the memory 150 via DQs signal connections (e.g., data connections in the channel 190) and provide the link ECC to the memory 150 via a signal connection of the read data strobe RDQS (e.g., non-data connections in the channel 190).
[0044] Information transmitted across the channel 190 may be stored in registers in the memory I/O module 160 of the memory 150 as a temporary or short-term storage location prior to longer-term storage in the memory array 175. The memory I/O module 160 may include first and second registers for storing the data (e.g., user data or application data) and metadata, respectively. A first plurality of registers 182A-K store data; and a second plurality of registers 181A-N store the metadata.
Regarding independent Claim 9, Suh discloses the same limitations as applied to claims 1 and 17, above, and in addition, the memory system to receive a read command associated with data bits;
[0057] An operation for executing a read command involving data and metadata by a memory device is described in FIG. 3B. A read command issued by the host to the memory device of method 300 causes the memory 150 to perform a read operation.
At block 352 metadata is received from the memory array corresponding to the read address into a second plurality of registers.
At block 354, receiving of data from the memory array corresponding to a read address into a first plurality of registers. In some embodiments, the metadata is loaded into the second set of registers before normal data (e.g., data located in columns 0x00-0x3B) is accessed.
In some embodiments, blocks 352 and 356 may be executed sequentially during a read operation to retrieve data and metadata at the same time from a memory device to a host. When a certain amount of data is accumulated in the registers, such as the registers being full or the requested data has been stored in the registers, the data may be transmitted from the registers through the channel 190 to the host.
At block 356, the data from the first plurality of registers is transmitted to the host over at least one data connection. For example, the contents of the data registers 182A-K may be modulated onto the data DQ[0:7] connection of channel 190 and received at the memory controller 130 of host 110.
At block 358, the data from the second plurality of registers is transmitted to the host over at least one non-data connection.
Regarding Claims 2-4, 10-12, 18-20, Suh discloses enabling an error correction mode at the memory system; [0051] The apparatus 100 may include a link ECC function to detect/correct errors arising from data transmissions in the channel 190. The memory I/O module 160 may include a memory link ECC decoder 161 and a memory link ECC encoder 162. Link ECC information may be attached during transit over the channel 190 and verified at either the host 110 or the memory 150 and then discarded. For example, in a write operation, the link ECC encoder 136 may generate a link ECC associated with a block of data to be written (e.g., write data) into the memory 150. The host 110 may provide the write data to the memory 150 via DQs signal connections (e.g., data connections in the channel 190) and provide the link ECC to the memory 150 via a signal connection of the read data strobe RDQS (e.g., non-data connections in the channel 190).
Regarding Claims 5, 6, 13, 14, 21, 22, Suh discloses update a state of one or more circuit components of the error correction encoder to one of an activated state or a deactivated state based at least in part on receiving the second signaling. [0047] The apparatus 100 may implement the system ECC function to detect/correct errors arising in performing computing functions (e.g., operating with the at least one processor 120). The system ECC function may be particularly useful for applications with low error tolerance, such as automotive applications. In some examples, the system ECC encoder 132 may generate system ECC for a block of data and the ECC associated with the block of data, such as by attaching the ECC bits to the block of data. The memory controller 130 may send the block of data to other modules, such as the at least one processor 120 and/or the memory 150, along with the system ECC.
Regarding Claims 7, 8, 15, 16, Suh discloses activate a second error correction encoder based at least in part on receiving the second signaling, and activate a second error correction decoder’ [0046] The host 110 may be configured to perform multiple ECC functions. To support a system ECC function, the host 110 may include a system ECC memory 137. The memory controller 130 may be coupled to the system ECC memory 137 via a bus system 116. The memory controller 130 may further include a system ECC decoder 131 and a system ECC encoder 132. The controller PHY modules 134 may include a link ECC decoder 135 and a link ECC encoder 136.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: September 25, 2026
Non-Final Rejection 20260925
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
