Response to Arguments
Applicant's arguments filed 04/08/2026 have been fully considered but they are not persuasive. Applicant argued that “the control transistors of Choi correspond to transistors of a pixel circuit, particularly transistors connected to the light emitting element of the pixel circuit. In contrast, the claimed switching transistors correspond to transistors connected to a sensor, particularly to a light receiving element of the sensor, which is incorrect. As claimed, switching transistors (Choi et al., T6, T8) connecting the light receiving elements (ED1, ED2). As combination of Kim at al. and Choi et al,. switching transistors (Choi et al., T6, T8) connecting the light receiving elements (ED1, ED2) to the sensor circuit (see Kim et al. fig. 4, a sensing circuit (Kim et al. optical sensor PS).
Applicant also argued that Kim and Choi fail to discloses control line for controlling the “switching transistor” overlaps, in a plan view, a capacitor or transistor” of the pixel circuit, which is incorrect. As mention above, the combination of Kim et al. Choi et al., discloses “switching transistor”; Therefore, the combination of Kim et al. and Choi et al., discloses the sensor circuit comprising a sensor transistor; at least one of the control lines overlapping with at least one of the first transistor and the capacitor in a plan view (Kim et al. fig. 4, A plurality of pixels PX. Each of the pixels PX may include a light-emitting element EL of FIG. 4. Each of the optical sensors PS may be connected to one of the first through n-th scan lines SL1 through SLn, one of the read-out lines ROL, and the power supply voltage lines VL. And/or An area where the pixel electrode 170 and the organic light-emitting layer 175 overlap with each other may be defined as an emission area emitting light, and the color of the light may differ from one pixel PX to another pixel PX) (Choi et al. fig. 4, switching transistor T6, T8). Further more, the combination of Kim et al. and Choi et al., discloses control lines configured to control operations of the switching transistors ([0119] The first and second control transistors T6 and T8 can be controlled by the mode selection signal Sel supplied to the mode control line SEL, and can be turned on or turned off. The first and second control transistors T6, T8 can be turned on at different voltages) (when the mode selection signal Sel is the second gate-on-voltage VON2, the first control transistor T6 can be turned off, thus the driving transistor DT and the first emitting element ED1 cannot be connected. The second gate-on-voltage VON2 can correspond to a first gate-off-voltage for turning off the first control transistor T6.).
To further assist the Applicant with the guidance with claim language interpretations so that the Applicant can add further/more details limitations from the specification to the claims to overcome the prior arts, the Examiner is presenting MPEP, section 2111, Claim Interpretation; Broadest Reasonable Interpretation as follow: “The court explained that “reading a claim in light of the specification, to thereby interpret limitations explicitly recited in the claim, is a quite different thing from reading limitations of the specification into a claim,' to thereby narrow the scope of the claim by implicitly adding disclosed limitations which have no express basis in the claim.” The court found that applicant was advocating the latter, i.e., the impermissible importation of subject matter from the specification into the claim.). See also In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997) (The court held that the PTO is not required, in the course of prosecution, to interpret claims in applications in the same manner as a court would interpret claims in an infringement suit. Rather, the “PTO applies to verbiage of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art, taking into account whatever enlightenment by way of definitions or otherwise that may be afforded by the written description contained in applicant's specification.”)”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0317007) in view of Choi et al. (US 2025/0140199).
Regarding claims 1, 20 Kim et al. US 2023/0317007, figs. 1, 4-6, discloses a display device comprising: a pixel (PX) comprising a pixel circuit and a light emitting element (EL) connected to the pixel circuit (PX), the pixel circuit comprising a first transistor (T2, T2, T5) and a capacitor (Cst); a sensor (PS) comprising a sensor circuit, light receiving elements (PD), the sensor circuit comprising a sensor transistor; at least one of the control lines overlapping with at least one of the first transistor and the capacitor in a plan view (fig. 4, A plurality of pixels PX. Each of the pixels PX may include a light-emitting element EL of FIG. 4. Each of the optical sensors PS may be connected to one of the first through n-th scan lines SL1 through SLn, one of the read-out lines ROL, and the power supply voltage lines VL. And/or An area where the pixel electrode 170 and the organic light-emitting layer 175 overlap with each other may be defined as an emission area emitting light, and the color of the light may differ from one pixel PX to another pixel PX).
Kim et al. is silent about switching transistors connecting the light receiving elements to the sensor circuit. However, Kim et al. discloses the sensing capacitor Cph may be formed between the first and second nodes N1 and N2. The first electrode of the sensing capacitor Cph may be connected to the sensing anode of the photoelectric conversion element PD, the gate electrode of the first sensing transistor LT1, and the second electrode of the third sensing transistor LT3 through the first node N1, and the second electrode of the sensing capacitor Cph may be connected to the common voltage line through the second node N2. As a result, the sensing capacitor Cph may maintain the difference in electric potential between the first and second nodes N1 and N2.
It would have been obvious to the skilled in the art before the effective filing date of the invention to provide witching transistors connecting the light receiving elements in Kim et al.. as suggested by Choi et al., the motivation in order to the first control transistor T6 connected with the first emitting element ED1 can be turned on by the mode selection signal Sel, the first emitting element ED1 and the driving transistor DT are connected, thus the first emitting element ED1 can emit.
Therefore, the combination of Kim et al. and Choi et al., discloses control lines configured to control operations of the switching transistors ([0119] The first and second control transistors T6 and T8 can be controlled by the mode selection signal Sel supplied to the mode control line SEL, and can be turned on or turned off. The first and second control transistors T6, T8 can be turned on at different voltages) (when the mode selection signal Sel is the second gate-on-voltage VON2, the first control transistor T6 can be turned off, thus the driving transistor DT and the first emitting element ED1 cannot be connected. The second gate-on-voltage VON2 can correspond to a first gate-off-voltage for turning off the first control transistor T6.).
Regarding claim 2, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 1, wherein the control lines extend in a first direction and transversing the pixel (Choi et al. fig. 6, T6 andT8).
Regarding claims 3, 18, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 1, wherein the capacitor comprises a capacitor electrode (Kim et al. US 2023/0317007, figs. 1, 4-6, Cst), and wherein two or less insulating layers are interposed between the capacitor electrode and the control lines in a cross-sectional view (Kim et al., The third gate insulating film 133 may cover the first interlayer insulating film 141 and the second semiconductor layer ACT2 and may insulate the second semiconductor layer ACT2 and the third gate layer GTL3. The third gate insulating film 133 may include the same material as the first gate insulating film 131. In an embodiment, the third gate insulating film 133 is entirely made of a single material and the first gate insulating film 131 is entirely made of the same single material. And Choi et al. display panel 110 according to one embodiment, the circuit element layer disposed on the first substrate 110 can include a plurality of insulating layers stacked on the first substrate 110. For example, the plurality of insulating layers can include a buffer layer 210, a gate insulating layer 220, an interlayer insulating layer 230, a protection layer 240, and a planarization layer 250).
Regarding claim 4, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 3, wherein, in a plan view, a partial section of at least one of the control lines overlaps with about 50% or more of the capacitor in a
second direction, and the control lines roughly extend in a first direction, and wherein the second direction is perpendicular to the first direction (see Kim et al. pars. 133-135, 138, Choi et al. par., 85).
Regarding claim 5, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 4, wherein, in a plan view, the partial section of the at least one of the control lines completely overlaps with the capacitor in the
second direction (see Kim et al. pars. 53, 83, Choi et al. 91-93, 146).
Regarding claim 6, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 1, wherein the switching transistors comprise a first switching transistor configured to connect a first light receiving element to the sensor circuit in response to a first control signal of a first control line, and a second switching transistor configured to connect a second light receiving element to the sensor circuit in response to a second control signal of a second control line, and wherein the first control line overlaps with the capacitor (see Kim fig. 4, and Choi et al. fig. 6, T6, T8, ED1, ED2, Sel), (see Kim et al. pars. 133-135, 138, Choi et al. par., 85).
Regarding claim 7, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 6, wherein, in a plan view, the first control line transverses the capacitor (see Choi et al. fig. 6, T6, T8, Sel).
Regarding claim 8, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 7, wherein the second control line overlaps with an edge portion of the capacitor (Kim et al. figs. 5, 7, pars. 133-135, Choi et al., pars. 64, 85).
Regarding claims 9, 11, 12, 17, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 8, further comprising: a data line configured to transmit a data signal; and a scan line configured to transmit a scan signal,
wherein the pixel circuit further comprises a second transistor configured to transfer the data signal to the first transistor in response to the scan signal, and wherein the first control line overlaps with the scan line (Kim et al. figs. 5, 7, pars. 167, 168, Choi et al., pars. 145, see response above and see rejection of claim 2).
Regarding claim 10, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 6, wherein the second control line does not overlap with the capacitor (Kim et al. figs. 5, 7, pars. 133-135, Choi et al., pars. 64, 85).
Regarding claim 13, 19, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 1, wherein control signals applied to the
control lines change between a first voltage level and a second voltage level in only a
blank period, and have either the first voltage level or the second voltage level in an
active period, and wherein a valid data signal is provided to the pixel in the active period, and the
valid data signal is not provided to the pixel in the blank period (Kim et al., 99, 104).
Regarding claim 14, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 1, further comprising a plurality of sensors comprising the sensor, wherein the control lines are commonly connected to all of the plurality of sensors (see Kim et al., pars., 59, 61, 73, 79, 80).
Regarding claim 15, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 1, wherein the first transistor of the pixel comprises a silicon semiconductor, and the switching transistors of the sensor comprise an oxide semiconductor (see Kim et al. pars. 103, 108, 132, and Choi et al. pars. 79, 107).
Regarding claim 16, the combination of Kim et al. US 2023/0317007, figs. 1, 4-6, and Choi et al. fig. 6, discloses the display device of claim 1, wherein the light emitting element and the light receiving element are at the same layer (see Kim et al. fig. 5, EL and PD, par. 116, 128, 130).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Van N Chow whose telephone number is (571)272-7590. The examiner can normally be reached M-F 10-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Ke can be reached at 5712727776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VAN N CHOW/Primary Examiner, Art Unit 2627
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