DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) are: “controller”, “driver”, “first outputs”, “connection portions” and “reset”, as recited in claims 1-17; and “first outputs” and “reset”, as recited in claims 18-20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hong et al. (US 2023/0197011).
Regarding claim 18
Hong et al. shows the display device comprising:
pixels connected to scan lines (GL/SCAN) and to data lines (DL, see Figs. 1, 3, 6 and 7); and
a scan driver (120) comprising stage circuits for driving the scan lines (see Figs. 4-6), at least one of the stage circuits comprising:
a driver (502, see Fig. 7) for controlling voltages of a first node (Q) and a second node (QB);
first outputs (514) (SCAN(i)-SCAN(i+3)) configured to receive one of scan clock signals (SCCKL), and to output the one of the scan clock signals as an enable scan signal (SCAN(i)-SCAN(i+3)) based on a voltage of one of local nodes (Q/QB, see para. 0209-0210);
connection portions for controlling an electrical connection between the local nodes (Q/QB nodes) and the first node (taken to be same as either Q or QB node) in response to a voltage of a connection control line (taken to be the lines connecting the Q and QB nodes to units 502, 504, 506, 508, 510, 512 and 514); and
a reset (510) configured to supply a voltage at a logic low level to the connection control line (QB node) based on a voltage of the second node (GVSS3) (see para. 0198-0199).
Regarding claim 19
Hong et al. further shows, wherein the connection portions are configured to block the electrical connection between the local nodes and the first node during a period in which the first outputs are configured to output the one of the scan clock signals (taken to be, when the transistors T53 and T52 are turned on by the input reset signal, the transistors discharge or reset the local and first nodes QB, and therefore block electrical connection, see para. 0200-0201).
Regarding claim 20
Hong et al. further shows, the electronic device comprising:
a processor (taken to be inherent to the display device 100 for processing the information from the date driver 120, controller 120, data driver 130, etc., see Fig. 1 and para. 0047); and
display device comprising pixels connected to scan lines (GL/SCAN) and to data lines (DL, see Figs. 1, 3, 6 and 7); and
a driver (502, see Fig. 7) for controlling voltages of a first node (Q) and a second node (QB);
first outputs (514) (SCAN(i)-SCAN(i+3)) configured to receive one of scan clock signals (SCCKL), and to output the one of the scan clock signals as an enable scan signal (SCAN(i)-SCAN(i+3)) based on a voltage of one of local nodes (Q/QB, see para. 0209-0210);
connection portions for controlling an electrical connection between the local nodes (Q/QB nodes) and the first node (taken to be same as either Q or QB node) in response to a voltage of a connection control line (taken to be the lines connecting the Q and QB nodes to units 502, 504, 506, 508, 510, 512 and 514); and
a reset (510) configured to supply a voltage at a logic low level to the connection control line (QB node) based on a voltage of the second node (GVSS3) (see para. 0198-0199).
Allowable Subject Matter
Claims 1-17 are allowed.
The following is an Examiner's Statement of Reasons for Allowance:
Regarding claims 1-17
The prior art of record, including Hong et al. (US 2023/0197011), taken to be the closest prior art noted above, taken alone or in combination does not teach, suggest or render obvious the stage circuit having the combination of elements and structure, along with having the further limitations which include,
connection portions configured to control an electrical connection between the local nodes and the first node in response to the voltage of the connection control line; and a reset connected between the connection control line and a fourth power input terminal for receiving a fourth power, and configured to control an electrical connection between the connection control line and the fourth power input terminal based on the voltage of the second node, as recited in claims 1-17.
Further, even though Hong et al. shows the invention substantially as claimed, as discussed in the above rejections, it does not specifically show or render obvious the limitations of claims 1-17, noted above.
Also, none of the prior art of record teaches the connection portions configured to control an electrical connection between the local nodes and the first node in response to the voltage of the connection control line; and a reset connected between the connection control line and a fourth power input terminal for receiving a fourth power, and configured to control an electrical connection between the connection control line and the fourth power input terminal based on the voltage of the second node, as recited in claims 1-17.
Therefore, it is believed that one of ordinary skilled in the art at the time the invention was filed, would not consider it obvious to modify Hong et al., with any of the prior art of record, to include the limitations as recited in claims 1-17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi et al. (US 2021/0104197), shows a display device (see Fig. 1) comprising: pixels (PX) connected to scan lines (SC/SS) and to data lines (D); and a scan driver (13) comprising stage circuits for driving the scan lines (see Fig. 4), at least one of the stage circuits comprising: a driver (SST1) for controlling voltages of a first node (Q) and a second node (QB); first outputs (SST5-SST6) configured to receive one of scan clock signals (see Fig. 6), and to output the one of the scan clock signals as an enable scan signal based on a voltage of one of local nodes (Q and QB); and a reset, (see the abstract, Figs. 1-10, and para. 0008 and 0059-0196).
Lee et al. (US 2022/0108656), shows a display device comprising: pixels connected to scan lines and to data lines (see Fig. 1); and a scan driver (100) comprising stage circuits for driving the scan lines (see Fig. 9), at least one of the stage circuits comprising: a driver for controlling voltages of a first node (Q) and a second node (QB); first outputs (140) configured to receive one of scan clock signals, and to output the one of the scan clock signals as an enable scan signal based on a voltage of one of local nodes (see Fig. 10); and a reset (see the abstract, Figs. 1-11, and para. 0060-0189).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUHAMMAD N EDUN whose telephone number is (571)272-7617. The examiner can normally be reached Mon-Fri 10:00-6:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BENJAMIN C. LEE can be reached on (571) 272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUHAMMAD N. EDUN/
Primary Patent Examiner
Art Unit 2629
/MUHAMMAD N EDUN/Primary Examiner, Art Unit 2629