DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 2 of U.S. Patent No. 12,300,160. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application claim is broader in every aspect than the patent claim and is therefore an obvious variant thereof.
Claim 1’s limitation of “ A display panel comprising: an element layer including a light emitting element; and a circuit layer including a pixel circuit connected to the light emitting element, wherein the circuit layer includes: a first transistor connected between a first drive voltage line and the light emitting element and configured to operate according to a potential of a first node; a second transistor connected between a data line and a second node; a third transistor connected between the first transistor and the first node; a first capacitor electrode connected to the first node; a second capacitor electrode connected to the second node and facing the first capacitor electrode to form a first capacitor; and a third capacitor electrode facing the second capacitor electrode to form a second capacitor and connected to the first drive voltage line,”
is the same as the limitations of:
“1. A display panel comprising: an element layer including a light emitting element; and a circuit layer including a pixel circuit connected to the light emitting element, wherein the circuit layer includes: a first transistor connected between a first drive voltage line and the light emitting element and configured to operate according to a potential of a first node; a second transistor connected between a data line and a second node; a third transistor connected between the first transistor and the first node; a first capacitor electrode connected to the first node; a second capacitor electrode connected to the second node and facing the first capacitor electrode to form a first capacitor; a third capacitor electrode facing the second capacitor electrode to form a second capacitor and connected to the first drive voltage line;” of claim 1 of the patent number 12,300,160.
Continuing with the rest of claim 1 of the current application, the following limitation of claim 1 of the current application shown below:
“wherein the first to third capacitor electrodes are located on insulating layers different from each other, respectively.”
is similar to claim 2 of the patent number 12,300,160 that reads as the following, wherein the underlines sections are considered for the double patenting:
“the first capacitor electrode is on a first insulating layer, wherein the second capacitor electrode is on a second insulating layer covering the first capacitor electrode, wherein the third capacitor electrode is on a third insulating layer covering the second capacitor electrode, …”.
Therefore, claim 2 teaches a similar limitation wherein first to third capacitor electrodes are on different insulating layers from each other it is just explained in more details.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of the U.S. Patent number 12,300,160, wherein claim 2 of current application differs from claim 2 of the U.S. Patent number 12,300,160 in that the patent has an extra limitation of “and wherein the first and second bridge electrodes are on a fourth insulating layer covering the third capacitor electrode.”
Claim 3, 4, 6-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of the U.S. Patent number 12,300,160, wherein claims 3, 4, 6-17 of current application is the same as claim 3, 4, 6-17 of the U.S. Patent number respectively.
Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of the U.S. Patent number 12,300,160, wherein claim 5 of current application differs from claim 5 of the U.S. Patent number in which the patent does not teach covering the third capacitor electrode and has the limitation of “and the first and second bridge electrodes” extra.
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of the U.S. Patent number 12,300,160, wherein claim 18 of the current application differs from claim 18 of the U.S. Patent because the U.S. Patent has the limitation of “the first horizontal initialization voltage line, the second horizontal initialization voltage line, and the horizontal bias voltage line are on a same layer as the first and second bridge electrodes, and wherein” as extra.
Claim 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 19 and 20 of the U.S. Patent number 12,300,160, wherein claim 19 of the current application is the same as claims 19 and 20 of the U.S. Patent number 12,300,160.
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,300,160 in view of Hwang (U.S. Pub. No. 2022/0358873).
Current Application 19/206,020
Patent No. 12,300,160
20. An electronic device comprising: a display panel; a panel driver configured to drive the display panel; and a driving controller configured to control the panel driver,
See Below after the table. Taught by the prior art reference of Hwang (U.S. Pub. No. 2022/0358873).*1
the display panel comprising: an element layer including a light emitting element; and a circuit layer including a pixel circuit connected to the light emitting element, wherein the circuit layer includes: a first transistor connected between a first drive voltage line and the light emitting element and configured to operate according to a potential of a first node; a second transistor connected between a data line and a second node; a third transistor connected between the first transistor and the first node; a first capacitor electrode connected to the first node; a second capacitor electrode connected to the second node and facing the first capacitor electrode to form a first capacitor; and a third capacitor electrode facing the second capacitor electrode to form a second capacitor and connected to the first drive voltage line,
1. A display panel comprising: an element layer including a light emitting element; and a circuit layer including a pixel circuit connected to the light emitting element, wherein the circuit layer includes: a first transistor connected between a first drive voltage line and the light emitting element and configured to operate according to a potential of a first node; a second transistor connected between a data line and a second node; a third transistor connected between the first transistor and the first node; a first capacitor electrode connected to the first node; a second capacitor electrode connected to the second node and facing the first capacitor electrode to form a first capacitor; a third capacitor electrode facing the second capacitor electrode to form a second capacitor and connected to the first drive voltage line;
wherein the first to third capacitor electrodes are located on insulating layers different from each other, respectively.
Claim 2: “the first capacitor electrode is on a first insulating layer, wherein the second capacitor electrode is on a second insulating layer covering the first capacitor electrode, wherein the third capacitor electrode is on a third insulating layer covering the second capacitor electrode, …”.*2
*1) Claim 20 of this application does not recite the limitation “20. An electronic device comprising: a display panel; a panel driver configured to drive the display panel; and a driving controller configured to control the panel driver,”
The prior art reference of Hwang (U.S. Pub. No. 2022/0358873) teaches an electronic device (display device, [0048], line 1) comprising: a display panel (100); a panel driver (panel driver comprising of elements 300, 400, and 500, [0048]) configured to drive the display panel (Fig. 1 clearly shows that the panel driver having elements 300, 400, and 500 is connected to pixel P and driving the pixel P by applying signals to the gate line GL and data line DL, [0058], lines 1-3 and [0062], lines 1-3) ); and a driving controller (200) configured to control the panel driver ([0056], line 1- [0057], line 6, therefore the driving controller 200 is a part of the panel driver, however, the driving controller 200 is controlling elements of the panel driver like elements 300, 400, and 500, thus it is controlling the panel driver).
Therefore, it would have been obvious to one of ordinary skilled in the art at the time the invention was filed to have added the electronic device and driving controller of Hwang to the display panel of the U.S. Patent application number 12,300,160 because the signals generated by the driving controller to include vertical start signal, gate clock signal, horizontal start signal, load signal, and to generate gamma reference voltage in order to generate an image corresponding to visual information, [0053], [0054], [0055], and [0103], line 1.
*2) Continuing with the rest of claim 20 of the current application, the following limitation of claim 20 of the current application shown below:
“wherein the first to third capacitor electrodes are located on insulating layers different from each other, respectively.”
is similar to claim 2 of the patent number 12,300,160 that reads as the following, wherein the underlines sections are considered for the double patenting:
“the first capacitor electrode is on a first insulating layer, wherein the second capacitor electrode is on a second insulating layer covering the first capacitor electrode, wherein the third capacitor electrode is on a third insulating layer covering the second capacitor electrode, …”.
Therefore, claim 2 teaches a similar limitation wherein first to third capacitor electrodes are on different insulating layers from each other it is just explained in more details.
Allowable Subject Matter
Claims 1-20 overcome the prior art references below and would be allowable if they overcome the double patenting rejection above.
The prior art reference of Shang (U.S. Pub. No. 2022/0343855) describes techniques for driving a display panel using an improved gate driving circuit that can effectively double the output frequency of gate (scan) signals to mitigate visible flicker (especially relevant for OLED displays). The disclosed gate driving circuit includes (i) a frequency-doubling control circuit and (ii) an effective output circuit that includes multiple first shift registers. In operation, the first-stage shift register receives an output control signal (e.g., a frame start signal) and also receives a frequency-doubling control signal that is generated after a preset delay from the output control signal. As a result, even when the output control signal contains one pulse, the shift register(s) can output two pulses, enabling a “2K” pulse output behavior for “K” input pulses, thereby increasing the upper limit of scanning-signal frequency. Shang also discloses related implementations such as optional inverter circuitry and explains that the gate driving circuit may be integrated into a display substrate having gate lines in a display area. A corresponding display device may include the display substrate and an opposite substrate, and the disclosure provides a gate-driving method reflecting the same frequency-doubling concept.
Claim 1 is directed to a display panel pixel circuit architecture: an element layer with a light emitting element, and a circuit layer with a pixel circuit that includes (1) a first transistor between a first drive-voltage line and the light emitting element controlled by a first node, (2) a second transistor between a data line and a second node, (3) a third transistor between the first transistor and the first node, and a particular capacitor stack: a first capacitor between first and second capacitor electrodes (tied to first node and second node), plus a second capacitor formed by the second capacitor electrode facing a third capacitor electrode tied to the first drive-voltage line, where the first–third capacitor electrodes are on different insulating layers.
Shang partially overlaps only at a very high level in that it relates to display-panel driving and scanning signals (gate driving), and it expressly discusses display substrates/devices used for OLED panels and improving scan-signal frequency to avoid flicker. However, Shang does not teach or describe the claimed pixel circuit topology (the three specific transistors connected as claimed), nor the three-electrode/two-capacitor arrangement with electrodes on different insulating layers. Shang’s disclosure is focused on shift-register-based gate driving circuits and a frequency-doubling control signal scheme for scan outputs, rather than the internal circuit structure of each pixel. So, Shang reads most clearly on “display driving / scan-signal generation,” but it does not read on the core limitations of Claim 1 directed to the element layer + pixel circuit transistor/capacitor stack.
Claim 20 is directed to an electronic device including (i) a display panel, (ii) a panel driver configured to drive the panel, and (iii) a driving controller configured to control the panel driver, where the display panel includes the same element layer + pixel circuit + capacitor-electrode stack recited in Claim 1.
Shang overlaps with Claim 20 only in the sense that Shang discloses a display device built from a display substrate (including a gate driving circuit) and an opposite substrate, and it discusses implementing a gate driving method for scanning-signal output. But Shang still does not teach the panel driver + driving controller arrangement in the manner Claim 20 recites; Shang’s focus is on the gate driving circuit itself (frequency-doubling control circuit + shift registers) and its integration into a substrate/device. Most importantly, even if one treats Shang’s gate driving circuit as part of a “driver,” Shang does not disclose the specific pixel circuit of the display panel required by Claim 20 (first/second/third transistor connections; first/second/third capacitor electrodes on different insulating layers forming two capacitors with the stated node/drive-line connections). The missing pixel-level circuitry means Shang does not read on the key structural limitations that define Claim 20’s display panel.
Prior art reference of Yang (U.S. Pub. No. 2023/0267882) Yang discloses a pixel and display device (e.g., a mobile electronic device) directed to improving display driving by reducing or compensating threshold-voltage variation and supporting stable light emission in an OLED display. The disclosure shows a display system including a display panel, a scan driving circuit, a data driving circuit, and a timing controller (see the system block/layout of the panel and drivers). At the pixel level, Yang describes pixel circuits that drive a light-emitting element (OLED) using multiple control signals, including gate/scan signals (e.g., GI, GC, GW) and emission control signals (e.g., EM1, EM2), and includes nodes (e.g., N1, N2) coupled to capacitors (e.g., Cst1 and Cst2) for storing voltages and performing compensation. The figures depict a pixel circuit with a driving transistor and several switching transistors, along with storage capacitors and initialization/test paths (see pixel circuit schematics and timing diagrams). Yang’s approach uses these elements to control the OLED current accurately, including periods for writing data, compensation, initialization, and emission. Overall, Yang focuses on pixel-circuit driving/compensation in an OLED panel within an electronic device architecture including controller and driver circuits.
Claim 1 requires a display panel having (i) an element layer including a light emitting element and (ii) a circuit layer including a pixel circuit connected to the light emitting element. Yang clearly reads on this general framework because it discloses an OLED display panel with pixel circuits driving an OLED light-emitting element and depicts both panel-level and pixel-level structures. However, claim 1 is not just “any pixel circuit.” It specifically requires: (1) a first transistor connected between a first drive-voltage line and the light-emitting element and operating according to a first node; (2) a second transistor connected between a data line and a second node; (3) a third transistor connected between the first transistor and the first node; and, critically, a three-electrode capacitor stack: a first capacitor electrode connected to the first node, a second capacitor electrode connected to the second node forming a first capacitor with the first electrode, and a third capacitor electrode facing the second electrode forming a second capacitor and connected to the first drive-voltage line—where each of the three capacitor electrodes is located on a different insulating layer.
Yang’s pixel circuit (e.g., Fig. 4/6/8A–8E) includes a driving path and storage capacitors (Cst1, Cst2) connected to nodes (N1, N2) and supply lines (e.g., ELVDD/ELVSS), and it includes a data-writing transistor connected to a data line. This overlaps conceptually with having a drive transistor controlled by node potentials and capacitors storing voltage. But Yang does not clearly teach the claim’s distinctive “three capacitor electrodes forming two capacitors (a stacked capacitor structure)” with the third electrode connected to the first drive-voltage line, nor the explicit requirement that the first–third capacitor electrodes are on different insulating layers. Yang shows two capacitors (Cst1/Cst2) and their connections, but it does not expressly disclose the three-electrode stacked configuration or the insulating-layer separation as claimed.
Claim 20 adds system context: an electronic device including a display panel, a panel driver configured to drive the panel, and a driving controller configured to control the panel driver—where the display panel includes the same pixel circuit structure recited in claim 1. Yang strongly reads on the electronic-device architecture, because it explicitly depicts a display device including the display panel and driver circuits such as a scan driving circuit, data driving circuit, and a timing controller that controls driving. Thus, Yang reads on the “panel driver” and “driving controller” concepts at a high level: the scan/data driving circuits act as drivers for the panel, and the timing controller functions as a controller coordinating their operation. The main deficiency is the same as for claim 1: claim 20 requires the display panel to include the specific pixel circuit with (a) the three-transistor relationships (first transistor between first drive-voltage line and OLED; second transistor between data line and second node; third transistor between first transistor and first node), and (b) the three capacitor electrodes that form two capacitors via facing relationships, with each capacitor electrode being on a different insulating layer. Although Yang discloses a complex pixel circuit including a driving transistor, switching transistors, and capacitors tied to nodes and supply lines, it does not clearly disclose the claimed three-electrode stacked capacitor arrangement nor the insulating-layer placement requirement. Accordingly, Yang reads well on the overall “electronic device with panel + drivers + controller” aspect, but it does not fully read on the specific stacked-capacitor pixel circuit limitations that define claim 20’s display panel.
The prior art reference of Ha (U.S. Pub. No. 2024/0257738) discloses a display device and driving method that improves uniformity by compensating for luminance changes using a voltage applied outside a subpixel. The display system includes a timing controller, data driver, and gate driver, which drive a display panel having pixels/subpixels arranged in a display area (see Fig. 1 and the accompanying description pages in the back half of the document). At the pixel level, Ha shows subpixels that include a pixel circuit and an OLED light emitting element, with multiple scan/control signals (e.g., Sc1–Sc3 and emission signals Em1/Em2) that define phases such as initialization, sampling, compensation, and emission (see the timing diagrams in Fig. 7–8 and pixel-circuit schematic in Fig. 6). The pixel circuit includes a driving transistor and switching elements coupled to nodes (e.g., N2–N4) and supply lines (e.g., EVDD and EVSS), as well as capacitive elements labeled CT and CC, where CT is shown coupled to a voltage line (VCOM) and CC is coupled in the OLED/driving path (see Fig. 6, Fig. 12, and Fig. 14–15). A key aspect is applying a compensation-related voltage (illustrated as Vcom/Vcom1/Vcom2 etc.) via a line arrangement and/or demultiplexing so that selected pixels/subpixels receive compensation voltages to adjust emission characteristics (see Fig. 11, Fig. 13, Fig. 16–17). Overall, Ha focuses on panel driving/compensation using external compensation voltages and pixel circuits that support sampling and emission control.
Claim 1 requires a display panel with an element layer including a light emitting element and a circuit layer including a pixel circuit connected to that light emitting element. Ha clearly reads on these general aspects because it discloses an OLED subpixel including an OLED element and a pixel circuit driven by scan/emission signals (e.g., Fig. 6 and timing in Fig. 7–8). Ha also generally reads on having a driving transistor controlled by node potentials and having switches that connect a data line and control lines to internal nodes during writing/sampling phases. However, Ha does not clearly teach the specific three-transistor and stacked-capacitor structure required by claim 1. The claim requires: (1) a first transistor between a first drive-voltage line and the light emitting element operating based on a first node; (2) a second transistor between a data line and a second node; (3) a third transistor between the first transistor and the first node; and (4) a very specific capacitor arrangement: a first capacitor formed by a first capacitor electrode (at the first node) and a second capacitor electrode (at the second node), plus a second capacitor formed by the second capacitor electrode facing a third capacitor electrode connected to the first drive-voltage line, where all three capacitor electrodes are on different insulating layers.
Ha depicts two capacitive components (CT and CC) and a circuit with multiple transistors/nodes (Fig. 6; also variants in Fig. 12, 14, 15), but it does not expressly disclose the claim’s three distinct capacitor electrodes arranged as a stacked two-capacitor structure sharing the second capacitor electrode, nor the requirement that the three capacitor electrodes are located on different insulating layers. In short, Ha overlaps with general OLED pixel circuitry and driving/compensation, but it does not read on the particular stacked capacitor electrode architecture recited in claim 1.
Claim 20 recites an electronic device including (i) a display panel, (ii) a panel driver configured to drive the display panel, and (iii) a driving controller configured to control the panel driver, where the display panel includes the same pixel circuit structure required by claim 1. Ha strongly reads on the system-level architecture because it explicitly shows a timing controller (driving controller concept), plus data/gate drivers (panel driver concept) driving a display panel with subpixels (see Fig. 1 and the associated driver blocks). Thus, Ha satisfies the “electronic device + panel driver + controller” framework at a high level. But claim 20 still requires that the display panel itself includes the specific pixel circuit limitations of claim 1, including the defined three-transistor relationships and the two-capacitor/three-electrode stacked capacitor structure with each electrode on a different insulating layer. As discussed above, Ha shows pixel circuits with an OLED, a driving transistor, switching transistors, and capacitors CT/CC, but it does not clearly disclose the three capacitor electrodes forming two capacitors by facing relationships, nor the insulating-layer placement of each electrode. Accordingly, Ha reads well on claim 20’s device-level controller/driver arrangement, but it does not fully read on the specific stacked-capacitor pixel circuit that defines the display panel portion of claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang (U.S. Pub. No. 2023/0260456) teaches a display device having OLED pixel
structure.
Cho (U.S. Pub. No. 2021/0210020) teaches a display panel pixel structure.
Han (U.S. Pub. No. 2014/0139502) teaches a pixel structure having OLED in the
pixel structure.
Inquiry
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/PEGEMAN KARIMI/Primary Examiner, Art Unit 2623