Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyake (U.S. Patent Application Publication 20160300900 A1).
Regarding Claim 1, Miyake teaches a display panel (par 0491 Fig 37A display panel 5002), comprising:
a pixel comprising a pixel circuit and a light-emitting diode (par 0505 Fig 45A pixel comprises a pixel circuit TR1-5, DrTr, C1-2 and a light emitting device OLED);
a data line configured to provide a data signal to the pixel (par 0113 Fig 45A a data line provides a data signal VDATA to the pixel);
a gate line configured to provide a gate signal to the pixel (par 0103 Fig 45A a gate line GL1 provides a gate signal to the pixel); and
a power line configured to provide a power signal to the pixel (par 0111 Fig 45A a power provides a power signal VANO to the pixel), wherein
the pixel circuit comprises:
a driving transistor electrically connected to the light-emitting diode and comprising an input electrode, an output electrode, a control electrode, and a sub-control electrode (par 0512 Fig 45A driving transistor DrTr electrically connected to the light-emitting diode OLED [through an emissions transistor Tr4 as in applicant’s Fig.2A] and comprising an input source electrode, an output drain electrode, a control gate electrode, and a sub-control back-gate electrode);
a switching transistor configured to be controlled by the gate signal and disposed between the data line and the driving transistor (par 0512 Fig 45A switching transistor Tr1 controlled by gate signal of GL1 and disposed between the data line of VDATA and the driving transistor DrTr);
a compensation transistor disposed between the output electrode and the control electrode of the driving transistor (par 0512 Fig 45A compensation transistor Tr2 disposed between the output drain electrode of DrTr and the control gate electrode of DrTr); and
a sub-compensation transistor configured to transfer a compensation signal to the sub-control electrode of the driving transistor and configured to be controlled by a same signal as the compensation transistor (par 0512 Fig 45A sub-compensation transistor Tr3 provides a compensation signal V0 to the sub-control back gate electrode of DrTr and configured to be controlled by a same signal GL2 as the compensation transistor Tr2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Miyake (U.S. Patent Application Publication 20160300900 A1) in view of Seo (U.S. Patent Application 20210027683 A1).
Regarding Claim 2, Miyake teaches the display panel of claim 1. However, Miyake appears not to expressly teach wherein
a voltage value of the compensation signal is greater than a voltage value of the power signal.
Seo teaches wherein
a voltage value of the compensation signal is greater than a voltage value of the power signal (par 0134-0135 Fig 7A the back gate voltage BS2 may have a level greater than the power signal voltage ELVDD).
Miyake and Seo are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake with the inclusion of the compensation signal voltage greater than the power signal voltage of Seo. The motivation would have been in order to provide a partial driving mode (Seo par 0134).
Claims 3 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (U.S. Patent Application Publication 20160300900 A1) in view of Hwang et al. (U.S. Patent Application 20200365082 A1, hereinafter “Hwang”).
Regarding Claim 3, Miyake teaches the display panel of claim 1. However, Miyake appears not to expressly teach wherein
a voltage value of the compensation signal decreases as an ambient temperature decreases.
Hwang teaches wherein
a voltage value of the compensation signal decreases as an ambient temperature decreases (par 0063 Figs 9,11 as ambient temperature decreases to maintain a constant current a higher voltage is required for the n-channel TFT of Fig 9, but for a p-channel TFT a lower voltage would be required to maintain a constant current, and thus a voltage value of the compensation signal decreases as an ambient temperature decreases).
Miyake and Hwang are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake with the inclusion of the compensation signal variation with temperature variation of Hwang. The motivation would have been in order to allow the drive transistor in the pixel circuit to be made with a p-channel TFT process.
Regarding Claim 18, Miyake teaches an electronic device (par 0491 Fig 37D portable game machine), comprising:
a processor (par 0484 Fig 37D CPU);
a memory (par 0484 Fig 37D memory)
a display device (par 0484 Fig 36A display device), comprising:
a display panel (par 0491 Fig 37A display panel 5002), wherein
the display panel comprises:
a pixel comprising a pixel circuit and a light-emitting diode (par 0505 Fig 45A pixel comprises a pixel circuit TR1-5, DrTr, C1-2 and a light emitting device OLED);
a data line configured to provide a data signal to the pixel (par 0113 Fig 45A a data line provides a data signal VDATA to the pixel);
a gate line configured to provide a gate signal to the pixel (par 0103 Fig 45A a gate line GL1 provides a gate signal to the pixel); and
a power line configured to provide a power signal to the pixel (par 0111 Fig 45A a power provides a power signal VANO to the pixel), wherein
the pixel circuit comprises:
a driving transistor electrically connected to the light-emitting diode and comprising an input electrode, an output electrode, a control electrode, and a sub-control electrode (par 0512 Fig 45A driving transistor DrTr electrically connected to the light-emitting diode OLED [through an emissions transistor Tr4 as in applicant’s Fig.2A] and comprising an input source electrode, an output drain electrode, a control gate electrode, and a sub-control back-gate electrode);
a switching transistor configured to be controlled by the gate signal and disposed between the data line and the driving transistor (par 0512 Fig 45A switching transistor Tr1 controlled by gate signal of GL1 and disposed between the data line of VDATA and the driving transistor DrTr);
a compensation transistor disposed between the output electrode and the control electrode of the driving transistor (par 0512 Fig 45A compensation transistor Tr2 disposed between the output drain electrode of DrTr and the control gate electrode of DrTr); and
a sub-compensation transistor configured to transfer a compensation signal to the sub-control electrode of the driving transistor and configured to be controlled by a same signal as the compensation transistor (par 0512 Fig 45A sub-compensation transistor Tr3 provides a compensation signal V0 to the sub-control back gate electrode of DrTr and configured to be controlled by a same signal GL2 as the compensation transistor Tr2); and
a user interface configured to sense user input via touch (par 0494 Fig 37D a game machine is taught which comprises a user interface with buttons 5307 and a stylus sensitive display 5303; par 0411 Fig 30B touch panel 2000 provides a user interface which may sense user input via the approach or touch/contact of an object such as a finger) or cursor select of an icon presented on the display panel.
However, Miyake appears not to expressly teach
a memory having stored application programs for execution by the processor; wherein
the processor is caused to execute one or more of the stored application programs upon receipt of the user input.
Hwang teaches
a memory having stored application programs for execution by the processor (par 0028 Fig 1 the processor may execute programs or instructions (e.g., an operating system or application program) stored on e.g. the local memory 14 and/or the main memory storage device 16); wherein
the processor is caused to execute one or more of the stored application programs upon receipt of the user input (par 0031 Figs 1,2 input structures 22 (such as a keyboard and/or touchpad) may be used to interact with the computer 10A, such as to start, control, or operate a GUI or applications running on computer 10A. For example, a keyboard and/or touchpad may allow a user to navigate a user interface or application interface displayed on the electronic display 18).
Miyake and Hwang are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake with the inclusion of the application handling via processor and memory of Hwang. The motivation would have been in order to allow the processor to adjust image data that is sent to the electronic display to compensate for operational variations, thereby improving the quality of the image frames, e.g. an application interface, appearing on the electronic display (Hwang par 0029).
Regarding Claim 19, Miyake as modified teaches the electronic device of claim 18, wherein
the stored application programs include one or more of a camera application, an audiovisual streaming application, or a telephone application (Hwang paras 0032-0033 teach a telephone which may be a combination of at least phone, media player, data organizer, and game platform applications).
Miyake and Hwang are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake with the inclusion of the applications of Hwang. The motivation would have been in order to allow the processor to adjust image data that is sent to the electronic display to compensate for operational variations, thereby improving the quality of the image frames, e.g. an application interface, appearing on the electronic display (Hwang par 0029).
Regarding Claim 20, Miyake as modified teaches the electronic device of claim 18, wherein
the user interface is a touch screen embedded in the display panel, wherein the touch screen includes touch sensors for sensing a touch or a tap by a user (Miyake par 0494 Fig 37D a game machine is taught which comprises a user interface with buttons 5307 and a stylus sensitive display 5303; par 0411 Fig 30B touch panel 2000 provides a user interface which may sense user input via the approach or touch/contact of an object such as a finger).
Claims 4 and 9-10 are rejected under 35 U.S.C. 103 as being obvious over Miyake (U.S. Patent Application Publication 20160300900 A1) in view of Yu et al. (U.S. Patent Application 20230402008 A1, hereinafter “Yu”).
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
The rejections below under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding Claim 4, Miyake teaches the display panel of claim 1, further comprising:
an emission control line configured to provide an emission control signal to the pixel (par 0505 Fig 45A emission control line GL3 configured to provide an emission control signal to the pixel);
a second emission transistor configured to be controlled by the emission control signal and disposed between the driving transistor and the light-emitting diode (par 0505 Fig 45A emission transistor Tr4 controlled by emission control signal GL3 and disposed between the driving transistor DrTr and the light-emitting diode OLED).
However, Miyake appears not to expressly teach
a first emission transistor configured to be controlled by the emission control signal and disposed between the power line and the driving transistor; and
an emission compensation transistor configured to be controlled by the emission control signal and disposed between the power line and the sub-control electrode of the driving transistor.
Yu teaches
an emission control line configured to provide an emission control signal to the pixel (par 0064 Fig 2 emission control line EMj configured to provide an emission control signal to the pixel);
a first emission transistor configured to be controlled by the emission control signal and disposed between the power line and the driving transistor (par 0081,0505 Fig 2 first emission transistor T1 controlled by emission control signal EMj and disposed between the power line ELVSS and the driving transistor DTR);
a second emission transistor configured to be controlled by the emission control signal and disposed between the driving transistor and the light-emitting diode (par 0081,0505 Fig 2 second emission transistor T2 controlled by emission control signal EMj and disposed between the driving transistor DTR and the light-emitting diode ED); and
an emission compensation transistor configured to be controlled by the emission control signal and disposed between the power line and the sub-control electrode of the driving transistor (par 0081,0505 Fig 2 emission compensation transistor CT2 controlled by the emission control signal EMj and disposed between the power line ELVSS and the sub-control electrode TBG of the driving transistor DTR).
Miyake and Yu are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake with the inclusion of the emission control and compensation arrangement of Yu. The motivation would have been in order that the back gate electrode TBG of the driving transistor DTR may be synchronized with the second node N2 by the second transistor CT2 (Yu par 0081).
Regarding Claim 9, Miyake teaches a display panel (par 0491 Fig 37A display panel 5002), comprising:
a pixel comprising a pixel circuit and a light-emitting diode (par 0505 Fig 45A pixel comprises a pixel circuit TR1-5, DrTr, C1-2 and a light emitting device OLED);
a data line configured to provide a data signal to the pixel (par 0113 Fig 45A a data line provides a data signal VDATA to the pixel);
a gate line configured to provide a gate signal to the pixel (par 0103 Fig 45A a gate line GL1 provides a gate signal to the pixel); and
a power line configured to provide a power signal to the pixel (par 0111 Fig 45A a power provides a power signal VANO to the pixel), and
an emission control line configured to provide an emission control signal to the pixel (par 0505 Fig 45A emission control line GL3 configured to provide an emission control signal to the pixel), wherein
the pixel circuit comprises:
a driving transistor electrically connected to the light-emitting diode and comprising an input electrode, an output electrode, a control electrode, and a sub-control electrode (par 0512 Fig 45A driving transistor DrTr electrically connected to the light-emitting diode OLED [through an emissions transistor Tr4 as in applicant’s Fig.2A] and comprising an input source electrode, an output drain electrode, a control gate electrode, and a sub-control back-gate electrode);
a switching transistor configured to be controlled by the gate signal and disposed between the data line and the driving transistor (par 0512 Fig 45A switching transistor Tr1 controlled by gate signal of GL1 and disposed between the data line of VDATA and the driving transistor DrTr);
a second emission transistor configured to be controlled by the emission control signal and disposed between the driving transistor and the light-emitting diode (par 0505 Fig 45A emission transistor Tr4 controlled by emission control signal GL3 and disposed between the driving transistor DrTr and the light-emitting diode OLED).
However, Miyake appears not to expressly teach
a first emission transistor configured to be controlled by the emission control signal and disposed between the power line and the driving transistor; and
an emission compensation transistor configured to be controlled by the emission control signal and disposed between the power line and the sub-control electrode of the driving transistor.
Yu teaches
an emission control line configured to provide an emission control signal to the pixel (par 0064 Fig 2 emission control line EMj configured to provide an emission control signal to the pixel);
a first emission transistor configured to be controlled by the emission control signal and disposed between the power line and the driving transistor (par 0081,0505 Fig 2 first emission transistor T1 controlled by emission control signal EMj and disposed between the power line ELVSS and the driving transistor DTR);
a second emission transistor configured to be controlled by the emission control signal and disposed between the driving transistor and the light-emitting diode (par 0081,0505 Fig 2 second emission transistor T2 controlled by emission control signal EMj and disposed between the driving transistor DTR and the light-emitting diode ED); and
an emission compensation transistor configured to be controlled by the emission control signal and disposed between the power line and the sub-control electrode of the driving transistor (par 0081,0505 Fig 2 emission compensation transistor CT2 controlled by the emission control signal EMj and disposed between the power line ELVSS and the sub-control electrode TBG of the driving transistor DTR).
Miyake and Yu are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake with the inclusion of the emission control and compensation arrangement of Yu. The motivation would have been in order that the back gate electrode TBG of the driving transistor DTR may be synchronized with the second node N2 by the second transistor CT2 (Yu par 0081).
Regarding Claim 10, Miyake as modified teaches the display panel of claim 9, further comprising:
a compensation transistor disposed between the output electrode and the control electrode of the driving transistor (Miyake par 0512 Fig 45A compensation transistor Tr2 disposed between the output drain electrode of DrTr and the control gate electrode of DrTr); and
a sub-compensation transistor configured to transfer a compensation signal to the sub-control electrode of the driving transistor and configured to be controlled by a same signal as the compensation transistor (Miyake par 0512 Fig 45A sub-compensation transistor Tr3 provides a compensation signal V0 to the sub-control back gate electrode of DrTr and configured to be controlled by a same signal GL2 as the compensation transistor Tr2).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (U.S. Patent Application Publication 20160300900 A1) in view of Jung et al. (U.S. Patent Application Publication 20220101798 A1, hereinafter “Jung”).
Regarding Claim 5, Miyake teaches the display panel of claim 1. However, Miyake appears not to expressly teach further comprising:
a capacitor disposed between the power line and the compensation transistor.
Jung teaches
a capacitor disposed between the power line and the compensation transistor (par 0094 Fig 7 Cst1 disposed between ELVDD and the compensation transistor M1).
Miyake and Jung are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake with the inclusion of the drive transistor gate capacitor to power of Jung. The motivation would have been in order that the internal compensation circuit samples, using a plurality of switch elements, a threshold voltage Vth of the driving element DT to store it in a capacitor Cst1 (Jung par 0094).
Regarding Claim 7, Miyake teaches the display panel of claim 1. However, Miyake appears not to expressly teach further comprising:
a second initialization line configured to provide a second initialization signal to the pixel; and
a second initialization transistor disposed between the second initialization line and the light-emitting diode and configured to transfer the second initialization signal to the light-emitting diode.
Jung teaches
a second initialization line configured to provide a second initialization signal to the pixel (par 0094 Fig 7 a second initialization line PL2 provides a second initialization signal Vini to node n4 through M6); and
a second initialization transistor disposed between the second initialization line and the light-emitting diode and configured to transfer the second initialization signal to the light-emitting diode (par 0093 Fig 7 second initialization transistor M6 disposed between the line PL2 providing Vini and the light-emitting diode OLED and configured to transfer the second initialization signal Vini to the OLED).
Miyake and Jung are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake with the inclusion of the second initialization structure of Jung. The motivation would have been in order to provide starting voltages to pixel circuit nodes prior to threshold voltage sampling (Jung par 0111).
Claim 6 is rejected under 35 U.S.C. 103 as being obvious over Miyake (U.S. Patent Application Publication 20160300900 A1) in view of Park et al. (U.S. Patent Application 20240062710 A1, hereinafter “Park”).
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
The rejection below under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02
Regarding Claim 6, Miyake teaches the display panel of claim 1. However, Miyake appears not to expressly teach
further comprising:
a first initialization line configured to provide a first initialization signal to the pixel; and
a first initialization transistor disposed between the first initialization line and the control electrode of the driving transistor and configured to be turned on simultaneously with the compensation transistor for a predetermined period.
Park teaches
further comprising:
a first initialization line configured to provide a first initialization signal to the pixel (par 0305 Fig 27 first initialization line VREF provides a first initialization signal VREF to the pixel); and
a first initialization transistor disposed between the first initialization line and the control electrode of the driving transistor and configured to be turned on simultaneously with the compensation transistor for a predetermined period (par 0305 Fig 27 first initialization transistor T5 disposed between the first initialization line VREF and the control electrode gate of the driving transistor T1; and configured to be turned on simultaneously by the GC signal with the compensation transistor T3 for a predetermined period).
Miyake and Park are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake with the inclusion of the first initialization arrangement of Park. The motivation would have been in order to receive the reference voltage VREF through the fifth transistor T5 and Cst to change a voltage of the gate electrode of the driving transistor T1 (Park par 0076).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Miyake (U.S. Patent Application Publication 20160300900 A1) in view of Yu et al. (U.S. Patent Application 20230402008 A1, hereinafter “Yu”) and further in view of Seo (U.S. Patent Application 20210027683 A1).
Regarding Claim 11, Miyake as modified teaches the display panel of claim 10. However, Miyake as modified appears not to expressly teach wherein
a voltage value of the compensation signal is greater than a voltage value of the power signal.
Seo teaches wherein
a voltage value of the compensation signal is greater than a voltage value of the power signal (par 0134-0135 Fig 7A the back gate voltage BS2 may have a level greater than the power signal voltage ELVDD).
Miyake Yu and Seo are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake/Yu with the inclusion of the compensation signal voltage greater than the power signal voltage of Seo. The motivation would have been in order to provide a partial driving mode (Seo par 0134).
Claim 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Miyake (U.S. Patent Application Publication 20160300900 A1) in view of Yu et al. (U.S. Patent Application 20230402008 A1, hereinafter “Yu”) and further in view of Seo (U.S. Patent Application 20210027683 A1) and Hwang et al. (U.S. Patent Application 20200365082 A1, hereinafter “Hwang”).
Regarding Claim 12, Miyake as modified teaches the display panel of claim 11. However, Miyake as modified appears not to expressly teach wherein
the voltage value of the compensation signal decreases as an ambient temperature decreases.
Hwang teaches wherein
a voltage value of the compensation signal decreases as an ambient temperature decreases (par 0063 Figs 9,11 as ambient temperature decreases to maintain a constant current a higher voltage is required for the n-channel TFT of Fig 9, but for a p-channel TFT a lower voltage would be required to maintain a constant current, and thus a voltage value of the compensation signal decreases as an ambient temperature decreases).
Miyake Hwang Seo and Yu are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake/Hwang/Seo with the inclusion of the hold capacitor of Yu. The motivation would have been in order to allow the drive transistor in the pixel circuit to be made with a p-channel TFT process.
Regarding Claim 13, Miyake as modified teaches the display panel of claim 12, further comprising:
a capacitor disposed between the power line and the compensation transistor (Yu par 0071 Fig 2 a capacitor C1 disposed between the power line ELVSS and the compensation transistor T7).
Miyake Yu Seo and Hwang are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake/Yu/Seo with the inclusion of the compensation signal variation with temperature variation of Hwang. The motivation would have been in order to allow the data signal Di transmitted from the i-th data line DLi to be held at the drive transistor gate (Yu par 0075).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Miyake (U.S. Patent Application Publication 20160300900 A1) in view of Yu et al. (U.S. Patent Application 20230402008 A1, hereinafter “Yu”) and further in view of Seo (U.S. Patent Application 20210027683 A1), Hwang et al. (U.S. Patent Application 20200365082 A1, hereinafter “Hwang”), and Park et al. (U.S. Patent Application 20240062710 A1, hereinafter “Park”).
Regarding Claim 14, Miyake as modified teaches the display panel of claim 13. However, Miyake appears not to expressly teach
further comprising:
a first initialization line configured to provide a first initialization signal to the pixel; and
a first initialization transistor disposed between the first initialization line and the control electrode of the driving transistor and configured to be turned on simultaneously with the compensation transistor for a predetermined period.
Park teaches
further comprising:
a first initialization line configured to provide a first initialization signal to the pixel (par 0305 Fig 27 first initialization line VREF provides a first initialization signal VREF to the pixel); and
a first initialization transistor disposed between the first initialization line and the control electrode of the driving transistor and configured to be turned on simultaneously with the compensation transistor for a predetermined period (par 0305 Fig 27 first initialization transistor T5 disposed between the first initialization line VREF and the control electrode gate of the driving transistor T1; and configured to be turned on simultaneously by the GC signal with the compensation transistor T3 for a predetermined period).
Miyake Yu Seo Hwang and Park are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake/Yu/Seo/Hwang with the inclusion of the first initialization arrangement of Park. The motivation would have been in order to receive the reference voltage VREF through the fifth transistor T5 and Cst to change a voltage of the gate electrode of the driving transistor T1 (Park par 0076).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Miyake (U.S. Patent Application Publication 20160300900 A1) in view of Yu et al. (U.S. Patent Application 20230402008 A1, hereinafter “Yu”) and further in view of Seo (U.S. Patent Application 20210027683 A1), Hwang et al. (U.S. Patent Application 20200365082 A1, hereinafter “Hwang”), Park et al. (U.S. Patent Application 20240062710 A1, hereinafter “Park”), and Jung et al. (U.S. Patent Application Publication 20220101798 A1, hereinafter “Jung”).
Regarding Claim 15, Miyake as modified teaches the display panel of claim 14. However, Miyake appears not to expressly teach further comprising:
a second initialization line configured to provide a second initialization signal to the pixel; and
a second initialization transistor disposed between the second initialization line and the light-emitting diode and configured to transfer the second initialization signal to the light-emitting diode.
Jung teaches
a second initialization line configured to provide a second initialization signal to the pixel (par 0094 Fig 7 a second initialization line PL2 provides a second initialization signal Vini to node n4 through M6); and
a second initialization transistor disposed between the second initialization line and the light-emitting diode and configured to transfer the second initialization signal to the light-emitting diode (par 0093 Fig 7 second initialization transistor M6 disposed between the line PL2 providing Vini and the light-emitting diode OLED and configured to transfer the second initialization signal Vini to the OLED).
Miyake Yu Seo Hwang Park and Jung are analogous art as they each pertain to electronic device display compensation. It would have been obvious to a person of ordinary skill in the art to modify the electronic device of Miyake/Yu/Seo/Hwang/Park with the inclusion of the second initialization structure of Jung. The motivation would have been in order to provide starting voltages to pixel circuit nodes prior to threshold voltage sampling (Jung par 0111).
Allowable Subject Matter
Claims 8 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 8:
While closest prior art Miyake (20160300900 A1) and Jung (20220101798 A1) teach portions of the limitations of Claim 8, the prior art of record fails to teach or fairly suggest the particular limitations of Claim 8, namely "a bias signal line configured to provide a bias signal to the pixel; and a bias transistor disposed between the bias signal line and the driving transistor and configured to be controlled by a same signal as the second initialization transistor" in combination with all other limitations of the claim and of claims on which the claim depends.
Claim 16:
While closest prior art Miyake (20160300900 A1), Yu (20230402008 A1), Seo (20210027683 A1), Hwang (20200365082 A1), Park (20240062710 A1), and Jung (20220101798 A1) teach portions of the limitations of Claim 16, the prior art of record fails to teach or fairly suggest the particular limitations of Claim 16, namely "a bias signal line configured to provide a bias signal to the pixel; and a bias transistor disposed between the bias signal line and the driving transistor and configured to be controlled by a same signal as the second initialization transistor" in combination with all other limitations of the claim and of claims on which the claim depends.
Claim 17 would be allowable dependent on the allowability of Claim 16.
Conclusion
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/MARK EDWARDS/Primary Examiner, Art Unit 2624
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