DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this office action and presented for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5, 7-14, and 16-19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5, and 8-9 of U.S. Patent No. 12299451 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations of each of the aforementioned instant claims are taught by a corresponding claim of the ‘451 patent. As an exemplary case, see the table below, wherein standard-format limitations in the left column correlate to italicized limitations in the right column.
Claim 1 of Instant Application: 19206182
Claim 1 of U.S. Patent No. 12299451
1. A system comprising:
1. A system, comprising:
a set of registers capable of storing a set of values; and a processor capable of,
a processor, wherein the processor includes a plurality of processor registers that includes a first processor register and a second processor register, and wherein the processor is configured to:
in response to an instruction: determining a subset of the set of registers; preserving a subset of the set of values stored in the subset of the set of registers; and clearing a remainder of the set of values stored in a remainder of the set of registers without clearing the subset of the set of values stored in the subset of the set of registers.
execute a first instruction in a first execution context, wherein the first instruction is associated with a transition to a second execution context; receive a PRESERVE instruction that indicates the first processor register among the plurality of processor registers; responsive to the PRESERVE instruction and the transition from the first execution context to the second execution context, preserve a value in the first processor register by clearing the second processor register without clearing the first processor register; and execute a second instruction in the second execution context.
All the limitations of claim 2 are taught by claim 5 of the ‘451 patent.
All the limitations of claim 3 are taught by claim 8 of the ‘451 patent.
All the limitations of claim 4 are taught by claim 8 of the ‘451 patent.
All the limitations of claim 5 are taught by claim 8 of the ‘451 patent.
All the limitations of claim 7 are taught by claim 3 of the ‘451 patent.
All the limitations of claim 8 are taught by claim 9 of the ‘451 patent.
All the limitations of claim 9 are taught by claim 1 of the ‘451 patent.
All the limitations of claim 10 are taught by claim 1 of the ‘451 patent.
All the limitations of claim 11 are taught by claim 5 of the ‘451 patent.
All the limitations of claim 12 are taught by claim 8 of the ‘451 patent.
All the limitations of claim 13 are taught by claim 8 of the ‘451 patent.
All the limitations of claim 14 are taught by claim 8 of the ‘451 patent.
All the limitations of claim 16 are taught by claim 1 of the ‘451 patent.
All the limitations of claim 17 are taught by claim 1 of the ‘451 patent.
All the limitations of claim 18 are taught by claim 5 of the ‘451 patent.
All the limitations of claim 19 are taught by claim 8 of the ‘451 patent.
Claims 6, 15, and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12299451 in view of Plondke et al. (Plondke) (US 20130067205 A1).
Regarding the additional limitation(s) not taught by the applied reference(s) thus far, Plondke is relied upon to render obvious the additional limitation(s) in an analogous manner as Plondke is relied upon in the rejection(s) of the aforementioned instant claim(s) below; see the citations of Plondke and corresponding rationale(s) for obviousness in the rejection(s) of the aforementioned instant claim(s) under 35 USC 103 below.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6 and 15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 6 recites the limitation “the first instruction is received by the processor prior to the second instruction being received by the processor” in lines 1-2. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0019], [0020], [0032]) does not appear to provide support for the first instruction being “received by the processor” prior to the second instruction being “received by the processor”.
Claim 15 recites the limitation “the first instruction is received by the processor prior to the second instruction being received by the processor” in lines 1-2. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraphs [0019], [0020], [0032]) does not appear to provide support for the first instruction being “received by the processor” prior to the second instruction being “received by the processor”.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a set of registers capable of storing a set of values; and a processor capable of, in response to an instruction: determining a subset of the set of registers; preserving a subset of the set of values stored in the subset of the set of registers; and clearing a remainder of the set of values stored in a remainder of the set of registers without clearing the subset of the set of values stored in the subset of the set of registers” in lines 2-7. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether the claim merely requires a processor that has the theoretical capability of “in response to an instruction: determining a subset of the set of registers; preserving a subset of the set of values stored in the subset of the set of registers; and clearing a remainder of the set of values stored in a remainder of the set of registers without clearing the subset of the set of values stored in the subset of the set of registers” even if it is not designed or ever used to do so, or whether the claim indeed requires a processor which is designed to and does “in response to an instruction: determine[e] a subset of the set of registers; preserv[e] a subset of the set of values stored in the subset of the set of registers; and clear[] a remainder of the set of values stored in a remainder of the set of registers without clearing the subset of the set of values stored in the subset of the set of registers”. Similarly, it is indefinite as to whether the claim merely requires that a set of registers has the theoretical capability of storing the recited set of values, or whether the claim indeed requires a set of registers which is designed to and does store the recited set of values. Examiner recommends using more definite claim language than “capable of”. Relatedly, the claim does not appear to have antecedent basis for the set of values stored in the set of registers, given that the recitation of “a set of registers capable of storing a set of values” in claim 1, line 2, does not appear to necessitate a set of values that are indeed stored in a set of registers. Similarly, Examiner recommends using more definite claim language than “capable of”.
Claims 2-9 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 9 recites the limitation “the processor is capable of: executing a first set of instructions in a first context prior to execution of the instruction; and executing a second set of instructions in a second context after execution of the instruction” in lines 1-3. However, it is indefinite as to whether the claim merely requires that the processor has the theoretical capability of “executing a first set of instructions in a first context prior to execution of the instruction; and executing a second set of instructions in a second context after execution of the instruction”, or whether the claim indeed requires a processor that is designed to and does execute a first set of instructions in a first context prior to execution of the instruction; and execute a second set of instructions in a second context after execution of the instruction. Examiner recommends using more definite claim language than “capable of”.
Claim 10 recites the limitation “a processor capable of, based on an instruction that specifies a subset of the set of registers, clearing each register of the set of registers that is not specified by the instruction such that a set of values stored in the subset of the set of registers is preserved” in lines 3-5. However, it is indefinite as to whether the claim merely requires that the processor has the theoretical capability of “based on an instruction that specifies a subset of the set of registers, clearing each register of the set of registers that is not specified by the instruction such that a set of values stored in the subset of the set of registers is preserved”, or whether the claim indeed requires a processor that is designed to and does, based on an instruction that specifies a subset of the set of registers, clear each register of the set of registers that is not specified by the instruction such that a set of values stored in the subset of the set of registers is preserved. Examiner recommends using more definite claim language than “capable of”.
Claims 11-16 are rejected for failing to alleviate the rejection of claim 10 above.
Claim 17 recites the limitation “the instructions is” in line 2. However, the metes and bounds of this limitation are indefinite. For example, “the instructions” does not appear to have antecedent basis. In addition, the recitation of “is” following “instructions” makes it unclear as to whether “instructions” is intended to be a singular or plural noun. Note that “the instructions” is further recited in claim 19, line 3.
Claims 18-20 are rejected for failing to alleviate the rejection of claim 17 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-13, and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hammond et al. (Hammond) (US 6209085 B1) in view of Schuchman et al. (Schuchman) (US 8762692 B2).
Consider claim 1, Hammond discloses a system comprising: a set of registers (col. 1, lines 15-16, a processor comprises a number of registers contained in its register set for use during the execution of a process) capable of storing a set of values (col. 1, line 17, contents); and a processor (col. 1, line 15, processor) capable of: determining a subset (col. 2, lines 7-8, the disable bit is set to indicate the floating point register file is disabled; col. 1, line 64, to col. 2, line 1, a second method in the prior art for preserving register states in a single processor system employs disable bits for certain "register files" (i.e., groupings of registers--e.g., the floating point registers may be grouped as the floating point register file)) of the set of registers (col. 1, lines 15-16, a processor comprises a number of registers contained in its register set for use during the execution of a process); preserving a subset of the set of values stored in the subset of the set of registers (col. 1, lines 64-65, preserving register states; col. 2, lines 1-3, the contents of the floating point register file are not saved or loaded as part of a process's register state during process switches; col. 2, lines 8-11, during a process switch from the first process, only that portion of the register state of the first process which is not stored in the floating point register file is stored in a storage device; col. 2, lines 17-24, if no other processes utilize the floating point register file while the first process is not executing, the floating point register file is not saved or loaded. In this manner, disable bits permit the operating system to delay, and possibly avoid, the saving and loading of the floating point register file. Thus, process switch overhead is reduced by reducing the number of registers which must be saved and loaded; col. 1, lines 27-29, when a processor switches from one process to another, a process switch (also termed as a "context switch" or a "task switch") is said to have occurred); and clearing a remainder of the set of values stored in a remainder of the set of registers without clearing the subset of the set of values stored in the subset of the set of registers (col. 1, lines 64-65, preserving register states; col. 2, lines 1-3, the contents of the floating point register file are not saved or loaded as part of a process's register state during process switches; col. 2, lines 8-11, during a process switch from the first process, only that portion of the register state of the first process which is not stored in the floating point register file is stored in a storage device; col. 2, lines 17-24, if no other processes utilize the floating point register file while the first process is not executing, the floating point register file is not saved or loaded. In this manner, disable bits permit the operating system to delay, and possibly avoid, the saving and loading of the floating point register file. Thus, process switch overhead is reduced by reducing the number of registers which must be saved and loaded; col. 1, lines 27-29, when a processor switches from one process to another, a process switch (also termed as a "context switch" or a "task switch") is said to have occurred).
However, Hammond does not disclose that the aforementioned functionality is in response to an instruction.
On the other hand, Schuchman discloses functionality being in response to an instruction (col. 4, lines 7-22, machine-readable medium having stored thereon a set of instructions, which when executed by a machine, such as a processor, cause the underlying hardware to perform one or more methods prescribed by the instructions. In one embodiment, the instructions, when executed by a processor, cause the processor to reduce power consumed by the processor. For example, at least one embodiment includes instructions prescribing operations, including specifying a subset of registers for a register operation, such as saving or restoring state information of registers, performing the register operation, and performing a portion of a standby operation. Embodiments may specify a subset of registers to minimize the number of registers involved with the processor switch operation. In one embodiment, a processor switch operation may include a sleep operation, a context switch operation, or an MWAIT operation; col. 4, lines 43-49, processor 160 may have architectural hardware to perform, and allow software to invoke, one or more of the power saving techniques described herein. In other words, various embodiments may have hardware to decode and execute instructions described herein, or instructions or commands similar to the ones described, which enable the power saving techniques; col. 8, lines 45-48, an Instruction Set Architecture (ISA) associated with a processor may enable programs, such as applications or operating systems, to specify registers register sets, or portions thereof; col. 11, lines 24-34, apparatus 200 may comprise a portion of a processor executing code of an operating system and one or more applications. One or more embodiments may allow software, such as an application, a process, or an operating system to save and/or restore state information of a subset of registers, where the saving/restoring of state information is associated with a processor switch operation. For example, the processor switch operation may comprise a switch from one mode of operation to another or a switch from executing the instructions of one thread or process to executing the instructions of another thread or process; col. 11, lines 49-51, an application, process, or OS may save and/or restore state information of a subset of registers to/from persistent memory 290; col. 12, lines 3-9, for example, apparatus 200 may execute instructions that cause apparatus 200 to stop instruction execution during a first mode of operation and enter a second mode of operation, a low-power operating state, until occurrence of an event or class of events, such as executing instructions associated with an MWAIT, MONITOR, HLT, PAUSE, SYSCALL, SYSEXIT, or other instructions; col. 12, lines 37-41, in one or more embodiments, apparatus 200 may perform a processor operation, such as context switch or a switch to a low-power operating mode, by executing instructions of an operating system or an application; col. 12, line 65, to col. 13, line 16, In one embodiment apparatus 200 may perform a save operation for state information of one or more of a subset of registers of RRF 295, a subset of registers 280, and a subset of registers of RAT 235 to persistent memory 290, upon the execution of an MWAIT instruction of apparatus 200. Alternatively, for the sake of an additional example, apparatus 200 may perform a restore operation of previously saved state information from persistent memory 290 to a subset of registers RRF 295, a subset of registers 280, and a subset of registers 235, upon the execution of a context switch between two applications. Stated alternatively, apparatus 200 may execute a series of uops associated with a processor switch operation, via the fetch unit 210, decode unit 220, rename unit 230, execution unit 270, etc., wherein executing one or more of the uops causes apparatus 200 to save or restore state information for a subset or limited number of registers of registers of RRF 295, registers 280, and RAT 235 to/from persistent memory 290; col. 13, lines 52-54, a specific instruction, such as a "SleepWithRegister SetsAndHandler(bitmap* regset, func* handler)" instruction; col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schuchman with the invention of Hammond to facilitate implementation capability and flexibility. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Hammond as cited above, and the prior art elements of Schuchman as cited above) according to known methods (Examiner submits that implementation of operations via instructions is known. Also see, for example, col. 4, lines 5-11, which lists hardware implementation and software implementation as alternatives) to yield predictable results (the invention of Hammond, implemented via an instruction), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 2, the overall combination entails the system of claim 1 (see above), wherein the instruction is a protected call instruction (Schuchman, col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
Consider claim 3, the overall combination entails the system of claim 1 (see above), wherein: the instruction is a first instruction; and the determining of the subset of the set of registers, the preserving of the subset of the set of values, and the clearing of the remainder of the set of values are further in response to a second instruction (Schuchman, col. 4, lines 11-22, col. 4, lines 7-22, machine-readable medium having stored thereon a set of instructions, which when executed by a machine, such as a processor, cause the underlying hardware to perform one or more methods prescribed by the instructions. In one embodiment, the instructions, when executed by a processor, cause the processor to reduce power consumed by the processor. For example, at least one embodiment includes instructions prescribing operations, including specifying a subset of registers for a register operation, such as saving or restoring state information of registers, performing the register operation, and performing a portion of a standby operation. Embodiments may specify a subset of registers to minimize the number of registers involved with the processor switch operation. In one embodiment, a processor switch operation may include a sleep operation, a context switch operation, or an MWAIT operation; col. 4, lines 43-49, processor 160 may have architectural hardware to perform, and allow software to invoke, one or more of the power saving techniques described herein. In other words, various embodiments may have hardware to decode and execute instructions described herein, or instructions or commands similar to the ones described, which enable the power saving techniques; col. 8, lines 45-48, an Instruction Set Architecture (ISA) associated with a processor may enable programs, such as applications or operating systems, to specify registers register sets, or portions thereof; col. 11, lines 24-34, apparatus 200 may comprise a portion of a processor executing code of an operating system and one or more applications. One or more embodiments may allow software, such as an application, a process, or an operating system to save and/or restore state information of a subset of registers, where the saving/restoring of state information is associated with a processor switch operation. For example, the processor switch operation may comprise a switch from one mode of operation to another or a switch from executing the instructions of one thread or process to executing the instructions of another thread or process; col. 11, lines 49-51, an application, process, or OS may save and/or restore state information of a subset of registers to/from persistent memory 290; col. 12, lines 3-9, for example, apparatus 200 may execute instructions that cause apparatus 200 to stop instruction execution during a first mode of operation and enter a second mode of operation, a low-power operating state, until occurrence of an event or class of events, such as executing instructions associated with an MWAIT, MONITOR, HLT, PAUSE, SYSCALL, SYSEXIT, or other instructions; col. 12, lines 37-41, in one or more embodiments, apparatus 200 may perform a processor operation, such as context switch or a switch to a low-power operating mode, by executing instructions of an operating system or an application; col. 12, line 65, to col. 13, line 16, In one embodiment apparatus 200 may perform a save operation for state information of one or more of a subset of registers of RRF 295, a subset of registers 280, and a subset of registers of RAT 235 to persistent memory 290, upon the execution of an MWAIT instruction of apparatus 200. Alternatively, for the sake of an additional example, apparatus 200 may perform a restore operation of previously saved state information from persistent memory 290 to a subset of registers RRF 295, a subset of registers 280, and a subset of registers 235, upon the execution of a context switch between two applications. Stated alternatively, apparatus 200 may execute a series of uops associated with a processor switch operation, via the fetch unit 210, decode unit 220, rename unit 230, execution unit 270, etc., wherein executing one or more of the uops causes apparatus 200 to save or restore state information for a subset or limited number of registers of registers of RRF 295, registers 280, and RAT 235 to/from persistent memory 290; col. 13, lines 52-54, a specific instruction, such as a "SleepWithRegister SetsAndHandler(bitmap* regset, func* handler)" instruction; col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
Consider claim 4, the overall combination entails the system of claim 3 (see above), wherein the second instruction is a protected call instruction (Schuchman, col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
Consider claim 7, the overall combination entails the system of claim 1 (see above), wherein the instruction includes a field that specifies the subset of the set of registers by specifying a set of mask values (Schuchman, col. 8, lines 54-55, bitmap* regset; col. 9, lines 54-58, generate appropriate bitmaps specifying registers or portions of registers whose contents are to be saved/restored (or prevented from being saved or restored) as a result of executing a low-power mode instruction, such as a "SleepWithRegisterSet" instruction).
Consider claim 8, the overall combination entails the system of claim 1 (see above), wherein the set of registers includes a set of address registers, a set of data registers, and a set of map registers (Hammond, col. 1, line 67, floating point registers; col. 2, lines 9-11, portion of the register state of the first process which is not stored in the floating point register file; col. 4, lines 22-24, integer register file, a floating point register file, and a segmentation register file; Schuchman, col. 10, lines 38-39, general purpose integer registers, floating point/MMX registers, and data indexing registers; Examiner generally notes that it would have also been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the set of registers to include a set of address registers and a set of data registers to support calculations on addresses and data).
Consider claim 9, the overall combination entails the system of claim 1 (see above), wherein the processor is capable of: executing a first set of instructions in a first context prior to execution of the instruction; and executing a second set of instructions in a second context after execution of the instruction (Hammond, col. 1, lines 27-29, when a processor switches from one process to another, a process switch (also termed as a "context switch" or a "task switch") is said to have occurred).
Consider claim 10, Hammond discloses a system comprising: a set of registers (col. 1, lines 15-16, a processor comprises a number of registers contained in its register set for use during the execution of a process); and a processor (col. 1, line 15, processor) capable of, based on a specification of a subset of the registers, clearing each register of the set of registers that is not specified such that a set of values stored in the subset of the set of registers is preserved (col. 1, lines 64-65, preserving register states; col. 2, lines 1-3, the contents of the floating point register file are not saved or loaded as part of a process's register state during process switches; col. 2, lines 8-11, during a process switch from the first process, only that portion of the register state of the first process which is not stored in the floating point register file is stored in a storage device; col. 2, lines 17-24, if no other processes utilize the floating point register file while the first process is not executing, the floating point register file is not saved or loaded. In this manner, disable bits permit the operating system to delay, and possibly avoid, the saving and loading of the floating point register file. Thus, process switch overhead is reduced by reducing the number of registers which must be saved and loaded; col. 1, lines 27-29, when a processor switches from one process to another, a process switch (also termed as a "context switch" or a "task switch") is said to have occurred).
However, Hammond does not disclose that the aforementioned functionality is based on an instruction.
On the other hand, Schuchman discloses functionality being based on an instruction (col. 4, lines 7-22, machine-readable medium having stored thereon a set of instructions, which when executed by a machine, such as a processor, cause the underlying hardware to perform one or more methods prescribed by the instructions. In one embodiment, the instructions, when executed by a processor, cause the processor to reduce power consumed by the processor. For example, at least one embodiment includes instructions prescribing operations, including specifying a subset of registers for a register operation, such as saving or restoring state information of registers, performing the register operation, and performing a portion of a standby operation. Embodiments may specify a subset of registers to minimize the number of registers involved with the processor switch operation. In one embodiment, a processor switch operation may include a sleep operation, a context switch operation, or an MWAIT operation; col. 4, lines 43-49, processor 160 may have architectural hardware to perform, and allow software to invoke, one or more of the power saving techniques described herein. In other words, various embodiments may have hardware to decode and execute instructions described herein, or instructions or commands similar to the ones described, which enable the power saving techniques; col. 8, lines 45-48, an Instruction Set Architecture (ISA) associated with a processor may enable programs, such as applications or operating systems, to specify registers register sets, or portions thereof; col. 11, lines 24-34, apparatus 200 may comprise a portion of a processor executing code of an operating system and one or more applications. One or more embodiments may allow software, such as an application, a process, or an operating system to save and/or restore state information of a subset of registers, where the saving/restoring of state information is associated with a processor switch operation. For example, the processor switch operation may comprise a switch from one mode of operation to another or a switch from executing the instructions of one thread or process to executing the instructions of another thread or process; col. 11, lines 49-51, an application, process, or OS may save and/or restore state information of a subset of registers to/from persistent memory 290; col. 12, lines 3-9, for example, apparatus 200 may execute instructions that cause apparatus 200 to stop instruction execution during a first mode of operation and enter a second mode of operation, a low-power operating state, until occurrence of an event or class of events, such as executing instructions associated with an MWAIT, MONITOR, HLT, PAUSE, SYSCALL, SYSEXIT, or other instructions; col. 12, lines 37-41, in one or more embodiments, apparatus 200 may perform a processor operation, such as context switch or a switch to a low-power operating mode, by executing instructions of an operating system or an application; col. 12, line 65, to col. 13, line 16, In one embodiment apparatus 200 may perform a save operation for state information of one or more of a subset of registers of RRF 295, a subset of registers 280, and a subset of registers of RAT 235 to persistent memory 290, upon the execution of an MWAIT instruction of apparatus 200. Alternatively, for the sake of an additional example, apparatus 200 may perform a restore operation of previously saved state information from persistent memory 290 to a subset of registers RRF 295, a subset of registers 280, and a subset of registers 235, upon the execution of a context switch between two applications. Stated alternatively, apparatus 200 may execute a series of uops associated with a processor switch operation, via the fetch unit 210, decode unit 220, rename unit 230, execution unit 270, etc., wherein executing one or more of the uops causes apparatus 200 to save or restore state information for a subset or limited number of registers of registers of RRF 295, registers 280, and RAT 235 to/from persistent memory 290; col. 13, lines 52-54, a specific instruction, such as a "SleepWithRegister SetsAndHandler(bitmap* regset, func* handler)" instruction; col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schuchman with the invention of Hammond to facilitate implementation capability and flexibility. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Hammond as cited above, and the prior art elements of Schuchman as cited above) according to known methods (Examiner submits that implementation of operations via instructions is known. Also see, for example, col. 4, lines 5-11, which lists hardware implementation and software implementation as alternatives) to yield predictable results (the invention of Hammond, implemented via an instruction), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 11, the overall combination entails the system of claim 10 (see above), wherein the instruction is a protected call instruction (Schuchman, col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
Consider claim 12, the overall combination entails the system of claim 10 (see above), wherein: the instruction is a first instruction; and the clearing of each register of the set of registers that is not specified by the first instruction is further based on a second instruction (Schuchman, col. 4, lines 11-22, col. 4, lines 7-22, machine-readable medium having stored thereon a set of instructions, which when executed by a machine, such as a processor, cause the underlying hardware to perform one or more methods prescribed by the instructions. In one embodiment, the instructions, when executed by a processor, cause the processor to reduce power consumed by the processor. For example, at least one embodiment includes instructions prescribing operations, including specifying a subset of registers for a register operation, such as saving or restoring state information of registers, performing the register operation, and performing a portion of a standby operation. Embodiments may specify a subset of registers to minimize the number of registers involved with the processor switch operation. In one embodiment, a processor switch operation may include a sleep operation, a context switch operation, or an MWAIT operation; col. 4, lines 43-49, processor 160 may have architectural hardware to perform, and allow software to invoke, one or more of the power saving techniques described herein. In other words, various embodiments may have hardware to decode and execute instructions described herein, or instructions or commands similar to the ones described, which enable the power saving techniques; col. 8, lines 45-48, an Instruction Set Architecture (ISA) associated with a processor may enable programs, such as applications or operating systems, to specify registers register sets, or portions thereof; col. 11, lines 24-34, apparatus 200 may comprise a portion of a processor executing code of an operating system and one or more applications. One or more embodiments may allow software, such as an application, a process, or an operating system to save and/or restore state information of a subset of registers, where the saving/restoring of state information is associated with a processor switch operation. For example, the processor switch operation may comprise a switch from one mode of operation to another or a switch from executing the instructions of one thread or process to executing the instructions of another thread or process; col. 11, lines 49-51, an application, process, or OS may save and/or restore state information of a subset of registers to/from persistent memory 290; col. 12, lines 3-9, for example, apparatus 200 may execute instructions that cause apparatus 200 to stop instruction execution during a first mode of operation and enter a second mode of operation, a low-power operating state, until occurrence of an event or class of events, such as executing instructions associated with an MWAIT, MONITOR, HLT, PAUSE, SYSCALL, SYSEXIT, or other instructions; col. 12, lines 37-41, in one or more embodiments, apparatus 200 may perform a processor operation, such as context switch or a switch to a low-power operating mode, by executing instructions of an operating system or an application; col. 12, line 65, to col. 13, line 16, In one embodiment apparatus 200 may perform a save operation for state information of one or more of a subset of registers of RRF 295, a subset of registers 280, and a subset of registers of RAT 235 to persistent memory 290, upon the execution of an MWAIT instruction of apparatus 200. Alternatively, for the sake of an additional example, apparatus 200 may perform a restore operation of previously saved state information from persistent memory 290 to a subset of registers RRF 295, a subset of registers 280, and a subset of registers 235, upon the execution of a context switch between two applications. Stated alternatively, apparatus 200 may execute a series of uops associated with a processor switch operation, via the fetch unit 210, decode unit 220, rename unit 230, execution unit 270, etc., wherein executing one or more of the uops causes apparatus 200 to save or restore state information for a subset or limited number of registers of registers of RRF 295, registers 280, and RAT 235 to/from persistent memory 290; col. 13, lines 52-54, a specific instruction, such as a "SleepWithRegister SetsAndHandler(bitmap* regset, func* handler)" instruction; col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
Consider claim 13, the overall combination entails the system of claim 12 (see above), wherein the second instruction is a protected call instruction (Schuchman, col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
Consider claim 16, the overall combination entails the system of claim 12 (see above), wherein the second instruction is associated with a context switch (Hammond, col. 1, lines 27-29, when a processor switches from one process to another, a process switch (also termed as a "context switch" or a "task switch") is said to have occurred).
Consider claim 17, Hammond discloses specifying a subset (col. 2, lines 7-8, the disable bit is set to indicate the floating point register file is disabled; col. 1, line 64, to col. 2, line 1, a second method in the prior art for preserving register states in a single processor system employs disable bits for certain "register files" (i.e., groupings of registers--e.g., the floating point registers may be grouped as the floating point register file)) of a set of registers (col. 1, lines 15-16, a processor comprises a number of registers contained in its register set for use during the execution of a process), wherein a processor is to clear a remainder of the set of registers such that a set of values stored in the subset of the set of registers is preserved (col. 1, lines 64-65, preserving register states; col. 2, lines 1-3, the contents of the floating point register file are not saved or loaded as part of a process's register state during process switches; col. 2, lines 8-11, during a process switch from the first process, only that portion of the register state of the first process which is not stored in the floating point register file is stored in a storage device; col. 2, lines 17-24, if no other processes utilize the floating point register file while the first process is not executing, the floating point register file is not saved or loaded. In this manner, disable bits permit the operating system to delay, and possibly avoid, the saving and loading of the floating point register file. Thus, process switch overhead is reduced by reducing the number of registers which must be saved and loaded; col. 1, lines 27-29, when a processor switches from one process to another, a process switch (also termed as a "context switch" or a "task switch") is said to have occurred).
However, Hammond does not disclose a non-transitory computer-readable medium storing processor instructions that includes an instruction, wherein the instructions is configured to, when executed by the processor, cause the aforementioned functionality.
On the other hand, Schuchman discloses a non-transitory computer-readable medium storing processor instructions that includes an instruction, wherein the instructions is configured to, when executed by a processor, cause functionality (col. 4, lines 7-22, machine-readable medium having stored thereon a set of instructions, which when executed by a machine, such as a processor, cause the underlying hardware to perform one or more methods prescribed by the instructions. In one embodiment, the instructions, when executed by a processor, cause the processor to reduce power consumed by the processor. For example, at least one embodiment includes instructions prescribing operations, including specifying a subset of registers for a register operation, such as saving or restoring state information of registers, performing the register operation, and performing a portion of a standby operation. Embodiments may specify a subset of registers to minimize the number of registers involved with the processor switch operation. In one embodiment, a processor switch operation may include a sleep operation, a context switch operation, or an MWAIT operation; col. 4, lines 43-49, processor 160 may have architectural hardware to perform, and allow software to invoke, one or more of the power saving techniques described herein. In other words, various embodiments may have hardware to decode and execute instructions described herein, or instructions or commands similar to the ones described, which enable the power saving techniques; col. 8, lines 45-48, an Instruction Set Architecture (ISA) associated with a processor may enable programs, such as applications or operating systems, to specify registers register sets, or portions thereof; col. 11, lines 24-34, apparatus 200 may comprise a portion of a processor executing code of an operating system and one or more applications. One or more embodiments may allow software, such as an application, a process, or an operating system to save and/or restore state information of a subset of registers, where the saving/restoring of state information is associated with a processor switch operation. For example, the processor switch operation may comprise a switch from one mode of operation to another or a switch from executing the instructions of one thread or process to executing the instructions of another thread or process; col. 11, lines 49-51, an application, process, or OS may save and/or restore state information of a subset of registers to/from persistent memory 290; col. 12, lines 3-9, for example, apparatus 200 may execute instructions that cause apparatus 200 to stop instruction execution during a first mode of operation and enter a second mode of operation, a low-power operating state, until occurrence of an event or class of events, such as executing instructions associated with an MWAIT, MONITOR, HLT, PAUSE, SYSCALL, SYSEXIT, or other instructions; col. 12, lines 37-41, in one or more embodiments, apparatus 200 may perform a processor operation, such as context switch or a switch to a low-power operating mode, by executing instructions of an operating system or an application; col. 12, line 65, to col. 13, line 16, In one embodiment apparatus 200 may perform a save operation for state information of one or more of a subset of registers of RRF 295, a subset of registers 280, and a subset of registers of RAT 235 to persistent memory 290, upon the execution of an MWAIT instruction of apparatus 200. Alternatively, for the sake of an additional example, apparatus 200 may perform a restore operation of previously saved state information from persistent memory 290 to a subset of registers RRF 295, a subset of registers 280, and a subset of registers 235, upon the execution of a context switch between two applications. Stated alternatively, apparatus 200 may execute a series of uops associated with a processor switch operation, via the fetch unit 210, decode unit 220, rename unit 230, execution unit 270, etc., wherein executing one or more of the uops causes apparatus 200 to save or restore state information for a subset or limited number of registers of registers of RRF 295, registers 280, and RAT 235 to/from persistent memory 290; col. 13, lines 52-54, a specific instruction, such as a "SleepWithRegister SetsAndHandler(bitmap* regset, func* handler)" instruction; col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Schuchman with the invention of Hammond to facilitate implementation capability and flexibility. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Hammond as cited above, and the prior art elements of Schuchman as cited above) according to known methods (Examiner submits that implementation of operations via instructions is known. Also see, for example, col. 4, lines 5-11, which lists hardware implementation and software implementation as alternatives) to yield predictable results (the invention of Hammond, implemented via an instruction), which is an example of a rationale that may support a conclusion of obviousness, as per MPEP 2143.
Consider claim 18, the overall combination entails the non-transitory computer-readable medium of claim 17 (see above), wherein the instruction is a protected call instruction (Schuchman, col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
Consider claim 19, the overall combination entails the non-transitory computer-readable medium of claim 17 (see above), wherein: the instruction is a first instruction; the instructions include a second instruction that is a protected call instruction; and the clearing of the remainder of the set of registers is further based on the second instruction (Schuchman, col. 4, lines 7-22, machine-readable medium having stored thereon a set of instructions, which when executed by a machine, such as a processor, cause the underlying hardware to perform one or more methods prescribed by the instructions. In one embodiment, the instructions, when executed by a processor, cause the processor to reduce power consumed by the processor. For example, at least one embodiment includes instructions prescribing operations, including specifying a subset of registers for a register operation, such as saving or restoring state information of registers, performing the register operation, and performing a portion of a standby operation. Embodiments may specify a subset of registers to minimize the number of registers involved with the processor switch operation. In one embodiment, a processor switch operation may include a sleep operation, a context switch operation, or an MWAIT operation; col. 4, lines 43-49, processor 160 may have architectural hardware to perform, and allow software to invoke, one or more of the power saving techniques described herein. In other words, various embodiments may have hardware to decode and execute instructions described herein, or instructions or commands similar to the ones described, which enable the power saving techniques; col. 8, lines 45-48, an Instruction Set Architecture (ISA) associated with a processor may enable programs, such as applications or operating systems, to specify registers register sets, or portions thereof; col. 11, lines 24-34, apparatus 200 may comprise a portion of a processor executing code of an operating system and one or more applications. One or more embodiments may allow software, such as an application, a process, or an operating system to save and/or restore state information of a subset of registers, where the saving/restoring of state information is associated with a processor switch operation. For example, the processor switch operation may comprise a switch from one mode of operation to another or a switch from executing the instructions of one thread or process to executing the instructions of another thread or process; col. 11, lines 49-51, an application, process, or OS may save and/or restore state information of a subset of registers to/from persistent memory 290; col. 12, lines 3-9, for example, apparatus 200 may execute instructions that cause apparatus 200 to stop instruction execution during a first mode of operation and enter a second mode of operation, a low-power operating state, until occurrence of an event or class of events, such as executing instructions associated with an MWAIT, MONITOR, HLT, PAUSE, SYSCALL, SYSEXIT, or other instructions; col. 12, lines 37-41, in one or more embodiments, apparatus 200 may perform a processor operation, such as context switch or a switch to a low-power operating mode, by executing instructions of an operating system or an application; col. 12, line 65, to col. 13, line 16, In one embodiment apparatus 200 may perform a save operation for state information of one or more of a subset of registers of RRF 295, a subset of registers 280, and a subset of registers of RAT 235 to persistent memory 290, upon the execution of an MWAIT instruction of apparatus 200. Alternatively, for the sake of an additional example, apparatus 200 may perform a restore operation of previously saved state information from persistent memory 290 to a subset of registers RRF 295, a subset of registers 280, and a subset of registers 235, upon the execution of a context switch between two applications. Stated alternatively, apparatus 200 may execute a series of uops associated with a processor switch operation, via the fetch unit 210, decode unit 220, rename unit 230, execution unit 270, etc., wherein executing one or more of the uops causes apparatus 200 to save or restore state information for a subset or limited number of registers of registers of RRF 295, registers 280, and RAT 235 to/from persistent memory 290; col. 13, lines 52-54, a specific instruction, such as a "SleepWithRegister SetsAndHandler(bitmap* regset, func* handler)" instruction; col. 11, lines 5-8, an instruction or group of instructions as part of a function, such as a "SleepWithRegisterSet" instruction or function, which may be accessed as an OS system call or an ISA extension; col. 12, line 9, SYSCALL).
Claim(s) 5-6, 14-15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hammond and Schuchman as applied to claims 3, 12, and 20 above, and further in view of Plondke et al. (Plondke) (US 20130067205 A1).
Consider claim 5, the combination thus far entails the system of claim 3 (see above), but does not explicitly disclose that the first instruction and the second instruction are to be executed in parallel.
On the other hand, Plondke explicitly discloses that a first instruction and a second instruction are to be executed in parallel ([0003], lines 5-6, it may be advantageous to execute multiple instructions in parallel).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Plondke with the combination of Hammond and Schuchman in order to increase system performance.
Consider claim 6, the combination thus far entails the system of claim 3 (see above), but does not explicitly disclose the first instruction is received by the processor prior to the second instruction being received by the processor.
On the other hand, Plondke explicitly discloses that a first instruction is received by a processor prior to a second instruction being received by the processor ([0003], line 5, instruction sequences).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Plondke with the combination of Hammond and Schuchman in order to, for example, maintain program correctness in instances where the first instruction and the second instruction cannot be executed in parallel due to, for example, particular dependencies between the two.
Consider claim 14, the combination thus far entails the system of claim 12 (see above), but does not explicitly disclose that the first instruction and the second instruction are to be executed in parallel.
On the other hand, Plondke explicitly discloses that a first instruction and a second instruction are to be executed in parallel ([0003], lines 5-6, it may be advantageous to execute multiple instructions in parallel).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Plondke with the combination of Hammond and Schuchman in order to increase system performance.
Consider claim 15, the combination thus far entails the system of claim 12 (see above), but does not explicitly disclose the first instruction is received by the processor prior to the second instruction being received by the processor.
On the other hand, Plondke explicitly discloses that a first instruction is received by a processor prior to a second instruction being received by the processor ([0003], line 5, instruction sequences).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Plondke with the combination of Hammond and Schuchman in order to, for example, maintain program correctness in instances where the first instruction and the second instruction cannot be executed in parallel due to, for example, particular dependencies between the two.
Consider claim 20, the combination thus far entails the non-transitory computer-readable medium of claim 19 (see above), but does not entail the first instruction and the second instruction are included in a packet.
On the other hand, Plondke explicitly discloses that a first instruction and a second instruction are included in a packet ([0003], lines 5-6, it may be advantageous to execute multiple instructions in parallel; [0003], lines 11-12, instructions encapsulated within a single VLIW packet may be executed in parallel).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Plondke with the combination of Hammond and Schuchman in order to increase system performance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sundaram et al. (US 20040055003 A1) discloses “during the process of context switching the volatile registers that are used are saved and the non-volatile registers are saved if and only if they are used. By not saving/restoring registers that are not being used, the execution overhead for the context switching process is reduced” (see paragraph [0045]), which is relevant to the claimed clearing and preserving.
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/KEITH E VICARY/Primary Examiner, Art Unit 2183
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