DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 17, 18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US PGPub 2018/0122304) in view of Kwak et al (US 8,581,812).
Regarding claim 1, Kim discloses a display apparatus (figs. 1 and 4, display apparatus 100) comprising:
a first pixel arranged in a row and an odd column (fig. 4, pixel PXa connected to Sk and DLj); and
a second pixel arranged in the row and an even column (fig. 4, pixel PXb connected to Sk and DLj+1), wherein each of the first pixel and the second pixel comprises:
a light-emitting diode (fig. 4, EL1 and EL2);
a first transistor (fig. 4, either of transistors T12 and T22) configured to output a current corresponding to a data signal ([0066], “When the first switching transistor T13 and the first transistor T11 are turned on and the data signal Di provided from the j-th data line DLj is applied to the first node N11, the second transistor T12 may be turned on. Accordingly, an amount of a current flowing through the organic light emitting diode EL1 is controlled by the data signal Di, and thus a grayscale of the image may be displayed”); and
a second transistor (fig. 4, either of transistors T11 and T21) transmitting the data signal to the first transistor ([0066], “When the first switching transistor T13 and the first transistor T11 are turned on and the data signal Di provided from the j-th data line DLj is applied to the first node N11, the second transistor T12 may be turned on. Accordingly, an amount of a current flowing through the organic light emitting diode EL1 is controlled by the data signal Di, and thus a grayscale of the image may be displayed”); and
a distribution transistor (fig. 4, either of transistors T13 and T23) connected between the second transistor and a data line configured to supply the data signal (see Fig. 4; [0061], “The first switching transistor T13 provides a data signal Di, sometime called a data output signal Di, from the j-th data line DLj to the first pixel circuit PX1a in response to the scan signal Sk+1 provided through the (k+1)th scan line SLk+1” and [0079], “The second switching transistor T23 applies the data signal Di from the (j+1)th data line DI j+1 to the second pixel circuit PX2b in response to a scan signal Sk+2 provided through the (k+2)th scan line SLk+2”),
wherein, while the second transistor (T11) of the first pixel and the second transistor (T21) of the second pixel are simultaneously activated (fig. 4, transistors T11 and T21 both have their gate connected to Sk line), the distribution transistor (T13) of the first pixel and the distribution transistor (T23) of the second pixel are sequentially activated (fig. 5, Sk+1 and Sk+2 are sequentially activated).
With regard to the activation period of the distribution transistor which is determined by the scan signal period in Kim, while Kim teaches “the active period AP of the scan signal Sk partially overlaps with the active period AP of the scan signal Sk+1”, and further teaches “the active period AP of each of the scan signal Sk and the scan signal Sk+1 should not be limited thereto or thereby” ([0070]), it has been known to have active periods of scan signals not overlap. In a similar field of endeavor of display devices, Kwak discloses wherein the period in which activated and the period in which (column 6, lines 1-6, “Here, the first, second and third clock signals CLA, CLB and CLC for respectively turning on the first transistors MA1, MA2, . . . , MAm, the second transistors MB1, MB2, . . . , MBm, and the third transistors MC1, MC2, . . . , MCm are supplied during different periods which do not overlap with one another”).
In view of the teachings of Kim and Kwak, it would have been obvious to one of ordinary skill in the art to have the activation periods not overlap, as taught by Kwak, within the system of Kim, where Kim teaches at [0070] that although the active periods of the scan signals partially overlap, this should not be limiting and thus implies other alternatives would be known, therefore having the activation periods of Kim to not overlap would have constituted a known alternative for implementation of the intended objectives, and which alternative is furthermore shown to be known in the art by Kwak.
Regarding claim 2, the combination of Kim and Kwak further discloses further comprising:
a first data line (Kim: fig. 1, DL1) connected to the first pixel (Kim: fig. 1, DL1 connected to PXa);
a second data line (Kim: fig. 1, DL2) connected to the second pixel (Kim: fig. 1, DL2 connected to PXb);
an output line (Kim: fig. 1, D1) connected to the first data line and the second data line (Kim: fig. 1, D1 connected to DL1 and DL2); and
a driving circuit (Kim: fig. 1, data driving circuit 140) connected to the output line and configured to supply the data signal through the output line (Kim: [0052], “The data driving circuit 140 outputs data output signals D1 to Dw through a plurality of channels CH1 to CHw in response to the data signal RGB_DATA and the first control signal DCS from the driving controller 120”).
Regarding claim 17, Kim discloses a display apparatus (fig. 1, display device 100) comprising:
a pixel area (fig. 1, display panel 110 and [0045]-[0046], “organic light emitting display panel” including a plurality of pixels) comprising a first pixel arranged in a row and an odd column (fig. 1, PXa) and a second pixel arranged in the row and an even column (fig. 1, PXb); and
a gate driving circuit (fig. 1, scan driving circuit 130) configured to output a gate signal to the first pixel and the second pixel ([0051], “The scan driving circuit 130 sequentially drives the scan lines SL1 to SLn in response to the second control signal SCS from the driving controller 120”), wherein each of the first pixel and the second pixel comprises:
a light-emitting diode (fig. 4, EL1 and EL2);
a first transistor (fig. 4, either of transistors T12 and T22) configured to output a current corresponding to a data signal ([0066], “When the first switching transistor T13 and the first transistor T11 are turned on and the data signal Di provided from the j-th data line DLj is applied to the first node N11, the second transistor T12 may be turned on. Accordingly, an amount of a current flowing through the organic light emitting diode EL1 is controlled by the data signal Di, and thus a grayscale of the image may be displayed”);
a second transistor (fig. 4, either of transistors T11 and T21) transmitting the data signal to the first transistor ([0066], “When the first switching transistor T13 and the first transistor T11 are turned on and the data signal Di provided from the j-th data line DLj is applied to the first node N11, the second transistor T12 may be turned on”) and configured to receive a first gate signal (fig. 4, Sk); and
a distribution transistor (fig. 4, either of transistors T13 and T23) connected between the second transistor and a data line configured to supply the data signal (fig. 4, T13 connected between DLj and T11), and configured to receive a second gate signal (fig. 4, Sk+1 and Sk+2),
wherein a conductivity type of the distribution transistor of the first pixel is same as a conductivity type of the distribution transistor of the second pixel (fig. 4, transistors T13 and T23 are both NMOS transistors),
the second gate signal output by the gate driving circuit to the distribution transistor of the second pixel is delayed from the second gate signal output to the distribution transistor of the first pixel (fig. 5, Sk+2 delayed from Sk+1), and
during a first sub-period of a period in which the second transistors of the first pixel and the second pixel are simultaneously activated in response to the first gate signal output by the gate driving circuit, the distribution transistor of the first pixel is activated and the distribution transistor of the second pixel is not activated ([0073], “Since a period in which the scan signal Sk has the low level and the scan signal Sk+1 has the high level corresponds to the time of the one horizontal period 1H, a data write time tWa in which a data signal DATA(j) is provided to the first node N11 of the first pixel PXa may be obtained by the one horizontal period 1H. When the scan signal Sk+1 is transitioned to the low level, the first switching transistor T13 is turned off”), and during a second sub-period of the period, the distribution transistor of the first pixel is not activated and the distribution transistor of the second pixel is activated ([0075], “A data write time tWb in which a data signal DATA(j+1) is provided to the first node N21 of the second pixel PXb from a time point at which the second selection signal SEL2 is transitioned to the low level to a time point at which the scan signal Sk is transitioned to the high level may be obtained by the one horizontal period 1H. When the scan signal Sk is transitioned to the high level, the first transistor T21 is turned off”).
With regard to the activation period of the distribution transistor which is determined by the scan signal period in Kim, while Kim teaches “the active period AP of the scan signal Sk partially overlaps with the active period AP of the scan signal Sk+1”, and further teaches “the active period AP of each of the scan signal Sk and the scan signal Sk+1 should not be limited thereto or thereby” ([0070]), it has been known to have active periods of scan signals not overlap. In a similar field of endeavor of display devices, Kwak discloses wherein the first sub-period in which (column 6, lines 1-6, “Here, the first, second and third clock signals CLA, CLB and CLC for respectively turning on the first transistors MA1, MA2, . . . , MAm, the second transistors MB1, MB2, . . . , MBm, and the third transistors MC1, MC2, . . . , MCm are supplied during different periods which do not overlap with one another”).
In view of the teachings of Kim and Kwak, it would have been obvious to one of ordinary skill in the art to have the activation periods not overlap, as taught by Kwak, within the system of Kim, where Kim teaches at [0070] that although the active periods of the scan signals partially overlap, this should not be limiting and thus implies other alternatives would be known, therefore having the activation periods of Kim to not overlap would have constituted a known alternative for implementation of the intended objectives, and which alternative is furthermore shown to be known in the art by Kwak.
Regarding claim 18, the combination of Kim and Kwak further discloses further comprising:
a first data line (Kim: fig. 4, DLj) connected to the first pixel (Kim: fig. 4, DLj connected to PXa);
a second data line (Kim: fig. 4, DLj+1) connected to the second pixel (Kim: fig. 4, DLj+1 connected to PXb);
an output line (Kim: fig. 4, Dj) connected to the first data line and the second data line (Kim: fig. 4, Dj connected to DLj and DLj+1); and
a data driving circuit (Kim: fig. 4, selection circuit 150) connected to the output line and configured to supply the data signal through the output line (Kim: [0053], “The selection circuit 150 selectively and electrically connects the channels CH1 to CHw of the data driving circuit 140 to the data lines DL1 to DLm in response to the first and second selection signals SEL1 and SEL2. For instance, responsive to the first and second selection signals SEL1 and SEL2, the selection circuit 150 electrically connects the channel CH1 to one of the data line DL1 and the data line DL2 and electrically connects the channel CHw to one of the data line DLm-1 and the data line DLm”).
Regarding claim 21, the combination of Kim and Kwak further discloses an electronic apparatus (Kim: [0044], “Referring to FIG. 1, the display device 100 includes a display panel 110, a driving controller 120, a scan driving circuit 130, a data driving circuit 140, a selection circuit 150, and a power supply 160”) comprising the display apparatus of claim 1.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim and Kwak in view of Lim et al. (US PGPub 2023/0157112) and Wang (US PGPub 2023/0410746).
Regarding claim 3, while Kim and Kwak teaches a first and second pixel circuit, other types of pixel circuitry are known including using multiple transistors. In a similar field of endeavor of pixels circuits, Lim discloses wherein each of the first pixel and the second pixel further comprises:
a third transistor (fig. 3, transistor T3) connected to a gate of the first transistor (fig. 3, T3 connected to gate of T1) and a first terminal of the first transistor (fig. 3, T3 connected to T1 at D);
a fourth transistor (fig. 3, transistor T4) connected to the gate of the first transistor (fig. 3, T4 connected to gate of T1) and a first initialization voltage line (fig. 3, Vint);
a fifth transistor (fig. 3, transistor T5) connected to a driving voltage line (fig. 3, ELVDD) and the first terminal of the first transistor (fig. 3, T5 connected to D through T1);
a sixth transistor (fig. 3, transistor T6) connected to a second terminal of the first transistor (fig. 3, T6 connected to S through T1) and the light-emitting diode (fig. 3, OLED);
a seventh transistor (fig. 3, transistor T7) connected to the light-emitting diode (fig. 3, OLED) and a second initialization voltage line (fig. 3, Vint, where a first and a second initialization voltage line are the same line); and
a capacitor (fig. 3, C1) connected to the gate of the first transistor (fig. 3, C1 connected to gate of T1)
In view of the teachings of Kim, Kwak and Lim it would have been obvious to one of ordinary skill in the art to use the pixel circuitry to Lim within the system of Kim and Kwak as a known specific pixel circuitry having known advantages such as improved stability, control and other improvements.
While the combination of Kim, Kwak and Lim teaches a capacitor, it has been known to connect a capacitor to a light emitting diode. In a similar field of endeavor of pixel circuitry, Wang discloses a capacitor (fig. 4, C1) connected to the gate of the first transistor (fig. 4, C1 connected to gate of T0) and the light-emitting diode (fig. 4, C1 connected to OLED).
In view of the teachings of Kim, Kwak, Lim and Wang, it would have been obvious to one of ordinary skill in the art to connect the capacitor of Kim, Kwak and Lim to the light-emitting diode, as taught by Wang, for the purpose of signal storage.
Regarding claim 4, the combination of Kim, Kwak, Lim and Wang further discloses wherein the first transistor of each of the first pixel and the second pixel is connected to the light-emitting diode (Kim: fig. 4, T12 and T22 connected to EL1 and EL2), and
the first transistor further comprises a back gate facing the gate of the first transistor (Wang: [0024] dual gate transistor T0).
Claims 5-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Kwak, Lim and Wang further in view of Yu et al. (US PGPub 2024/0381715).
Regarding claim 5, the combination of Kim, Kwak, Lim and Wang further discloses further comprising:
a first gate line (Lim: fig. 4, GWL) configured to supply a first gate signal ;
a second gate line (Lim: fig. 4, GIL) configured to supply a second gate signal to the fourth transistor of the first pixel and the fourth transistor of the second pixel (Lim: [0086], “The first to ninth transistors T1 to T9, the first capacitor C1, and the second capacitor C2 are connected to first to fourth scan lines GWL, GCL, GIL, and GBL configured to respectively transfer first to fourth scan signals GW, GC, GI, and GB”);
a third gate line (Lim: fig. 4, EML) configured to supply a third gate signal to the fifth transistor and the sixth transistor of the first pixel, and to the fifth transistor and the sixth transistor of the second pixel (Lim: [0086], “the emission control line EML configured to transfer an emission control signal EM”); and
a fourth gate line (Lim: fig. 4, GBL) configured to supply a fourth gate signal to the seventh transistor of the first pixel and the seventh transistor of the second pixel (Lim: [0086], “The first to ninth transistors T1 to T9, the first capacitor C1, and the second capacitor C2 are connected to first to fourth scan lines GWL, GCL, GIL, and GBL configured to respectively transfer first to fourth scan signals GW, GC, GI, and GB, the data line DL configured to transfer a data voltage Dm, the emission control line EML configured to transfer an emission control signal EM, the power line PL configured to transfer the first driving voltage ELVDD, a first voltage line VL1 configured to transfer an initialization voltage Vint, a second voltage line VL2 configured to transfer a reference voltage Vref, a third voltage line VL3 configured to transfer a bias voltage Vbias, and a common electrode to which the second driving voltage ELVSS is applied”).
While the combination of Kim, Kwak, Lim and Wang teaches a first gate line, it has been known to connect the gate line to the second and third transistors. In a similar field of endeavor of display devices, Yu discloses a first gate line (fig. 5, S1) configured to supply a first gate signal to the second transistor and the third transistor of the first pixel, and to the second transistor and the third transistor of the second pixel ([0081] and [0083] control of second transistor T2 and control of fourth transistor T4 connected to S1).
In view of the teachings of Kim, Kwak, Lim, Wang and Yu, it would have been obvious to one of ordinary skill in the art to include the signal S1 of Yu within the circuitry of Kim, Kwak, Lim and Wang, for the purpose of supplying a known signal to a plurality of transistor to achieve expected results and reduce the required number of signals.
Regarding claim 6, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein a conductivity type of the distribution transistor of the first pixel is same as a conductivity type of the distribution transistor of the second pixel (Kim: fig. 4, T12 and T23 are both nmos transistors).
Regarding claim 7, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein the fourth gate signal supplied to the seventh transistor of the second pixel is delayed from the fourth gate signal supplied to the seventh transistor of the first pixel (Lim: where there would be a delay for a signal to travel along a signal line),
the fourth gate signal supplied to the seventh transistor of the first pixel and the fourth gate signal supplied to the distribution transistor of the first pixel have same timings as each other, and the fourth gate signal supplied to the seventh transistor of the second pixel and the fourth gate signal supplied to the distribution transistor of the second pixel have same timings as each other (Lim: fig. 3 and [0103], GBL supplied to T7 and transistor T9 where T9 supplies a bias voltage to the driving transistor).
Regarding claim 8, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein a period in which the first gate signal is a level voltage for activating the second transistor comprises a first sub-period and a second sub-period following the first sub-period, a period in which the fourth gate signal is a level voltage for activating the distribution transistor of the first pixel overlaps the first sub-period, a period in which the fourth gate signal is a level voltage for activating the distribution transistor of the second pixel overlaps the second sub-period (Kim: fig. 5, Sk+1 and Sk+2 are sequentially activated and overlap), and
the period in which the fourth gate signal is the level voltage for activating the distribution transistor of the first pixel and the period in which the fourth gate signal is the level voltage for activating the distribution transistor of the second pixel do not overlap each other (Kim: fig. 5, SEL1 and SEL2 do not overlap each other).
Regarding claim 9, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein the second gate signal delayed from the second gate signal supplied to the fourth transistor of the first pixel is supplied to the distribution transistor of the first pixel (Kim: fig. 5, Sk+1 delayed from Sk),
the second gate signal delayed from the second gate signal supplied to the fourth transistor of the second pixel is supplied to the distribution transistor of the second pixel (Kim: fig. 5, Sk+2 delayed from Sk+1),
the second gate signal supplied to the fourth transistor of the first pixel and the second gate signal supplied to the fourth transistor of the second pixel have same timings as each other (Lim: fig. 3, signal GIL), and
the second gate signal supplied to the distribution transistor of the second pixel is delayed from the second gate signal supplied to the distribution transistor of the first pixel (Kim: fig. 5, Sk+2 delayed from Sk+1).
Regarding claim 10, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein a period in which the first gate signal is a level voltage for activating the second transistor comprises a first sub-period and a second sub-period following the first sub-period, a period in which the second gate signal is a level voltage for activating the distribution transistor of the first pixel overlaps the first sub-period, a period in which the second gate signal is a level voltage for activating the distribution transistor of the second pixel overlaps the second sub-period (Kim: fig. 5, Sk+1 and Sk+2 are sequentially activated and overlap), and
the period in which the second gate signal is the level voltage for activating the distribution transistor of the first pixel and the period in which the second gate signal is the level voltage for activating the distribution transistor of the second pixel do not overlap each other (Kim: fig. 5, SEL1 and SEL2 do not overlap each other).
Regarding claim 11, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein a period in which the fourth gate signal is a level voltage for activating the seventh transistor overlaps the period in which the first gate signal is the level voltage for activating the second transistor (Wang: fig. 5, activation of signals S1 and S2 overlap each other in t1).
Regarding claim 12, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein a conductivity type of the distribution transistor of the first pixel is different from a conductivity type of the distribution transistor of the second pixel (Kim: fig. 8, transistors STj and STj+1 can act as the distribution transistors and have different conductivity types where 150a is the selection circuit).
Regarding claim 13, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein the third gate signal delayed from the third gate signal supplied to the fifth transistor of the first pixel is supplied to the distribution transistor of the first pixel and the distribution transistor of the second pixel (Kim: figs. 6 and 7, SEL1 connected to transistors STj and STj+1).
Regarding claim 14, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein, in a period in which the first gate signal is a level voltage for activating the second transistor, a voltage level of the third gate signal supplied to the distribution transistor of the first pixel and the distribution transistor of the second pixel is changed (Kim: figs. 6 and 7, SEL1 connected to transistors STj and STj+1 where the transistors are activated oppositely).
Regarding claim 15, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein a period in which the fourth gate signal is a level voltage for activating the seventh transistor overlaps the period in which the first gate signal is the level voltage for activating the second transistor (Wang: fig. 5, activation of signals S1 and S2 overlap each other in t1).
Regarding claim 16, the combination of Kim, Kwak, Lim, Wang and Yu further discloses wherein a conductivity type of the fifth transistor is different from a conductivity type of the second transistor (Lim: fig. 3, transistor T2 is a different conductivity type as transistor T5).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lim, Wang and Zhang et al. (US PGPub 2024/0373686).
Regarding claim 19, Kim discloses a display apparatus (fig. 1, display device 100) comprising:
a pixel area (fig. 1, display panel 110 and [0045]-[0046], “organic light emitting display panel” including a plurality of pixels) comprising a first pixel arranged in a row and an odd column (fig. 1, PXa) and a second pixel arranged in the row and an even column (fig. 1, PXb); and
a gate driving circuit (fig. 1, scan driving circuit 130) configured to output a gate signal to the first pixel and the second pixel ([0051], “The scan driving circuit 130 sequentially drives the scan lines SL1 to SLn in response to the second control signal SCS from the driving controller 120”), wherein each of the first pixel and the second pixel comprises:
a light-emitting diode (fig. 6, EL3 and EL4);
a first transistor (fig. 6, transistors T32 and T42) configured to output a current corresponding to a data signal (fig. 6, function of transistors T32 and T42);
a second transistor (fig. 6, transistors T31 and T41) transmitting the data signal to the first transistor (fig. 6, function of T31 and T41) and configured to receive a first gate signal (fig. 6, Sk); and
a distribution transistor (fig. 6, transistors STj and STj+1) connected between the second transistor and a data line configured to supply the data signal (fig. 6, STj and STj+1 connected to Di and T31 and T41), and configured to receive a second gate signal (fig. 6, SEL1),
wherein a conductivity type of the distribution transistor of the first pixel is different from a conductivity type of the distribution transistor of the second pixel ([0089], “The transistor STj is a PMOS transistor, and the transistor STj+1 is an NMOS transistor”),
in a period in which the second transistors of the first pixel and the second pixel are simultaneously activated in response to the first gate signal output by the gate driving circuit, a voltage level of the second gate signal output by the gate driving circuit is changed (fig. 7, Sk), and
in a first sub-period of the period, the distribution transistor of the first pixel is activated and the distribution transistor of the second pixel is not activated (fig. 7, tWa), and in a second sub-period of the period, the distribution transistor of the first pixel is not activated and the distribution transistor of the second pixel is activated (fig. 7, tWb).
While Kim teaches a first and second pixel circuit, other types of pixel circuitry are known including using multiple transistors. In a similar field of endeavor of pixels circuits, Lim discloses wherein each of the first pixel and the second pixel further comprises:
a third transistor (fig. 3, transistor T3) connected to a gate of the first transistor (fig. 3, T3 connected to gate of T1) and a first terminal of the first transistor (fig. 3, T3 connected to T1 at D);
a fourth transistor (fig. 3, transistor T4) connected to the gate of the first transistor (fig. 3, T4 connected to gate of T1) and a first initialization voltage line (fig. 3, Vint);
a fifth transistor (fig. 3, transistor T5) connected to a driving voltage line (fig. 3, ELVDD) and the first terminal of the first transistor (fig. 3, T5 connected to D through T1);
a sixth transistor (fig. 3, transistor T6) connected to a second terminal of the first transistor (fig. 3, T6 connected to S through T1) and the light-emitting diode (fig. 3, OLED);
a seventh transistor (fig. 3, transistor T7) connected to the light-emitting diode (fig. 3, OLED) and a second initialization voltage line (fig. 3, Vint, where a first and a second initialization voltage line are the same line); and
a capacitor (fig. 3, C1) directly connected to the gate of the first transistor (fig. 3, C1 connected to gate of T1)
In view of the teachings of Kim and Lim it would have been obvious to one of ordinary skill in the art to use the pixel circuitry to Lim within the system of Kim as a known specific pixel circuitry having known advantages such as improved stability, control and other improvements.
While the combination of Kim and Lim teaches a capacitor, it has been known to connect a capacitor to a light emitting diode. In a similar field of endeavor of pixel circuitry, Wang discloses a capacitor (fig. 4, C1) directly connected to the gate of the first transistor (fig. 4, C1 connected to gate of T0) and the light-emitting diode (fig. 4, C1 connected to OLED).
In view of the teachings of Kim, Lim and Wang, it would have been obvious to one of ordinary skill in the art to connect the capacitor of Kim and Lim to the light-emitting diode, as taught by Wang, for the purpose of signal storage.
While the combination of Kim, Lim and Wang discloses transistors connected to a voltage initialization line, it has been known to have a first and a second initialization voltage lines. In a similar field of endeavor of display devices, Zhang discloses a fourth transistor directly connected to a first initialization voltage line (fig. 1, T1 connected to Vinit1) and a seventh transistor directly connected to a second initialization voltage line (fig. 1, T7 connected to Vinit2).
In view of the teachings of Kim, Lim, Wang and Zhang it would have been obvious to one of ordinary skill in the art to include a second initialization voltage line, as taught by Zhang, within the system of Kim, Kwak, Lim and Wang, for the purpose of providing the known benefit of stabilizing luminance uniformity across high-resolution panels.
Regarding claim 20, the combination of Kim, Lim, Wang and Zhang further discloses further comprising:
a first data line (Kim: fig. 4, DLj) connected to the first pixel (Kim: fig. 4, DLj connected to PXa);
a second data line (Kim: fig. 4, DLj+1) connected to the second pixel (Kim: fig. 4, DLj+1 connected to PXb);
an output line (Kim: fig. 4, Dj) connected to the first data line and the second data line (Kim: fig. 4, Dj connected to DLj and DLj+1); and
a data driving circuit (Kim: fig. 4, selection circuit 150) connected to the output line and configured to supply the data signal through the output line (Kim: [0053], “The selection circuit 150 selectively and electrically connects the channels CH1 to CHw of the data driving circuit 140 to the data lines DL1 to DLm in response to the first and second selection signals SEL1 and SEL2. For instance, responsive to the first and second selection signals SEL1 and SEL2, the selection circuit 150 electrically connects the channel CH1 to one of the data line DL1 and the data line DL2 and electrically connects the channel CHw to one of the data line DLm-1 and the data line DLm”).
Response to Arguments
Applicant’s arguments with respect to claims 1, 17, 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
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