DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-15 are pending.
Claim Objections
Claims and 11 are objected to because of the following informalities:
Claim 7, line 2, should read “between the gate electrode and the hole collector electrode.”
Appropriate correction is required.
Claim 11, line 1, should read “The enhancement mode GaN transistor of claim 1” for consistency. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 6 recites the limitation "wherein the stack of layers further comprises indium" in line 1. Specifically, claim 6 depends from claim 4, which then depends from claim 3, which depends from claim 2, which depends from claim 1, none of which recite a limitation of “a stack of layers.” There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, claim 6 will be interpreted to depend from claim 5, as supported by at least Fig. 13G.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999).
Regarding claim 9, the term “implemented” is used by the claim to mean “formed in,” while the accepted meaning is “to take steps to put into practice” or “to give practical effect to and ensure actual fulfillment by concrete measures” as defined by Merriam Webster’s dictionary. The term is indefinite because the specification does not clearly redefine the term. For purposes of examination, it will be interpreted that the applicant intends that the circuit comprises an element with a GaN material, in order to enable integration in the same device as the transistor in the claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 7, 8, 9, and 11 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5, 9, 10, 11 of copending U.S. Patent Application No. 18/436,352. Although the claims at issue are not identical, they are not patentably distinct from each other because:
19/207,772 (Instant Application)
18/436,352
Claim 1:
An enhancement mode GaN transistor, comprising:
a source electrode,
a gate electrode,
a drain electrode, (Electrodes are inherent to source, gate, and drain components)
and a hole collector electrode,
wherein the gate electrode and the hole collector electrode contact a GaN layer that serves as both GaN gate material under the gate electrode and as a connection from the GaN gate material layer to the hole collector electrode;
and wherein, when a negative voltage is applied to the hole collector electrode relative to the source electrode, holes in the GaN gate material are removed. (Application of a voltage must inherently be done relative to a reference point, per application 18/436,352, the source electrode and hole collector electrode are a part of the same circuit, and therefore choice the source as a reference point is obvious)
Claim 1:
An enhancement mode gallium nitride (GaN) transistor, comprising:
a source,
a gate and a drain,
wherein the gate comprises a p-type GaN material disposed over a front barrier layer and a gate electrode disposed over the p-type GaN material,
and a hole collector electrode,
wherein the gate electrode and the hole collector electrode contact the p-type GaN material of the gate,
and wherein, when a negative voltage is applied to the hole collector electrode, holes accumulating in the p-type GaN material of the gate are substantially eliminated removed.
Claim 7:
The enhancement mode GaN transistor of claim 1,
wherein the GaN layer has a recess between gate electrode and the hole collector electrode.
Claim 3:
The enhancement mode GaN transistor of claim 1, wherein the hole collector electrode is laterally spaced from the gate electrode on a top surface of the p-type GaN material of the gate.
Claim 5:
The enhancement mode GaN transistor of claim 3,
wherein the hole collector electrode extends into a recess in the p-type GaN material of the gate.
Claim 8:
The enhancement mode transistor of claim 1, wherein the hole collector electrode extends into the GaN gate material.
Claim 3:
The enhancement mode GaN transistor of claim 1, wherein the hole collector electrode is laterally spaced from the gate electrode on a top surface of the p-type GaN material of the gate.
Claim 5:
The enhancement mode GaN transistor of claim 3,
wherein the hole collector electrode extends into a recess in the p-type GaN material of the gate.
Claim 9:
The enhancement mode transistor of claim 1, wherein the hole collector electrode is electrically connected to an internal negative voltage power supply implemented in GaN.
Claim 9:
The enhancement mode GaN transistor of claim 1, wherein the hole collector electrode is electrically connected to a negative voltage generating circuit.
Claim 10:
The enhancement mode GaN transistor of claim 9, wherein the negative voltage generating circuit is formed in GaN and is integrated with the transistor
Claim 10:
The enhancement mode GaN transistor of claim 1, wherein the negative voltage is provided by a silicon IC co-packaged with the enhancement mode GaN transistor.
(The negative voltage generating circuit, if integrated with the transistor, must be co-packaged with it, necessarily).
Claim 10:
The enhancement mode GaN transistor of claim 9, wherein the negative voltage generating circuit is integrated with the transistor.
Claim 11:
The enhancement mode transistor of claim 1, wherein the negative voltage is provided externally through an I/O terminal.
Claim 14:
The enhancement mode GaN transistor of claim 1, wherein the negative voltage is provided externally through an I/O terminal.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims 2, 3, 5, and 6 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/436,352 in view of Cao et al. (US PGPub 2018/0366559; herein known as Cao).
Regarding claim 2, copending application 18/436,352 teaches the enhancement mode GaN transistor of claim 1, but does not explicitly teach wherein the GaN layer comprises AlxGayln(1-x-y)N.
Cao teaches (Fig. 8) wherein the GaN layer (508, [0031]) comprises AlxGayln(1-x-y)N ([0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include wherein the GaN layer comprises AlxGayln(1-x-y)N in order to provide favorable etch selectivity during manufacture (Cao, [0031]).
Regarding claim 3, copending application 18/436,352 in view of Cao teaches the enhancement mode GaN transistor of claim 2 wherein the GaN layer (Cao, 508, [0031]) further comprises a p-type dopant (Cao, [0031]).
Regarding claim 5, copending application 18/436,352 teaches the enhancement mode GaN transistor of claim 1, but does not explicitly teach wherein the GaN gate material comprises a stack of layers, the stack of layers comprising at least one GaN layer and at least one AlGaN layer.
Cao teaches (Fig. 8) wherein the GaN gate material comprises a stack of layers, the stack of layers comprising at least one GaN later (508, [0031]) and at least one AlGaN layer (507, [0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Okamoto and of Cao to include wherein the GaN gate material comprises a stack of layers, the stack of layers comprising at least one GaN layer and at least one AlGaN layer in order to provide favorable etch selectivity during manufacture (Cao, [0031]).
Regarding claim 6, copending application 18/436,352 in view of Cao teaches (Cao, Fig. 8) the enhancement mode GaN transistor of claim 4, wherein the stack of layers further comprises indium (Cao, [0031], 508 can contain Indium).
Claim 4 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/436,352 in view of Cao, and further in view of Lidow (US PGPub 2010/0258848; herein known as Lidow).
Regarding claim 4, copending application 18/436,352 in view of Cao teaches the enhancement mode GaN transistor of claim 3, but does not explicitly teach wherein the GaN layer is compensated.
Lidow teaches wherein the GaN layer is compensated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Okamoto in view of Cao and of Lidow to include wherein the GaN layer is compensated in order to reduce gate leakage (Lidow, [0009]).
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okamoto et al. (US PGPub 2010/0320505; herein known as Okamoto).
Regarding claim 1, Okamoto teaches (Fig. 9B) an enhancement mode GaN transistor ([0116]), comprising:
a source electrode (5, [0124]), a gate electrode (7, [0125]), a drain electrode (6, [0125]), and a hole collector electrode (8, [0126]),
wherein the gate electrode (7) and the hole collector electrode (8) contact a GaN layer (25, [0116]) that serves as both GaN gate material ([0116]) under the gate electrode and as a connection from the GaN gate material layer to the hole collector electrode; (the GaN gate material is located under and contacts the gate electrode and contacts the hole collector electrode)
and wherein, when a negative voltage is applied to the hole collector electrode relative to the source electrode, holes in the GaN gate material are removed. Application of a negative voltage to the hole collector electrode, relative to source, of Okamoto would switch the transistor to its “on” state, during which time the hole collector electrode, in contact with the p-type GaN material, would necessarily conduct holes from the p-type GaN material-of the gate and remove them from the device.
Regarding claim 7, Okamoto teaches (Fig. 9B) the enhancement mode GaN transistor of claim 1, wherein the GaN layer (25, [0116]) has a recess (source electrode 5 is recessed into gate material) between gate electrode (7) and the hole collector electrode (8, [0126]).
Regarding claim 8, Okamoto teaches (Fig. 9B) the enhancement mode GaN transistor of claim 1, wherein the hole collector electrode (8, [0126]) extends into the GaN gate material (25, [0116]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 5, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Okamoto as applied to claim 1 above, and further in view of Cao et al. (US PGPub 2018/0366559; herein known as Cao).
Regarding claim 2, Okamoto teaches the enhancement mode GaN transistor of claim 1, but does not explicitly teach wherein the GaN layer comprises AlxGayln(1-x-y)N.
Cao teaches (Fig. 8) wherein the GaN layer (508, [0031]) comprises AlxGayln(1-x-y)N ([0031]).
Because Okamoto and Cao are both directed toward enhancement mode transistor gate structures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Okamoto and of Cao to include wherein the GaN layer comprises AlxGayln(1-x-y)N in order to provide favorable etch selectivity during manufacture (Cao, [0031]).
Regarding claim 3, Okamoto in view of Cao teaches (Cao, Fig. 8) the enhancement mode GaN transistor of claim 2, wherein the GaN layer (Cao, 508, [0031]) further comprises a p-type dopant (Cao, [0031]).
Regarding claim 5, Okamoto teaches the enhancement mode GaN transistor of claim 1, but does not explicitly teach wherein the GaN gate material comprises a stack of layers, the stack of layers comprising at least one GaN layer and at least one AlGaN layer.
Cao teaches (Fig. 8) wherein the GaN gate material comprises a stack of layers, the stack of layers comprising at least one GaN later (508, [0031]) and at least one AlGaN layer (507, [0031]).
Because Okamoto and Cao are both directed toward enhancement mode transistor gate structures, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Okamoto and of Cao to include wherein the GaN gate material comprises a stack of layers, the stack of layers comprising at least one GaN layer and at least one AlGaN layer in order to provide favorable etch selectivity during manufacture (Cao, [0031]).
Regarding claim 6, Okamoto in view of Cao teaches (Cao, Fig. 8) the enhancement mode GaN transistor of claim 5, wherein the stack of layers further comprises indium (Cao, [0031], 508 can contain Indium).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Okamoto in view of Cao as applied to claim 3 above, and further in view of Lidow et al. (US PGPub 2010/0258848; herein known as Lidow).
Regarding claim 4, Okamoto in view of Cao teach the enhancement mode GaN transistor of claim 3, but does not explicitly teach wherein the GaN layer is compensated.
Lidow teaches wherein the GaN layer is compensated.
Because Okamoto in view of Cao and Lidow are both directed toward enhancement mode GaN transistors, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Okamoto in view of Cao and of Lidow to include wherein the GaN layer is compensated in order to reduce gate leakage (Lidow, [0009]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Okamoto as applied to claim 1 above, and further in view of Wu et al. (US PGPub 2014/0015066; herein known as Wu).
Regarding claim 9, Okamoto teaches the enhancement mode GaN transistor of claim 1, but does not explicitly teach wherein the hole collector electrode is electrically connected to an internal negative voltage power supply implemented in GaN.
Wu teaches (Fig. 6) a negative voltage generating circuit ([0050]).
Because Okamoto and Wu are directed toward enhancement mode GaN transistors, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Okamoto and Wu to include a negative voltage generating circuit in order to induce electron recombination (Wu, [0062]). Wu teaches wherein the circuit components are part of a HEMT device. ([0003]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Okamoto as applied to claim 1 above, and further in view of Then et al. (US PGPub 2022/0102344; herein known as Then).
Regarding claim 10, Okamoto teaches the enhancement mode GaN transistor of claim 1, but does not explicitly teach wherein the negative voltage is provided by a silicon IC co-packaged with the enhancement mode GaN transistor.
Then teaches wherein the negative voltage is provided by a silicon IC co-packaged with the enhancement mode GaN transistor. Then teaches ([0324]) multi-chip modules and system-in-package embodiments which incorporate an integrated circuit in the same package as another device. Because Okamoto and Then are both directed toward enhancement mode GaN transistors, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Okamoto and of Then to include wherein the negative voltage is provided by a silicon IC co-packaged with the enhancement mode GaN transistor in order to provide improved semiconductor package configurations (Then, [0321]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Okamoto as applied to claim 1 above, and further in view of Mandelli et al. (US PGPub 2019/0246051; herein known as Mandelli).
Regarding claim 11, Okamoto teaches the enhancement mode transistor of claim 1, but does not explicitly teach wherein the negative voltage is provided externally through an I/O terminal.
Mandelli teaches wherein the negative voltage ([0030]) is provided externally through an I/O terminal ([0027]; Pixel 300 is compatible with the image sensor 200, which contains I/O circuitry). Because Okamato and Mandelli are both directed toward enhancement mode GaN transistors for hole collection, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Okamato and Mandelli to include wherein the negative voltage is provided externally through an I/O terminal in order to convey pixel signals to other circuitry for processing (Mandelli, [0027]).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lidow in view of Okamoto and Nishimori et al. (US PGPub 2014/0084339; herein known as Nishimori).
Regarding claim 12, Lidow teaches (Figs. 3A-3E) a method of manufacturing an enhancement mode transistor, the method comprising:
depositing a GaN layer (15, [0023])) onto a barrier layer (14, [0023]) of an epitaxial structure ([0024]), the epitaxial structure comprising:
a silicon substrate (11, [0024]);
one or more buffer layers (13, [0024]) disposed on the silicon substrate;
a channel layer (inherently formed at the heterojunction of the barrier and buffer layers, [0024]) disposed on the one or more buffer layers;
and the barrier layer (14, [0024]) disposed on the channel layer;
depositing a gate metal layer (17, [0025]) onto the GaN layer;
etching a second portion of the gate metal layer and the GaN layer to form a gate contact (17, [0027]);
depositing a first dielectric layer (18, [0027]) over the gate metal layer, the GaN layer, and the barrier layer;
forming a source contact (20, [0023]) and a drain contact (19, [0028]) through the first dielectric layer (18) and the barrier layer (14) to contact the channel layer ([0028]);
a second connection to the gate contact to form a gate electrode, a third connection to the source contact to form a source electrode, and a fourth connection to the drain contact to form a drain electrode (Not shown, electrodes are inherent to source, gate, and drain components of field effect transistors).
Lidow does not explicitly teach: etching a first portion of the gate metal layer and forming a hole collection contact on the GaN layer; depositing a second dielectric layer over the first dielectric layer, the source contact, and the drain contact; nor forming a first connection to the hole collection contact to form a hole collector electrode.
Okamoto teaches (Fig. 9A) forming a hole collection contact (8, [0126]) on the GaN layer (4, [0126]), and forming a first connection (13, [0138]) to the hole collection contact (8) to form a hole collector electrode (part of the hole collection contact 8, [0138]).
Because Lidow and Okamoto are both directed toward enhancement mode transistors, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lidow and of Okamoto to include forming a hole collection contact on the GaN layer, and forming a first connection to the hole collection contact to form a hole collector electrode in order to enable extraction of holes from the FET device operating at high speed and at a high voltage (Okamoto, [0032]).
Lidow in view of Okamoto does not explicitly teach depositing a second dielectric layer over the first dielectric layer, the source contact, and the drain contact.
Nishimori teaches a second dielectric layer over the first dielectric layer, the source contact, and the drain contact ([0103]).
Because Lidow in view of Okamoto and Nishimori are directed toward enhancement mode FETs, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lidow in view of Okamoto and of Nishimori to include teaches a second dielectric layer over the first dielectric layer, the source contact, and the drain contact in order to provide chip protection (Nishimori, [0103]).
Regarding claim 13, Lidow in view of Okamoto and Nishimori teaches the method of claim 12, wherein the hole collection contact is formed with a portion of the gate metal layer. Lidow teaches wherein gate contacts are all formed during a same gate etch process and Okamoto teaches wherein the hole collection contact is formed, therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Lidow in view of Okamoto and Nishimori to include wherein the hole collection contact is formed with a portion of the gate metal layer in order to reduce the number of manufacturing steps required, and additionally to create self-aligned gate structures (Lidow, [0038]).
Regarding claim 14, Lidow in view of Okamoto and Nishimori teaches the method of claim 12, wherein the hole collection contact (Okamoto, Fig. 9B, 8, [0053]) is formed by depositing a second metal on the GaN layer (4, [0053]).
Regarding claim 15, Lidow in view of Okamoto and Nishimori teaches (Lidow, Fig. 7C) the method of claim 12, wherein etching the first portion of the gate metal layer (17, [0026]) comprises etching a portion of the GaN layer (15, [0026]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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