Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
The amendment filed 28 September 2026 has been entered.
Claims 1, 5 and 7 are amended; claims 2–4, 6 and 8–17 are unchanged; the replacement paragraph for paragraph [0102] of the specification is entered.
Claims 1–17 are pending; claims 1–6 are examined; claims 7–17 remain withdrawn.
Applicant’s arguments, see page 9, filed 28 September 2026, with respect to claims 5 and 6 have been fully considered and are persuasive. The rejection of claims 5 and 6 under 35 U.S.C. 112(b) has been withdrawn. The amendment of claim 5 replaces ‘adjacent to’ with ‘arranged next to’.
Applicant’s Statement of the Substance of the Interview
Applicant’s statement of the substance of the interview of 8 September 2026 (Remarks filed 28 September 2026, page 9) states: “It is acknowledged that the discussed claim amendments will overcome the present rejections.” That statement is inaccurate on a point bearing on patentability, and an accurate version is set out here (MPEP § 713.04).
The examiner gave no indication that the discussed amendment would overcome the rejections. As recorded in the Examiner Interview Summary mailed 11 September 2026: “The examiner explained that the newly proposed claim amendment would require additional search, consideration, and examination, and that no indication as to patentability could be provided at this time.” “No agreement was reached pertaining to the allowability of the claims or as to the sufficiency of the identified support.”
Identification of Support for the Amended Claims
The amendment adds to claim 1 (and to withdrawn claim 7) the limitations “independent of gate signals of sub-pixels of the first pixel group” and “independent of the gate signals of the sub-pixels of the second pixel group”.
The Remarks identify support only generally, as “FIGS. 7, 10, 12, 13A, 13B of the Application and the related descriptions” (page 10), and at the interview applicant’s representative identified FIG. 12.
The phrase “independent of gate signals” does not appear in the original disclosure.
Applicant should, in the reply to this action, point out with particularity, by paragraph number and figure, where the original disclosure describes that the data lines of each pixel group receive the recited voltages independent of the gate signals of the sub-pixels of that group.
See MPEP §§ 714.02 and 2163.06 (“Applicant should therefore specifically point out the support for any amendments made to the disclosure.”).
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 601, 602 and 603 (FIG. 12).
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The description identifies the switch parts of the switch circuit 300 as 61, 62 and 63 [e.g., Instant Specification Paragraph 109: the switch circuit 300 includes a plurality of switch parts 61, 62 and 63; Fig. 12: 601, 602, 603; Fig. 13A: 61; Fig. 13B: 62].
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 63 (paragraphs [0109]–[0114]; FIG. 13A shows the switch part 61 and FIG. 13B the switch part 62, and no figure shows the switch part 63).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because FIGS. 5, 6, 9, 11 and 15 label the one-frame period ‘1Fame’ (see paragraph [0099], which describes the one frame period), and FIG. 15 labels both the first and the second sub-frame periods ‘SF1’, whereas the description and FIG. 16 identify a first sub-frame period SF1, a second sub-frame period SF2 and a third sub-frame period SF3 [e.g., Instant Specification Paragraph 121: one frame period may be divided in time into a first sub-frame period SF1, a second sub-frame period SF2, and a third sub-frame period SF3; Fig. 15: SF1, SF1, SF3; Fig. 16: SF1, SF2, SF3].
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
(a) paragraph [0106] describes the second pixel group with the same words as the first pixel group, as including “odd-numbered sub-pixels of odd-numbered pixel lines” [e.g., Instant Specification Paragraph 106: The second pixel group including odd-numbered sub-pixels of odd-numbered pixel lines L1, L3 . . . L7 and odd-numbered sub-pixels of even-numbered pixel lines L2, L4 . . . L8 may be turned off during the first sub-frame period SF1 and turned on during the second sub-frame period SF2.; Fig. 10: SF1, L1, C2, L2, C1], whereas FIG. 10 shows the second pixel group as the even-numbered sub-pixels of the odd-numbered pixel lines and the odd-numbered sub-pixels of the even-numbered pixel lines;
(b) paragraph [0118] refers to “the fourth transistor M12” [e.g., Instant Specification Paragraph 118: The fourth transistor M12 is connected between the first input node and the second data line 132; Fig. 13A: M14; Fig. 13B: M14], where the fourth transistor is M14, as the remainder of the paragraph and FIGS. 13A and 13B identify it, M12 being the second transistor (paragraph [0116]);
(c) paragraph [0127] refers to “data lines DL2 and DL4 of the second pixel group” [e.g., Instant Specification Paragraph 127: The data lines DL2 and DL4 of the second pixel group may be connected to the sub-pixels SP2 of the second pixel group; Instant Specification Paragraph 127: data lines DL2 and DL5 of the second pixel group], where the same paragraph identifies the data lines of the second pixel group as DL2 and DL5 and DL4 as a data line of the first pixel group;
(d) paragraph [0147] refers to “the third switch signal SW2” [e.g., Instant Specification Paragraph 147: The fifth transistor M35 is connected between the first input node and the third data line DL3, and is turned on in response to the gate-on voltage Von of the third switch signal SW2.; Instant Specification Paragraph 147: a gate electrode connected to the third gate node to which the third switch signal SW3 is applied], where the third switch signal is SW3 (paragraphs [0127] and [0129]); and
(e) paragraph [0100] identifies VGL as the gate-on voltage and VGH as the gate-off voltage of the gate signal [e.g., Instant Specification Paragraph 100: ‘VGL’ indicates the gate-on voltage of the gate signal, and ‘VGH’ indicates the gate-off voltage of the gate signal], consistent with the p-channel pixel transistors of paragraphs [0086] and [0088], whereas FIG. 7 draws the pulses of the gate signals SCAN(1) to SCAN(n), in response to which the sub-pixels are charged [e.g., Instant Specification Paragraph 103: The sub-pixels of the first and second pixel groups are charged with the data voltage Vdata or black grayscale voltage Vblack in response to the pulses of the gate signals SCAN1 to SCAN(n); Fig. 7: SCAN(1)–SCAN(n), VGH, VGL], at the VGH level; the description and the drawing do not agree.
Appropriate correction is required.
Claim Interpretation
The following readings are applied under the broadest reasonable interpretation consistent with the specification.
(a) Independent of gate signals of sub-pixels of the first pixel group (claim 1, and the counterpart for the second pixel group) is read as reciting that the first data voltage and the black grayscale voltage that the data lines of a pixel group receive are supplied to those data lines, and selected between, by circuitry and control signals other than the gate signals of that group’s sub-pixels, the gate signals serving to write the voltage present on a data line into the sub-pixel.
The specification supplies the data voltage and the black grayscale voltage to the data lines through a switch circuit under switch signals from the timing controller [e.g., Instant Specification Paragraph 78: The timing controller 130 may control each of the switch elements of the switch circuit 300 to switch the data voltage of the pixel data and the black grayscale voltage.; Instant Specification Paragraph 114: The transistors M11 to M14 are turned on in response to the gate-on voltage Von of the switch signals SW1 and SW2; Fig. 12: 81, 82, 83, SW1, SW2; Fig. 13A: M11–M14, SW1, SW2], while the sub-pixels are charged with whichever voltage is on the data line in response to the gate signals [e.g., Instant Specification Paragraph 103: The sub-pixels of the first and second pixel groups are charged with the data voltage Vdata or black grayscale voltage Vblack in response to the pulses of the gate signals SCAN1 to SCAN(n) that are sequentially shifted in units of one pixel line as illustrated in FIG. 7; Fig. 7: SCAN(1)–SCAN(n), D1–D(m)].
The phrase is not read as requiring that the voltage type on a data line be unchanged from one gate line to the next within a sub-frame period: in the embodiment of FIGS. 9 and 10, which applicant cites as support for the phrase, the first pixel group includes the odd-numbered sub-pixels of the odd-numbered pixel lines and the even-numbered sub-pixels of the even-numbered pixel lines [e.g., Instant Specification Paragraph 106: the first pixel group including odd-numbered sub-pixels of odd-numbered pixel lines L1, L3 . . . L7 and even-numbered sub-pixels of even-numbered pixel lines L2, L4 . . . L8 may be turned on during the first sub-frame period SF1 and turned off during the second sub-frame period SF2; Fig. 10: SF1, C1, L1, L2],
the sub-pixels of a column sharing one data line [e.g., Instant Specification Paragraph 63: The sub-pixels arranged in the column direction (Y-axis direction) along a data line direction may share the data line 102.] and
the switch circuit of FIG. 12 applying to that method [e.g., Instant Specification Paragraph 108: FIG. 12 is a diagram showing an example of a switch circuit applicable to the duty driving methods of FIG. 6 and FIG. 9; Fig. 12: DL1–DL6],
so that within the first sub-frame period one data line carries the data voltage for one pixel line and the black grayscale voltage for the next.
(b) Black grayscale voltage is read per the specification’s own description: [e.g., Instant Specification Paragraph 66: The black grayscale voltage is a voltage that is independent of pixel data of an input image.; Instant Specification Paragraph 66: A first transistor of the sub-pixel to which a black grayscale voltage is applied is turned off, turning off the light emitting element.; Instant Specification Paragraph 66: The black grayscale voltage may be set to a voltage equal to, but not limited to, the voltage of the black grayscale or the lowest grayscale of the pixel data.]
(c) Sub-frame period is read as a portion of one frame period [e.g., Instant Specification Paragraph 94: The duty driving method of the present disclosure divides one frame period in time into two or more sub-frame periods.; Instant Specification Paragraph 101: one frame period may be divided in time into a first sub-frame period SF1 and a second sub-frame period SF2].
(d) Arranged next to (claim 5) is read as reciting neighboring pixels in the array; the specification permits interposed components [e.g., Instant Specification Paragraph 50: one or more other components may be interposed between them] and describes the switch parts as connected to sub-pixels of the same colors in adjacent pixels [e.g., Instant Specification Paragraph 113: The switch parts 61, 62 and 63 may be electrically connected to sub-pixels of the same colors in adjacent pixels.].
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the gate signals of the sub-pixels of the second pixel group” in the second data-line element. There is insufficient antecedent basis for this limitation in the claim.
The only gate signals previously recited are “gate signals of sub-pixels of the first pixel group”, and “the sub-pixels of the second pixel group” are first introduced in the fourth element.
It cannot be determined whether the gate signals of the sub-pixels of the second pixel group are the same gate signals as those of the first pixel group or different gate signals.
Claim 1 recites “sub-pixels of the first pixel group” in the first element and again, as a newly introduced element, in the third element (“sub-pixels of the first pixel group connected to the data lines of the first pixel group”).
It cannot be determined whether the sub-pixels recited in the third element are the same sub-pixels as those recited in the first element or additional sub-pixels. See MPEP § 2173.05(o).
The phrases “independent of gate signals of sub-pixels of the first pixel group” and “independent of the gate signals of the sub-pixels of the second pixel group” render claim 1 indefinite, because the claim does not make clear what relationship between the recited voltages and the gate signals is excluded, and the readings open to a skilled reader differ in scope.
The specification does not use the phrase.
It supplies and selects the data voltage and the black grayscale voltage through the switch circuit 300 under the switch signals SW1 and SW2 [e.g., Instant Specification Paragraph 78: The timing controller 130 may control each of the switch elements of the switch circuit 300 to switch the data voltage of the pixel data and the black grayscale voltage.],
charges the sub-pixels with whichever voltage is on the data line in response to the pulses of the gate signals [e.g., Instant Specification Paragraph 103: The sub-pixels of the first and second pixel groups are charged with the data voltage Vdata or black grayscale voltage Vblack in response to the pulses of the gate signals SCAN1 to SCAN(n)], and
in the embodiment of FIGS. 9 and 10 places the data voltage on a data line for one pixel line and the black grayscale voltage on the same line for the next within one sub-frame period [e.g., Instant Specification Paragraph 106: the first pixel group including odd-numbered sub-pixels of odd-numbered pixel lines L1, L3 . . . L7 and even-numbered sub-pixels of even-numbered pixel lines L2, L4 . . . L8 may be turned on during the first sub-frame period SF1 and turned off during the second sub-frame period SF2; Fig. 10: SF1, C1, L1, L2].
Read as reciting that the voltages are supplied to the data lines and selected between by circuitry and signals other than the gate signals, the phrase is met by every embodiment; read as reciting that the type of voltage on a data line is unaffected by which gate signal is pulsed, which is the reading applicant’s Remarks advance (page 10), the phrase excludes the embodiment of FIGS. 9 and 10 that applicant cites as its support.
Which of the two is claimed cannot be determined from the claim. In the second data-line element, the absence of a comma before ‘independent of’ leaves it unclear whether the phrase modifies the receipt of both the black grayscale voltage and the second data voltage or the receipt of the second data voltage during the second sub-frame period only.
For the purpose of applying the prior art, the phrases are interpreted as set out in paragraph 11 above. See MPEP § 2173.06.
Claims 2-6 are rejected as being dependent upon rejected base claim 1 and incorporating its indefiniteness.
Claim Rejections — 35 U.S.C. § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4–6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsui et al. (US 2012/0194576 A1).
Regarding claim 1, Matsui discloses a display panel [e.g., Paragraph 85: The pixels 11A and 11B are arranged in a matrix on the display panel 10.; Fig. 3: 11A, 11B, 151, 152] comprising:
data lines [e.g., Fig. 3: 151] of a first pixel group [e.g., Paragraph 86: The pixels in an odd-numbered driving block are connected to a first signal line and the pixels in an even-numbered driving block are connected to a second signal line which is different from the first signal line.; Paragraph 86: two signal lines (a first signal line 151 and a second signal line 152) are disposed in each pixel column; Fig. 3: 11A; Fig. 9A: Third (odd-numbered) driving block, 151]
connected to receive a first data voltage [e.g., Paragraph 133: In the period from T1 to T2 and the period from T3 to T4, on the other hand, the control line 144 is HIGH and the control line 143 is LOW to allow the second signal line 152 to carry the standard voltage.; Paragraph 133: the signal line driving circuit 15 is constantly outputting a signal voltage; Paragraph 117: The switching transistors 163 and 164 make up a first selector 16A which is disposed for each pixel column and selectively provides a signal voltage outputted from the signal line driving circuit 15 to one of the first signal line 151 and the second signal line 152.; Fig. 8: T1–T2, First signal line 151, Control line 144; Fig. 9A: 164, Signal voltage, 151]
during a first sub-frame period [e.g., Paragraph 133: the period from T1 to T2 corresponds to a threshold voltage detection period in the second driving block; Fig. 8: 1F period, T0–T4] and
a black grayscale voltage [e.g., Paragraph 130: the signal line driving circuit 15 has changed the voltage of the first signal line 151 from a signal voltage to a standard voltage to turn off the driving transistor 114; Paragraph 113: If the standard voltage is 0 V, for example, the standard voltage source and standard voltage line 119 may be omitted and switching transistors 161 and 162 may be connected to the power source line 112, instead of the standard voltage line 119.; Paragraph 139: the organic EL element 113 does not produce luminescence; Fig. 3: 119]
during a second sub-frame period [e.g., Paragraph 133: the control line 144 is at a LOW level and the control line 143 is at a HIGH level in the period from T0 to T1 and the period from T2 to T3 to allow the first signal line 151 carry a standard voltage; Fig. 8: T2–T3, First signal line 151, Control line 143; Fig. 9B: 162, Standard voltage, 151],
independent of gate signals of sub-pixels of the first pixel group [e.g., Paragraph 118: one control signal is outputted from the scanning/control line driving circuit 14 to the control line 141 and the control line 144 at the same time to turn on and off the switching transistors 161 and 164 in synchronization; Paragraph 97: The switching transistor 115 is a third switching transistor having a gate electrode connected to the scanning line 133.; Paragraph 105: The scanning line 133 has the function of providing timing of holding a signal voltage or a standard voltage for detecting the threshold voltage of the driving transistor 114 in the pixels that belong to the pixel rows including the pixels 11A and 11B.; Fig. 3: 141–144, 16, 14; Fig. 8: Scanning line (1, 1)–(4, m), Control line 143, Control line 144];
data lines [e.g., Fig. 3: 152] of a second pixel group [e.g., Paragraph 97: in the pixels 11B in an even-numbered driving block, the other of the source and the drain is connected to the second signal line 152; Fig. 3: 11B; Fig. 9A: Second (even-numbered) driving block, Fourth (even-numbered) driving block, 152]
connected to receive the black grayscale voltage during the first sub-frame period [e.g., Paragraph 133: In the period from T1 to T2 and the period from T3 to T4, on the other hand, the control line 144 is HIGH and the control line 143 is LOW to allow the second signal line 152 to carry the standard voltage.; Fig. 8: T1–T2, Second signal line 152; Fig. 9A: 161, Standard voltage, 152] and
a second data voltage during the second sub-frame period [e.g., Paragraph 91: the control circuit 20 causes the standard voltage to be outputted onto the second signal line while the signal voltage is being outputted onto the first signal line, and causes the standard voltage to be outputted onto the first signal line while the signal voltage is being outputted onto the second signal line; Fig. 8: T2–T3, Second signal line 152; Fig. 9B: 163, Signal voltage, 152]
independent of the gate signals of the sub-pixels of the second pixel group [e.g., Paragraph 118: the scanning/control line driving circuit 14 changes mutually exclusively the voltage level of the control signal provided to the control line 141 and the control line 144 and the voltage level of the control signal provided to the control line 142 and the control line 143 to turn on/off the set of the switching transistors 161 and 164 and turn on/off the set of the switching transistors 162 and 163 mutually exclusively; Fig. 3: 141–144];
sub-pixels of the first pixel group connected to the data lines of the first pixel group; [e.g., Paragraph 97: In the pixels 11A in an odd-numbered driving block, the other of the source and the drain is connected to the first signal line 151; Fig. 3: 11A, 151] and
sub-pixels of the second pixel group connected to the data lines of the second pixel group. [e.g., Paragraph 97: in the pixels 11B in an even-numbered driving block, the other of the source and the drain is connected to the second signal line 152; Fig. 3: 11B, 152] (e.g., see Paragraphs 85–153)
The first pixel group is the pixels 11A of the odd-numbered driving blocks, connected to the first signal line 151 of each pixel column, and the second pixel group is the pixels 11B of the even-numbered driving blocks, connected to the second signal line 152; the first sub-frame period is the period from T1 to T2 and the second sub-frame period is the period from T2 to T3 of FIG. 8, each a portion of the one-frame period (reading (c), paragraph 11 above).
The standard voltage is a black grayscale voltage under reading (b): it is a fixed voltage of the display device, 0 V by way of example, independent of the image data; it is applied to a signal line, after the switching transistors 116 of the block have quenched its organic EL elements, to turn off the driving transistor 114 of the pixels of the driving block being written in that period, whose organic EL elements 113 do not produce luminescence;
claim 1 requires the data lines to receive the voltage, which the signal line does for the whole period [e.g., Paragraph 113: The standard voltage line 119 is connected to a standard voltage source of the display device 1; Paragraph 129: This optically quenches the organic EL elements 113 and simultaneous production of luminescence in the pixels in the k-th driving block ends and a non-luminescence-production period in the k-th driving block starts.].
Under reading (a), the signal voltage and the standard voltage are selected onto each signal line by the selector circuit 16 under the control lines 141–144, which are distinct from the scanning lines 133 that write the pixels, and on each signal line the selected voltage is held for the whole period regardless of which scanning line is HIGH [e.g., Paragraph 133: the voltage level of the scanning line 133 (2, 1) to 133 (2, m) is HIGH in the period T1 to T2; Fig. 8: Scanning line (2, 1), Scanning line (2, m), First signal line 151, Second signal line 152].
Regarding claim 4, Matsui discloses a switch circuit [e.g., Paragraph 109: The selector circuit 16 illustrated in FIG. 3 includes switching transistors 161 to 164, each provided for each pixel column.; Fig. 3: 16, 161–164]
that is connected to a first input node [e.g., Fig. 3: 153] to which the first data voltage and the second data voltage are applied, [e.g., Paragraph 109: The data driver 153 is an integrated circuit (IC) that outputs a signal voltage corresponding to an input signal from the control circuit 20 to a pixel column connected to the data driver 153.; Paragraph 117: The switching transistors 163 and 164 make up a first selector 16A which is disposed for each pixel column and selectively provides a signal voltage outputted from the signal line driving circuit 15 to one of the first signal line 151 and the second signal line 152.]
a second input node [e.g., Fig. 3: 119] to which the black grayscale voltage is input, [e.g., Paragraph 113: The standard voltage line 119 is connected to a standard voltage source of the display device 1; Paragraph 114: The switching transistors 161 and 162 make up a second selector 16B which is disposed for each pixel column and selectively provides a standard voltage provided from the standard voltage source to one of the first signal line 151 and the second signal line 152.]
gate nodes [e.g., Fig. 3: 141, 142, 143, 144] to which switch signals are applied, [e.g., Paragraph 118: one control signal is outputted from the scanning/control line driving circuit 14 to the control line 141 and the control line 144 at the same time to turn on and off the switching transistors 161 and 164 in synchronization; Fig. 9A: 143, 144; Fig. 9B: 143, 144]
the data lines of the first pixel group, [e.g., Paragraph 116: One of a source and a drain of the switching transistor 164 is connected to the first signal line 151 and the other of the source and drain is connected to the data driver 153.; Fig. 3: 151, 11A] and
the data lines of the second pixel group. [e.g., Paragraph 115: One of a source and a drain of the switching transistor 163 is connected to the second signal line 152 and the other of the source and the drain is connected to the data driver 153.; Fig. 3: 152, 11B] (e.g., see Paragraphs 86–119)
Regarding claim 5, Matsui discloses the switch circuit includes: a first switch part [e.g., Paragraph 109: if each pixel is made up of an R (red) subpixel, a B (blue) subpixel, and a G (green) subpixel, the selector circuit 16 includes switching transistors 161 to 164, each provided for each subpixel, and the signal line driving circuit 15 includes data drivers 153, each provided for each subpixel column; Fig. 3: first 161–164 (leftmost column)]
connected to a data line [e.g., Fig. 3: first 151] connected to a sub-pixel of a first color of a first pixel, [e.g., Paragraph 97: In the pixels 11A in an odd-numbered driving block, the other of the source and the drain is connected to the first signal line 151; Fig. 3: 11A (R subpixel column)] and
a data line [e.g., Fig. 3: first 152]
connected to a sub-pixel of the first color of a second pixel arranged next to the first pixel; [e.g., Paragraph 97: in the pixels 11B in an even-numbered driving block, the other of the source and the drain is connected to the second signal line 152; Paragraph 110: FIG. 3 depicts only the pixels 11B (in two rows) in a last block and the pixels 11A (in only one row) in the last but one block.; Fig. 3: 11B (R subpixel column), row adjoining 11A]
a second switch part [e.g., Fig. 3: second 161–164]
connected to a data line [e.g., Fig. 3: second 151] connected to a sub-pixel of a second color of the first pixel, [e.g., Paragraph 109: the selector circuit 16 includes switching transistors 161 to 164, each provided for each subpixel; Fig. 3: 11A (B subpixel column)] and
a data line [e.g., Fig. 3: second 152] connected to a sub-pixel of the second color of the second pixel; and [e.g., Fig. 3: 11B (B subpixel column)]
a third switch part [e.g., Fig. 3: third 161–164]
connected to a data line [e.g., Fig. 3: third 151]
connected to a sub-pixel of a third color of the first pixel, [e.g., Paragraph 109: the signal line driving circuit 15 includes data drivers 153, each provided for each subpixel column; Fig. 3: 11A (G subpixel column)] and
a data line [e.g., Fig. 3: third 152]
connected to a sub-pixel of the third color of the second pixel. [e.g., Fig. 3: 11B (G subpixel column)] (e.g., see Paragraphs 108–121)
Regarding claim 6, Matsui discloses each of the switch parts includes:
a first transistor [e.g., Fig. 3: 164] connected between the first input node and a data line of the first pixel group and turned on in response to a gate-on voltage of a first switch signal; [e.g., Paragraph 116: Each of the switching transistors 164 is a first switch element having a gate connected to a control line 144. One of a source and a drain of the switching transistor 164 is connected to the first signal line 151 and the other of the source and drain is connected to the data driver 153.; Fig. 3: 164, 144, 151, 153; Fig. 9A: 164, 144]
a second transistor [e.g., Fig. 3: 162] connected between the second input node and a data line of the first pixel group and turned on in response to a gate-on voltage of a second switch signal; [e.g., Paragraph 112: Each of the switching transistors 162 is a third switch element having a gate connected to a control line 142. One of a source and a drain of the switching transistor 162 is connected to the first signal line 151 and the other of the source and the drain is connected to the standard voltage line 119.; Paragraph 118: The control line 142 and the control line 143 are connected to each other to form one common control line.; Fig. 3: 162, 142, 151, 119; Fig. 9B: 162, 143]
a third transistor [e.g., Fig. 3: 161] connected between the second input node and a data line of the second pixel group and turned on in response to the gate-on voltage of the first switch signal; and [e.g., Paragraph 111: Each of the switching transistors 161 is a fourth switch element having a gate connected to a control line 141. One of a source and a drain of the switching transistor 161 is connected to the second signal line 152 and the other of the source and drain is connected to a standard voltage line 119.; Paragraph 118: the control line 141 and the control line 144 in this embodiment are connected to each other to form one common control line; Fig. 3: 161, 141, 152, 119; Fig. 9A: 161, 144]
a fourth transistor [e.g., Fig. 3: 163] connected between the first input node and a data line of the second pixel group and turned on in response to the gate-on voltage of the second switch signal. [e.g., Paragraph 115: Each of the switching transistors 163 is a second switch element having a gate connected to a control line 143. One of a source and a drain of the switching transistor 163 is connected to the second signal line 152 and the other of the source and the drain is connected to the data driver 153.; Paragraph 118: the scanning/control line driving circuit 14 changes mutually exclusively the voltage level of the control signal provided to the control line 141 and the control line 144 and the voltage level of the control signal provided to the control line 142 and the control line 143 to turn on/off the set of the switching transistors 161 and 164 and turn on/off the set of the switching transistors 162 and 163 mutually exclusively; Fig. 3: 163, 143, 152, 153; Fig. 9B: 163, 143] (e.g., see Paragraphs 108–121)
The first switch signal is the common control signal on the control lines 141 and 144 and the second switch signal is the common control signal on the control lines 142 and 143, the two being changed mutually exclusively; the first input node is the output of the data driver 153 of the subpixel column and the second input node is the standard voltage line 119. In claim 5, the first pixel is a pixel 11A and the second pixel is the pixel 11B of the adjoining row in the same column (reading (d), paragraph 11 above), the selector being provided for each subpixel so that each switch part connects the two signal lines of one subpixel column.
Claim Rejections — 35 U.S.C. § 102 / § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1–3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2012/0249604 A1);
or, in the alternative, under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2012/0249604 A1) in view of Kawano (US 2012/0147064 A1).
Regarding claim 1, Kim discloses a display panel [e.g., Paragraph 34: the organic light emitting display includes a display unit 20 having a plurality of pixels 10 coupled to scan lines S1 to Sn and data lines D1 to Dm; Fig. 1: 20, 10, D1–Dm, S1–Sn] comprising:
data lines [e.g., Fig. 1: D1, D3, … Dm-1] of a first pixel group [e.g., Paragraph 36: The first display unit includes pixels coupled to odd scan lines (for example, odd-numbered scan lines S1, S3, . . . , Sn-1) and odd data lines (for example, odd-numbered data lines D1, D3, . . . , Dm-1).; Fig. 6A: D1, D3, S1, S3]
connected to receive a first data voltage [e.g., Paragraph 76: when the scan signal is supplied to the odd-numbered scan lines S1, S3, . . . , Sn-1, the corresponding data voltages Vd are supplied to the odd-numbered data lines D1, D3, . . . , Dm-1; Fig. 5: SF1, D1, D3, Vd]
during a first sub-frame period [e.g., Paragraph 75: a scan signal is sequentially supplied to all the scan lines S1 to Sn for the first sub-frame period SF1; Paragraph 48: The scan driver 30 performs a sub-frame period (SF) four times during one frame period in which an image of one frame is displayed.; Fig. 5: 1F, SF1] and
a black grayscale voltage [e.g., Paragraph 52: The data driver 40 may display black by supplying a black voltage Vblack to pixels not included in the display unit that receives the corresponding data voltages supplied for each of the sub-frame periods.; Paragraph 52: The black voltage Vblack may be supplied from the power supply 60 that generates the first power source ELVDD and the second power source ELVSS.; Paragraph 62: When the plurality of pixels 10 included in the display unit 20 receive the black voltage Vblack supplied from the black unit 120, they do not emit light and thus display black.; Fig. 3: 120, 122, Vblack]
during a second sub-frame period [e.g., Paragraph 80: the scan signal is sequentially supplied to all the scan lines S1 to Sn for the third sub-frame period SF3; Paragraph 81: when the scan signal is supplied to the odd-numbered scan lines S1, S3, . . . , Sn-1, the black voltage Vblack or the high-level voltage VGH is supplied to the odd-numbered data lines D1, D3, . . . , Dm-1; Paragraph 81: when the scan signal is supplied to the even-numbered scan lines S2, S4, Sn, the black voltage Vblack or the high-level voltage VGH is applied to all the data lines D1 to Dm; Paragraph 84: the order of the display units that emit light may be changed in other embodiments; Fig. 5: SF3, D1, D3],
independent of gate signals of sub-pixels of the first pixel group [e.g., Paragraph 56: A load signal Load is used to select which of the output buffers 112 (for example, odd output buffers coupled to the odd data lines, even output buffers coupled to the even data lines) transfer the corresponding data voltages to the data lines.; Paragraph 58: A black signal Bs is used to select which of the black buffers 122 (for example, odd black buffers coupled to the odd data lines, even black buffers coupled to the even data lines, or all the black buffers) transfer the black voltage to the corresponding data lines.; Paragraph 63: Each of the output buffers 112 and the black buffers 122 may be tri-state buffers controlled by the load signal Load and the black signal Bs, respectively. The load signal Load and the black signal Bs are included in the data driver control signal DCS.; Paragraph 48: the scan driver 30 generates the scan signal in response to a scan driver control signal SCS supplied from the timing controller 50, and sequentially supplies the generated scan signal to the scan lines S1 to Sn; Paragraph 43: the first transistor M1 becomes a switching transistor and is turned on by the scan signal to transfer the data voltage to a driving transistor; Fig. 3: 110, 112, Load, 120, 122, Bs; Fig. 1: 50, DCS, 30, SCS; Fig. 2: M1, Sn, Dm];
data lines [e.g., Fig. 1: D2, … Dm] of a second pixel group [e.g., Paragraph 37: the third display unit includes pixels coupled to odd-numbered scan lines S1, S3, . . . , Sn-1 and even-numbered data lines D2, D4, . . . , Dm; Fig. 6C: D2, Dm, S1, S3]
connected to receive the black grayscale voltage during the first sub-frame period [e.g., Paragraph 76: a voltage corresponding to a black display (for example, the black voltage Vblack, or the high-level voltage VGH of the scan signal) is applied to the even-numbered data lines D2, D4, . . . , Dm; Paragraph 77: when the scan signal is supplied to the even-numbered scan lines S2, S4, . . . , Sn, the black voltage Vblack or the high-level voltage VGH is applied to all the data lines D1 to Dm; Fig. 5: SF1, D2, Dm] and
a second data voltage during the second sub-frame period [e.g., Paragraph 81: the corresponding data voltages Vd are supplied to the even-numbered data lines D2, D4, . . . , Dm; Fig. 5: SF3, D2, Dm, Vd]
independent of the gate signals of the sub-pixels of the second pixel group [e.g., Paragraph 63: The load signal Load and the black signal Bs are included in the data driver control signal DCS.; Paragraph 58: When the black signal Bs is supplied to the black unit 120, each of the black buffers 122 in the corresponding plurality of black buffers 122 selected by the black signal Bs (for example, odd black buffers, even black buffers, or all black buffers 122) applies the black voltage Vblack to a corresponding data line.; Paragraph 56: When the load signal Load is supplied to the output unit 110, each of the output buffers 112 in the corresponding plurality of output buffers 112 selected by the load signal Load (for example, odd output buffers or even output buffers) applies one of the data voltages to a corresponding data line.; Fig. 3: 110, 120, Load, Bs];
sub-pixels of the first pixel group connected to the data lines of the first pixel group; [e.g., Paragraph 36: The first display unit includes pixels coupled to odd scan lines (for example, odd-numbered scan lines S1, S3, . . . , Sn-1) and odd data lines (for example, odd-numbered data lines D1, D3, . . . , Dm-1).; Paragraph 44: a first electrode of the first transistor M1 is coupled to the data line Dm; Fig. 1: 10; Fig. 2: 10, M1, Dm] and
sub-pixels of the second pixel group connected to the data lines of the second pixel group. [e.g., Paragraph 37: the third display unit includes pixels coupled to odd-numbered scan lines S1, S3, . . . , Sn-1 and even-numbered data lines D2, D4, . . . , Dm; Fig. 6C] (e.g., see Paragraphs 33–84)
The first pixel group is Kim’s first display unit and the second pixel group is Kim’s third display unit, which share the odd-numbered scan lines and differ in their data lines; the first sub-frame period is SF1 and the second sub-frame period is SF3, the order in which the display units emit light being changeable [e.g., Paragraph 84: the order of the display units that emit light may be changed in other embodiments].
The black voltage Vblack is a voltage independent of the pixel data, supplied from the power supply 60 through the black unit 120, and turns the pixel off (reading (b), paragraph 11 above).
Under reading (a), the data voltages and the black voltage are supplied to the data lines through the output buffers 112 and the black buffers 122 and selected between by the load signal Load and the black signal Bs of the data driver control signal DCS from the timing controller 50, and the scan signal serves to turn on the first transistor M1 of a pixel to transfer the voltage on its data line [e.g., Paragraph 44: When the scan signal is supplied from the scan line Sn, the first transistor M1 (that is coupled to the scan line Sn and the data line Dm) is turned on to supply the data voltage supplied from the data line Dm to the storage capacitor Cst.].
Regarding claim 2, Kim discloses during an emission period of the first sub-frame period, the sub-pixels of the first pixel group are turned on, and the sub-pixels of the second pixel group are turned off [e.g., Paragraph 77: only the first display unit among all the display units emits light for the first sub-frame period SF1; Paragraph 48: the four sub-frame periods are performed, so that the four display units sequentially emit light; Paragraph 62: they do not emit light and thus display black; Fig. 6A: D1, D3, S1, S3 (light), D2, Dm (black)]; and
during an emission period of the second sub-frame period, the sub-pixels of the first pixel group are turned off, and the sub-pixels of the second pixel group are turned on. [e.g., Paragraph 81: only the third display unit among all the display units emits light for the third sub-frame period SF3; Fig. 6C: D2, Dm, S1, S3 (light), D1, D3 (black)] (e.g., see Paragraphs 72–84)
Regarding claim 3, Kim discloses during a data addressing period of the first sub-frame period, the first data voltage is applied to the sub-pixels of the first pixel group, and the black grayscale voltage is applied to the sub-pixels of the second pixel group at the same time [e.g., Paragraph 48: In the sub-frame period, the scan signal is sequentially supplied to all the scan lines S1 to Sn.; Paragraph 76: when the scan signal is supplied to the odd-numbered scan lines S1, S3, . . . , Sn-1, the corresponding data voltages Vd are supplied to the odd-numbered data lines D1, D3, . . . , Dm-1; Paragraph 76: a voltage corresponding to a black display (for example, the black voltage Vblack, or the high-level voltage VGH of the scan signal) is applied to the even-numbered data lines D2, D4, . . . , Dm; Paragraph 43: the first transistor M1 becomes a switching transistor and is turned on by the scan signal to transfer the data voltage to a driving transistor; Fig. 5: SF1, S1, D1, D3, D2, Dm]; and
during a data addressing period of the second sub-frame period, the black grayscale voltage is applied to the sub-pixels of the first pixel group, and the second data voltage is applied to the sub-pixels of the second pixel group at the same time. [e.g., Paragraph 81: when the scan signal is supplied to the odd-numbered scan lines S1, S3, . . . , Sn-1, the black voltage Vblack or the high-level voltage VGH is supplied to the odd-numbered data lines D1, D3, . . . , Dm-1; Paragraph 81: the corresponding data voltages Vd are supplied to the even-numbered data lines D2, D4, . . . , Dm; Fig. 5: SF3, S1, D1, D3, D2, Dm] (e.g., see Paragraphs 72–84)
In the alternative (35 U.S.C. § 103 over Kim in view of Kawano).
Should it be shown that Kim discloses the data lines of the first pixel group receiving the first data voltage during the first sub-frame period, and the data lines of the second pixel group receiving the second data voltage during the second sub-frame period, independent of the gate signals of the respective sub-pixels with insufficient specificity,
because within a sub-frame period the data voltages are supplied to the data lines of the emitting display unit while its own scan lines are supplied and the black voltage while the other scan lines are supplied [e.g., Kim, Paragraph 77: when the scan signal is supplied to the even-numbered scan lines S2, S4, . . . , Sn, the black voltage Vblack or the high-level voltage VGH is applied to all the data lines D1 to Dm; Fig. 5: SF1, D1, D3]:
Kawano teaches a display apparatus in which the light emitting elements are driven with a first brightness signal in the first half of a frame period and a black-level signal in the latter half [e.g., Kawano, Paragraph 58: The driving unit 15 transmits a driving signal to an organic EL element of the display unit 12 based on the first brightness signal S1 to cause the organic EL element to emit light in the first half of a certain light-emission period.; Paragraph 59: the conversion unit 14 generates and outputs a second brightness signal S2 corresponding to the lowest bright level, that is, a black level, to the driving unit 15; Paragraph 68: The first period F1 includes a writing period W1 and a light-emission period E1, and the second period F2 includes a writing period W2 and a light-emission period E2.; Paragraph 70: since the second brightness signal S2 is in the lowest brightness level, that is, the black level, the organic EL element L1 does not emit light during the second light-emission period E2; Fig. 7: F1, W1, E1, F2, W2, E2, S1, S2],
in which the data signal is written row by row through the data lines during each writing period [e.g., Kawano, Paragraph 69: The driving unit 15 selects organic EL elements in rows by the control lines P1 during the first writing period W1 of the first period F1, transmits the data signal Vdata corresponding to a brightness signal to the data line, and writes the brightness signal in the driving circuit of an organic EL element provided on the row.; Paragraph 65: The driving circuit 2 receives a data signal Vdata transferred to a data line 7 extending in the column direction; Fig. 6: 7, P1, Tr1; Fig. 7: P1(1)–P1(M), Vdata(n)], and
in which the elements emitting on the high-brightness signal and those emitting on the black-level signal in a given half-frame are arranged alternately in the column direction with opposite phases, so that a whole column is on one signal for the whole half-frame and the adjacent column on the other [e.g., Kawano, Paragraph 85: the organic EL elements which emit light based on the high-brightness signal during a light-emission period and the organic EL elements which emit light based on the low-brightness signal during a light-emission period are provided in a mixed manner; Paragraph 85: the organic EL elements are alternately arranged in the row or column direction; Paragraph 87: the phases of the high-brightness light emission and the low-brightness light emission of the adjacent pixels are opposite to each other].
Kim and Kawano are analogous art because they are from the same field of endeavor, light emitting displays in which the pixels are driven with data voltages and a black level in sub-periods of one frame.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange Kim’s display units by data line rather than by scan line and data line — the pixels of the odd-numbered data lines (the first and fourth display units) forming one group and the pixels of the even-numbered data lines (the second and third display units) the other, the data driver supplying the data voltages to the active group’s data lines for every scan line of its sub-frame period through the output buffers selected by the load signal while the black unit holds the other group’s data lines at the black voltage — so that the pixels of the odd-numbered data lines receive the data voltages during the first sub-frame period for every scan line and the black voltage during the other sub-frame period, and the pixels of the even-numbered data lines the reverse, as Kawano teaches for its column-direction arrangement, because Kawano teaches that mixing the elements on the high-brightness and black-level signals in this way averages the brightness of adjacent elements and reduces the flicker that alternating whole-screen high and low brightness would cause [e.g., Kawano, Paragraph 84: the high-brightness display and the low-brightness display are alternately made in light-emission periods, which may cause image-screen flicker; Paragraph 85: As a result of averaged brightness of the adjacent organic EL elements, the flicker is reduced.];
Kim’s output unit and black unit already select the data lines to which the data voltages and the black voltage are applied by the load signal and the black signal, and hold a data line at the black voltage for a whole sub-frame period [e.g., Kim, Paragraph 58: A black signal Bs is used to select which of the black buffers 122 (for example, odd black buffers coupled to the odd data lines, even black buffers coupled to the even data lines, or all the black buffers) transfer the black voltage to the corresponding data lines.; Fig. 5: SF1, D2, Dm, SF3, D1, D3], so the modification applies a known technique to a similar device with predictable results.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
In this alternative, claims 2 and 3 are met for the reasons given above: the modification changes which pixels form each group, not the emission of one group while the other is off in each sub-frame period, nor the simultaneous application of the data voltages to one group’s data lines and the black voltage to the other’s during each scan.
Claim Rejections — 35 U.S.C. § 103
Claims 4–6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2012/0249604 A1) in view of Matsui et al. (US 2012/0194576 A1);
or, in the alternative, under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2012/0249604 A1) in view of Kawano (US 2012/0147064 A1) as applied to claim 1 above, and further in view of Matsui et al. (US 2012/0194576 A1).
Regarding claim 4, the claim recites: a switch circuit that is connected to a first input node to which the first data voltage and the second data voltage are applied, a second input node to which the black grayscale voltage is input, gate nodes to which switch signals are applied, the data lines of the first pixel group, and the data lines of the second pixel group.
Kim does not expressly disclose a switch circuit connected to a first input node to which the first data voltage and the second data voltage are applied, a second input node to which the black grayscale voltage is input, gate nodes to which switch signals are applied, and the data lines of the first and second pixel groups:
Kim’s data driver has an output buffer 112 and a black buffer 122 for each data line, the data voltages reaching each data line from its own output buffer [e.g., Kim, Paragraph 55: the data processor 100 outputs, in parallel, the data voltages to the data lines D1 to Dm; Paragraph 56: The output unit 110 includes a plurality of output buffers 112 respectively coupled to output terminals of the data processor 100.; Paragraph 58: the black unit 120 includes a plurality of black buffers 122 respectively coupled to output terminals of the plurality of output buffers 112; Fig. 3: 100, 110, 112, 120, 122].
In the alternative of paragraph 18 above, Kawano likewise does not disclose such a switch circuit, its driving unit writing the data signal to each data line [e.g., Kawano, Paragraph 69: transmits the data signal Vdata corresponding to a brightness signal to the data line, and writes the brightness signal in the driving circuit of an organic EL element provided on the row].
Matsui teaches a switch circuit [e.g., Paragraph 109: The selector circuit 16 illustrated in FIG. 3 includes switching transistors 161 to 164, each provided for each pixel column.; Fig. 3: 16, 161–164] that is connected to
a first input node [e.g., Fig. 3: 153]
to which the first data voltage and the second data voltage are applied, [e.g., Paragraph 109: The data driver 153 is an integrated circuit (IC) that outputs a signal voltage corresponding to an input signal from the control circuit 20 to a pixel column connected to the data driver 153.; Paragraph 117: The switching transistors 163 and 164 make up a first selector 16A which is disposed for each pixel column and selectively provides a signal voltage outputted from the signal line driving circuit 15 to one of the first signal line 151 and the second signal line 152.]
a second input node [e.g., Fig. 3: 119]
to which the black grayscale voltage is input, [e.g., Paragraph 113: The standard voltage line 119 is connected to a standard voltage source of the display device 1; Paragraph 114: The switching transistors 161 and 162 make up a second selector 16B which is disposed for each pixel column and selectively provides a standard voltage provided from the standard voltage source to one of the first signal line 151 and the second signal line 152.]
gate nodes [e.g., Fig. 3: 141, 142, 143, 144]
to which switch signals are applied, [e.g., Paragraph 118: one control signal is outputted from the scanning/control line driving circuit 14 to the control line 141 and the control line 144 at the same time to turn on and off the switching transistors 161 and 164 in synchronization; Fig. 9A: 143, 144; Fig. 9B: 143, 144]
the data lines of the first pixel group, [e.g., Paragraph 116: One of a source and a drain of the switching transistor 164 is connected to the first signal line 151 and the other of the source and drain is connected to the data driver 153.; Fig. 3: 151, 11A] and
the data lines of the second pixel group. [e.g., Paragraph 115: One of a source and a drain of the switching transistor 163 is connected to the second signal line 152 and the other of the source and the drain is connected to the data driver 153.; Fig. 3: 152, 11B] (e.g., see Paragraphs 86–119)
Kim and Matsui are analogous art because they are from the same field of endeavor, light emitting displays in which a data voltage and a fixed black-display voltage are supplied to the data lines of different pixels in sub-periods of one frame.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to supply Kim’s data voltages and black voltage to each pair of an odd-numbered and an even-numbered data line through Matsui’s selector circuit — one data driver output as the first input node, the black voltage as the second input node, and the mutually exclusive control signals as the switch signals — because Matsui teaches that providing one output line of the signal line driving circuit for two signal lines through the selector reduces the size of the driving circuit, the number of data drivers and output lines, and the mounting cost, and improves yield [e.g., Matsui, Paragraph 119: Thus, the size of the signal line driving circuit 15 can be reduced and, thanks to the reduction of the numbers of data drivers 153 and output lines, the cost for mounting the driving circuit can be reduced and the manufacturing yield can be improved.], and
Kim already supplies the data voltages to one line of each pair and the black voltage to the other at any one time [e.g., Kim, Paragraph 76: when the scan signal is supplied to the odd-numbered scan lines S1, S3, . . . , Sn-1, the corresponding data voltages Vd are supplied to the odd-numbered data lines D1, D3, . . . , Dm-1; Paragraph 76: a voltage corresponding to a black display (for example, the black voltage Vblack, or the high-level voltage VGH of the scan signal) is applied to the even-numbered data lines D2, D4, . . . , Dm], the mutually exclusive condition that Matsui’s selector implements.
During the scan of the other display units’ scan lines, when both data lines of a pair carry the black voltage, the combination retains Kim’s black unit, whose black signal can select all of the black buffers while the output buffers are in the high-impedance state [e.g., Kim, Paragraph 59: when the black signal Bs that selects all of the black buffers 122 is supplied to the black unit 120, each of the black buffers 122 transfers the black voltage Vblack to the corresponding data line; Paragraph 57: when the load signal Load is not supplied to the output unit 110, each of the output buffers 112 is in the high-impedance state and so does not transfer a data voltage to the corresponding data line], so that Matsui’s selector serves the condition in which one line of each pair carries a data voltage and the other the black voltage.
All the claimed elements were known in the prior art and one skilled in the art could have combined them by known methods with no change in their respective functions, the combination yielding predictable results.
In the alternative branch, the same reason applies to the display panel of Kim as modified by Kawano, whose column sets are likewise on the data voltage and the black voltage mutually exclusively in each sub-frame period.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Regarding claim 5, Matsui teaches the switch circuit includes:
a first switch part [e.g., Paragraph 109: if each pixel is made up of an R (red) subpixel, a B (blue) subpixel, and a G (green) subpixel, the selector circuit 16 includes switching transistors 161 to 164, each provided for each subpixel, and the signal line driving circuit 15 includes data drivers 153, each provided for each subpixel column; Fig. 3: first 161–164 (leftmost column)]
connected to a data line [e.g., Fig. 3: first 151]
connected to a sub-pixel of a first color of a first pixel, [e.g., Paragraph 97: In the pixels 11A in an odd-numbered driving block, the other of the source and the drain is connected to the first signal line 151; Fig. 3: 11A (R subpixel column)] and
a data line [e.g., Fig. 3: first 152]
connected to a sub-pixel of the first color of a second pixel arranged next to the first pixel; [e.g., Paragraph 97: in the pixels 11B in an even-numbered driving block, the other of the source and the drain is connected to the second signal line 152; Paragraph 110: FIG. 3 depicts only the pixels 11B (in two rows) in a last block and the pixels 11A (in only one row) in the last but one block.; Fig. 3: 11B (R subpixel column), row adjoining 11A]
a second switch part [e.g., Fig. 3: second 161–164]
connected to a data line [e.g., Fig. 3: second 151]
connected to a sub-pixel of a second color of the first pixel, [e.g., Paragraph 109: the selector circuit 16 includes switching transistors 161 to 164, each provided for each subpixel; Fig. 3: 11A (B subpixel column)] and
a data line [e.g., Fig. 3: second 152]
connected to a sub-pixel of the second color of the second pixel; and [e.g., Fig. 3: 11B (B subpixel column)]
a third switch part [e.g., Fig. 3: third 161–164]
connected to a data line [e.g., Fig. 3: third 151]
connected to a sub-pixel of a third color of the first pixel, [e.g., Paragraph 109: the signal line driving circuit 15 includes data drivers 153, each provided for each subpixel column; Fig. 3: 11A (G subpixel column)] and
a data line [e.g., Fig. 3: third 152]
connected to a sub-pixel of the third color of the second pixel. [e.g., Fig. 3: 11B (G subpixel column)] (e.g., see Paragraphs 108–121)
Regarding claim 6, Matsui teaches each of the switch parts includes:
a first transistor [e.g., Fig. 3: 164]
connected between the first input node and a data line of the first pixel group and turned on in response to a gate-on voltage of a first switch signal; [e.g., Paragraph 116: Each of the switching transistors 164 is a first switch element having a gate connected to a control line 144. One of a source and a drain of the switching transistor 164 is connected to the first signal line 151 and the other of the source and drain is connected to the data driver 153.; Fig. 3: 164, 144, 151, 153; Fig. 9A: 164, 144]
a second transistor [e.g., Fig. 3: 162]
connected between the second input node and a data line of the first pixel group and turned on in response to a gate-on voltage of a second switch signal; [e.g., Paragraph 112: Each of the switching transistors 162 is a third switch element having a gate connected to a control line 142. One of a source and a drain of the switching transistor 162 is connected to the first signal line 151 and the other of the source and the drain is connected to the standard voltage line 119.; Paragraph 118: The control line 142 and the control line 143 are connected to each other to form one common control line.; Fig. 3: 162, 142, 151, 119; Fig. 9B: 162, 143]
a third transistor [e.g., Fig. 3: 161]
connected between the second input node and a data line of the second pixel group and turned on in response to the gate-on voltage of the first switch signal; and [e.g., Paragraph 111: Each of the switching transistors 161 is a fourth switch element having a gate connected to a control line 141. One of a source and a drain of the switching transistor 161 is connected to the second signal line 152 and the other of the source and drain is connected to a standard voltage line 119.; Paragraph 118: the control line 141 and the control line 144 in this embodiment are connected to each other to form one common control line; Fig. 3: 161, 141, 152, 119; Fig. 9A: 161, 144]
a fourth transistor [e.g., Fig. 3: 163]
connected between the first input node and a data line of the second pixel group and turned on in response to the gate-on voltage of the second switch signal. [e.g., Paragraph 115: Each of the switching transistors 163 is a second switch element having a gate connected to a control line 143. One of a source and a drain of the switching transistor 163 is connected to the second signal line 152 and the other of the source and the drain is connected to the data driver 153.; Paragraph 118: the scanning/control line driving circuit 14 changes mutually exclusively the voltage level of the control signal provided to the control line 141 and the control line 144 and the voltage level of the control signal provided to the control line 142 and the control line 143 to turn on/off the set of the switching transistors 161 and 164 and turn on/off the set of the switching transistors 162 and 163 mutually exclusively; Fig. 3: 163, 143, 152, 153; Fig. 9B: 163, 143] (e.g., see Paragraphs 108–121)
Claims 5 and 6 are met by Matsui’s selector circuit as set forth above in the combination stated for claim 4, in either branch:
each pixel of Kim is made up of the R, B and G subpixels that Matsui provides, each subpixel column with its own pair of data lines and its own selector [e.g., Matsui, Paragraph 109: if each pixel is made up of an R (red) subpixel, a B (blue) subpixel, and a G (green) subpixel, the selector circuit 16 includes switching transistors 161 to 164, each provided for each subpixel, and the signal line driving circuit 15 includes data drivers 153, each provided for each subpixel column],
so that the three switch parts connect the same-color data lines of a pixel on the odd-numbered data lines of Kim and of the neighboring pixel on the adjacent even-numbered data lines [e.g., Kim, Paragraph 34: a display unit 20 having a plurality of pixels 10 coupled to scan lines S1 to Sn and data lines D1 to Dm; Fig. 1: 10, D1, D2],
the odd-numbered lines remaining the first group and the even-numbered lines the second, the selector being provided for each subpixel column and the first and second switch signals being the common control signals on the control lines 141/144 and 142/143.
Claims 1–5 are rejected under 35 U.S.C. 103 as being unpatentable over Kawano (US 2012/0147064 A1) in view of Zhang et al. (US 2022/0208874 A1).
Regarding claim 1, Kawano discloses a display panel [e.g., Paragraph 65: The driving circuit 2 is provided for each of the organic EL elements EL, and a current is supplied from a power supply VCC to the organic EL element EL via a driving transistor Tr2 and a light-emission period control switch Tr3.; Fig. 6: 2, EL, 7, P1, P2] comprising:
data lines [e.g., Paragraph 65: The driving circuit 2 receives a data signal Vdata transferred to a data line 7 extending in the column direction; Fig. 6: 7]
of a first pixel group [e.g., Paragraph 85: the organic EL elements are alternately arranged in the row or column direction; Paragraph 85: the organic EL elements which emit light based on the high-brightness signal during a light-emission period and the organic EL elements which emit light based on the low-brightness signal during a light-emission period are provided in a mixed manner]
connected to receive a first data voltage [e.g., Paragraph 70: The data signal Vdata corresponding to the first brightness signal S1 is written into the organic EL element L1.; Paragraph 69: transmits the data signal Vdata corresponding to a brightness signal to the data line, and writes the brightness signal in the driving circuit of an organic EL element provided on the row; Fig. 7: Vdata(n), W1]
during a first sub-frame period [e.g., Paragraph 68: The first period F1 includes a writing period W1 and a light-emission period E1, and the second period F2 includes a writing period W2 and a light-emission period E2.; Paragraph 84: the first period which is the first half of a single frame period or the second period which is the latter half of the single frame period; Fig. 7: F1, F2] and
a black grayscale voltage [e.g., Paragraph 59: the conversion unit 14 generates and outputs a second brightness signal S2 corresponding to the lowest bright level, that is, a black level, to the driving unit 15; Paragraph 70: since the second brightness signal S2 is in the lowest brightness level, that is, the black level, the organic EL element L1 does not emit light during the second light-emission period E2]
during a second sub-frame period [e.g., Paragraph 59: the driving unit 15 causes the organic EL element to stop emitting light in the latter half of the light-emission period; Fig. 7: F2, W2, E2, I1, S2],
independent of gate signals of sub-pixels of the first pixel group [e.g., Paragraph 62: The conversion unit 14 generates the brightness signal S1 and the brightness signal S2 or the brightness signal S3 based on the gray-scale signal Vin.; Paragraph 62: Information about the other brightness signal S2 is temporarily stored in a memory 16, read in the latter-half period of the single frame, and transmitted to the driving unit 15.; Paragraph 66: a data voltage Vdata of the data line 7 is held as the voltage across the holding capacitor; Fig. 6: P1, Tr1, 7];
data lines of a second pixel group connected to receive the black grayscale voltage during the first sub-frame period and a second data voltage during the second sub-frame period [e.g., Paragraph 87: the phases of the high-brightness light emission and the low-brightness light emission of the adjacent pixels are opposite to each other; Paragraph 85: the organic EL elements are alternately arranged in the row or column direction]
independent of the gate signals of the sub-pixels of the second pixel group [e.g., Paragraph 69: The driving unit 15 selects organic EL elements in rows by the control lines P1 during the first writing period W1 of the first period F1, transmits the data signal Vdata corresponding to a brightness signal to the data line, and writes the brightness signal in the driving circuit of an organic EL element provided on the row.; Fig. 7: P1(1)–P1(M), Vdata(n)];
sub-pixels of the first pixel group connected to the data lines of the first pixel group; and [e.g., Paragraph 65: The driving circuits 2 are controlled in rows with two control lines 5(P1) and 6(P2) extending in the row direction.; Fig. 6: 2, 7]
sub-pixels of the second pixel group connected to the data lines of the second pixel group. [e.g., Fig. 6: 2, 7; Fig. 11A: 33, 34, 35] (e.g., see Paragraphs 50–88)
In Kawano’s column-direction arrangement, applied to the first embodiment’s operation for the elements whose input gray scale is not greater than the gray scale Dx (elements of higher gray scale emit on the third brightness signal S3 in both halves [e.g., Kawano, Paragraph 71: the organic EL element L2 emits light with the brightness corresponding to the third brightness signal S3 in both the first and second light-emission periods E1 and E2]), the elements of the odd-numbered columns emit on the first brightness signal in the first period F1 and are held at the black level in the second period F2, and the elements of the even-numbered columns take the opposite phase; the data line of each column carries the data signal corresponding to S1 for every row in one writing period and the black-level signal for every row in the other.
The first pixel group is the elements of the odd-numbered columns and their data lines, the second pixel group the elements of the even-numbered columns and their data lines; the first sub-frame period is F1 and the second is F2 (reading (c), paragraph 11 above).
Under reading (a), the selection between the first brightness signal and the black-level signal for each element is made by the conversion unit 14 and the memory 16 of the signal processing unit, and the control lines P1 write whatever data voltage is on the data line into the driving circuit of the selected row.
To the extent the black grayscale voltage of reading (b) (paragraph 11 above) is required to be a fixed voltage independent of the image data rather than a black-level data signal generated from the input gray-scale signal, Kawano does not expressly disclose it:
Kawano’s black-level signal S2 is generated by the conversion unit 14 from the input gray-scale signal, for the elements whose gray scale is not greater than the threshold [e.g., Kawano, Paragraph 58: When the input gray-scale signal is not greater than the gray scale Dx, that is, a brightness indicated by the gray-scale signal is lower than the first threshold brightness Ith1, the comparison unit 13 outputs the signal (1) as the comparison result.; Paragraph 61: When the brightness S0 indicated by the input image signal Vin is higher than the first threshold brightness Ith1, the conversion unit 14 generates a third brightness signal S3 equivalent to the brightness S0 of the input image signal Vin.], and reaches the data line as a data signal from the driving unit 15.
Kawano’s black level S2, the lowest brightness level for every such element, meets the term under the broad reading; the express teaching of Zhang is relied on in preference.
Zhang teaches a display panel in which the pixel units of the odd-numbered and even-numbered columns are driven in alternation,
one set lit and the other held in a black state [e.g., Zhang, Paragraph 104: the pixel units PU in an odd column may be lit, while the pixel units PU in an even column may always be in the black state; Fig. 15: PU, P1, P2, P3, 31, 32, 33],
the black state being written from a fixed voltage terminal DH that outputs a black state voltage, separate from the driving chip that supplies the data signals, through black state control units 80 of transistors T10–T12 connected to the data lines of each column [e.g., Zhang, Paragraph 115: First electrodes of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 may be electrically connected to a fixed voltage terminal DH.; Paragraph 115: A second electrode of the tenth transistor T10 may be electrically connected to the first data line 31, a second electrode of the eleventh transistor T11 may be electrically connected to the second data line 32, and a second electrode of the twelfth transistor T12 may be electrically connected to the third data line 33.; Paragraph 116: the fixed voltage terminal DH may output a black state voltage, and after the black state voltage is written into the sub pixel, the sub pixel may be in a black state; Paragraph 116: The fixed voltage terminal DH may not need to be integrated on the driving chip.; Fig. 15: 80, T10, T11, T12, DH, 31, 32, 33],
the black state control units of the odd-numbered and even-numbered columns being switched by control signals CKH8 and CKH9 from the control unit rather than by the scan signal, so that the black state voltage is held on the data lines of one column set through the entire scan [e.g., Zhang, Paragraph 115: Gates of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 corresponding to the pixel units PU in an odd column may be electrically connected to an eighth control signal terminal 68.; Paragraph 117: the control signal CKH9 may be at a low level, such that the transistors T10-T12 corresponding to the pixel units PU in an even column may be in a turned-on state; Paragraph 117: The black state voltage outputted by the fixed voltage terminal DH may be written into the pixel units PU in an even column, and the pixel units PU in the even column may be in the black state.; Paragraph 76: The scan line 50 may be configured to transmit a scan signal SCAN to each sub-pixel P.; Fig. 15: 68, 69, 50; Fig. 16: First display mode, CKH8, CKH9, SCAN].
Kawano and Zhang are analogous art because they are from the same field of endeavor, display panels in which the pixels of alternate columns are driven with data signals and a black level through the data lines.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to supply the black level of Kawano’s non-emitting column set in each half-frame from a fixed black state voltage terminal through per-column black state switches held on for the whole period, as Zhang teaches, in place of writing the black-level data signal S2 from the driving unit,
because Zhang teaches that a black state voltage written from a fixed terminal keeps the pixel units that should be black stably in the black state and relieves the driving chip of supplying data signals to them, reducing the number of data signals output and the power consumption of the driving chip [e.g., Zhang, Paragraph 101: the pixel units that should be in the black state may be stably in the black state to prevent the occurrence of lighting; Paragraph 101: the driving chip may no longer need to provide a data signal to the pixel units PU in the black state, thereby reducing the quantity of data signals outputted by the driving chip and reducing the power consumption of the driving chip];
the substitution of one known way of putting a column of pixels in the black state for another yields the predictable result of the same non-emitting half-frame.
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); Graham v. John Deere Co., 383 U.S. 1 (1966).
Regarding claim 2, Kawano discloses during an emission period of the first sub-frame period, the sub-pixels of the first pixel group are turned on, and the sub-pixels of the second pixel group are turned off [e.g., Paragraph 70: The organic EL element L1 emits light with the corresponding brightness during the light-emission period E1.; Paragraph 87: Light is emitted pixel by pixel based on the first brightness signal S1 (high-brightness signal) and the second brightness signal S2 (low-brightness signal) alternately, and the phases of the high-brightness light emission and the low-brightness light emission of the adjacent pixels are opposite to each other.; Fig. 7: E1, I1, S1; Fig. 11A]; and
during an emission period of the second sub-frame period, the sub-pixels of the first pixel group are turned off, and the sub-pixels of the second pixel group are turned on. [e.g., Paragraph 70: since the second brightness signal S2 is in the lowest brightness level, that is, the black level, the organic EL element L1 does not emit light during the second light-emission period E2; Fig. 7: E2, I1, S2; Fig. 11B] (e.g., see Paragraphs 58–88)
Claim 2 is met for the elements driven on the first and second brightness signals, that is, the elements whose input gray scale is not greater than the gray scale Dx [e.g., Kawano, Paragraph 58: When the input gray-scale signal is not greater than the gray scale Dx, that is, a brightness indicated by the gray-scale signal is lower than the first threshold brightness Ith1, the comparison unit 13 outputs the signal (1) as the comparison result.];
in the combination with Zhang the non-emitting column set of each half-frame is held in the black state from the fixed voltage terminal for every pixel unit of the set [e.g., Zhang, Paragraph 104: the pixel units PU in an even column may always be in the black state].
Regarding claim 3, Kawano discloses during a data addressing period of the first sub-frame period, the first data voltage is applied to the sub-pixels of the first pixel group, and the black grayscale voltage is applied to the sub-pixels of the second pixel group at the same time [e.g., Paragraph 69: The driving unit 15 selects organic EL elements in rows by the control lines P1 during the first writing period W1 of the first period F1, transmits the data signal Vdata corresponding to a brightness signal to the data line, and writes the brightness signal in the driving circuit of an organic EL element provided on the row.; Paragraph 87: the phases of the high-brightness light emission and the low-brightness light emission of the adjacent pixels are opposite to each other; Fig. 7: W1, P1(1)–P1(M)]; and
during a data addressing period of the second sub-frame period, the black grayscale voltage is applied to the sub-pixels of the first pixel group, and the second data voltage is applied to the sub-pixels of the second pixel group at the same time. [e.g., Paragraph 69: After the data signal is written into each row, the organic EL elements are caused to emit light during the light-emission period E1. The same operations are repeated during the second period F2.; Paragraph 70: the data signal Vdata corresponding to the second brightness signal S2 is written into the organic EL element L1 during the second writing period W2; Fig. 7: W2] (e.g., see Paragraphs 58–88)
Each row is written in one writing period with the odd-numbered columns receiving the data signal of one phase and the even-numbered columns the other, so that the first data voltage is applied to the first group’s sub-pixels of the row and the black grayscale voltage to the second group’s at the same time; in the combination with Zhang, the black state voltage is on the second group’s data lines throughout the scan and is written into each row’s sub-pixels as the scan signal reaches that row [e.g., Zhang, Paragraph 117: The black state voltage outputted by the fixed voltage terminal DH may be written into the pixel units PU in an even column, and the pixel units PU in the even column may be in the black state.; Fig. 16: First display mode, SCAN, CKH9].
Regarding claim 4, the claim recites: a switch circuit that is connected to a first input node to which the first data voltage and the second data voltage are applied, a second input node to which the black grayscale voltage is input, gate nodes to which switch signals are applied, the data lines of the first pixel group, and the data lines of the second pixel group.
Kawano does not expressly disclose a switch circuit connected to a first input node to which the first data voltage and the second data voltage are applied, a second input node to which the black grayscale voltage is input, gate nodes to which switch signals are applied, and the data lines of the first and second pixel groups:
Kawano’s driving unit writes the data signal, including the black-level signal, to each data line [e.g., Kawano, Paragraph 69: transmits the data signal Vdata corresponding to a brightness signal to the data line, and writes the brightness signal in the driving circuit of an organic EL element provided on the row].
Zhang teaches a switch circuit [e.g., Zhang, Paragraph 61: the display panel 100 may include a plurality of multi-channel multiplexers 20, a plurality of data lines 30 and a plurality of data signal terminals 40; Fig. 15: 20, T1–T6, 80, T10–T12]
that is connected to a first input node [e.g., Zhang, Fig. 15: 40]
to which the first data voltage and the second data voltage are applied [e.g., Zhang, Paragraph 72: First electrodes of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be electrically connected to the data signal terminal 40.],
a second input node [e.g., Zhang, Fig. 15: DH]
to which the black grayscale voltage is input [e.g., Zhang, Paragraph 115: First electrodes of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 may be electrically connected to a fixed voltage terminal DH.; Paragraph 116: the fixed voltage terminal DH may output a black state voltage, and after the black state voltage is written into the sub pixel, the sub pixel may be in a black state],
gate nodes [e.g., Zhang, Fig. 15: 61–66, 68, 69]
to which switch signals are applied [e.g., Zhang, Paragraph 72: A gate of the first transistor T1 may be electrically connected to a first control signal terminal 61; Paragraph 74: the control signal terminals 61-66 may be integrated on the control unit 10, and the control signal terminals 61-66 may output voltage signals; Paragraph 76: The control signals outputted by the control signal terminals 61-66 may be CKH1, CKH2, CKH3, CKH4, CKH5, CKH6, respectively.; Paragraph 115: corresponding to the pixel units PU in an even column may be electrically connected to a ninth control signal terminal 69; Fig. 16: CKH1–CKH6, CKH8, CKH9],
the data lines of the first pixel group [e.g., Zhang, Paragraph 73: A second electrode of the first transistor T1 may be electrically connected to the first data line 31 corresponding to the pixel units PU; Fig. 15: 31, 32, 33 (odd columns)], and
the data lines of the second pixel group [e.g., Zhang, Paragraph 73: A second electrode of the fourth transistor T4 may be electrically connected to the first data line 31 corresponding to the pixel units PU; Paragraph 115: A second electrode of the tenth transistor T10 may be electrically connected to the first data line 31, a second electrode of the eleventh transistor T11 may be electrically connected to the second data line 32, and a second electrode of the twelfth transistor T12 may be electrically connected to the third data line 33.; Fig. 15: 31, 32, 33 (even columns)].
The reason to combine Kawano and Zhang is stated for claim 1 above; in addition, Zhang wires the data lines of the two columns to one data signal terminal through the multiplexer [e.g., Zhang, Paragraph 72: First electrodes of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be electrically connected to the data signal terminal 40.] and
the resulting switch circuit places Kawano’s first and second data voltages on the odd-numbered and even-numbered columns’ data lines from one input node and the black state voltage on the other set from the fixed voltage terminal under the control unit’s switch signals.
KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Regarding claim 5, Zhang teaches the switch circuit includes:
a first switch part [e.g., Fig. 15: T1, T4, T10 (odd column), T10 (even column)]
connected to a data line [e.g., Fig. 15: 31 (odd column)]
connected to a sub-pixel of a first color of a first pixel, [e.g., Paragraph 62: in the pixel units PU in a same column, sub-pixels of the same color may be electrically connected to a same data line 30, and sub-pixels of different colors may be electrically connected to different data lines 30; Paragraph 53: each pixel unit PU may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3; Fig. 15: PU, P1, 31] and
a data line [e.g., Fig. 15: 31 (even column)]
connected to a sub-pixel of the first color of a second pixel arranged next to the first pixel; [e.g., Paragraph 73: A second electrode of the fourth transistor T4 may be electrically connected to the first data line 31 corresponding to the pixel units PU; Fig. 15: T4, 31, PU (adjacent column)]
a second switch part [e.g., Fig. 15: T2, T5, T11 (odd column), T11 (even column)]
connected to a data line [e.g., Fig. 15: 32 (odd column)]
connected to a sub-pixel of a second color of the first pixel, [e.g., Fig. 15: P2] and
a data line [e.g., Fig. 15: 32 (even column)]
connected to a sub-pixel of the second color of the second pixel; and [e.g., Paragraph 115: a second electrode of the eleventh transistor T11 may be electrically connected to the second data line 32]
a third switch part [e.g., Fig. 15: T3, T6, T12 (odd column), T12 (even column)] connected to a data line [e.g., Fig. 15: 33 (odd column)]
connected to a sub-pixel of a third color of the first pixel, [e.g., Fig. 15: P3] and
a data line [e.g., Fig. 15: 33 (even column)]
connected to a sub-pixel of the third color of the second pixel. [e.g., Paragraph 115: a second electrode of the twelfth transistor T12 may be electrically connected to the third data line 33] (e.g., see Paragraphs 53–76, 114–117)
In Zhang’s switch circuit the transistors T1 and T4, with the two tenth transistors T10, connect the data signal terminal and the fixed voltage terminal to the first data lines 31 of the pixel units of the j-th and (j+1)-th columns, which are neighboring pixel units (reading (d), paragraph 11 above); T2 and T5 with the eleventh transistors serve the second data lines 32, and T3 and T6 with the twelfth transistors the third data lines 33.
Claim 5 is met in the combination for the reasons given for claims 1 and 4.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kawano (US 2012/0147064 A1) in view of Zhang et al. (US 2022/0208874 A1) as applied to claim 5 above, and further in view of Matsui et al. (US 2012/0194576 A1).
Regarding claim 6, the claim recites: each of the switch parts includes: a first transistor connected between the first input node and a data line of the first pixel group and turned on in response to a gate-on voltage of a first switch signal; a second transistor connected between the second input node and a data line of the first pixel group and turned on in response to a gate-on voltage of a second switch signal; a third transistor connected between the second input node and a data line of the second pixel group and turned on in response to the gate-on voltage of the first switch signal; and a fourth transistor connected between the first input node and a data line of the second pixel group and turned on in response to the gate-on voltage of the second switch signal.
Kawano does not expressly disclose the switch circuit, as stated for claim 4 (paragraph 20).
Zhang, as applied to claim 5, teaches four transistors per color connecting the data signal terminal and the fixed voltage terminal to the data lines of the two columns, but does not expressly disclose that they are turned on by a first switch signal and a second switch signal each turning on two of the four:
Zhang’s transistors are controlled by separate control signals [e.g., Zhang, Paragraph 76: The control signals outputted by the control signal terminals 61-66 may be CKH1, CKH2, CKH3, CKH4, CKH5, CKH6, respectively.; Paragraph 117: The control signal outputted by the eighth control signal terminal 68 may be CKH8, and the control signal outputted by the ninth control signal terminal 69 may be CKH9.; Fig. 16: CKH1, CKH4, CKH8, CKH9].
Matsui teaches a switch part of four transistors under two common control signals:
a first transistor [e.g., Fig. 3: 164]
connected between the first input node and a data line of the first pixel group and turned on in response to a gate-on voltage of a first switch signal; [e.g., Paragraph 116: Each of the switching transistors 164 is a first switch element having a gate connected to a control line 144. One of a source and a drain of the switching transistor 164 is connected to the first signal line 151 and the other of the source and drain is connected to the data driver 153.; Fig. 3: 164, 144, 151, 153; Fig. 9A: 164, 144]
a second transistor [e.g., Fig. 3: 162]
connected between the second input node and a data line of the first pixel group and turned on in response to a gate-on voltage of a second switch signal; [e.g., Paragraph 112: Each of the switching transistors 162 is a third switch element having a gate connected to a control line 142. One of a source and a drain of the switching transistor 162 is connected to the first signal line 151 and the other of the source and the drain is connected to the standard voltage line 119.; Paragraph 118: The control line 142 and the control line 143 are connected to each other to form one common control line.; Fig. 3: 162, 142, 151, 119; Fig. 9B: 162, 143]
a third transistor [e.g., Fig. 3: 161]
connected between the second input node and a data line of the second pixel group and turned on in response to the gate-on voltage of the first switch signal; and [e.g., Paragraph 111: Each of the switching transistors 161 is a fourth switch element having a gate connected to a control line 141. One of a source and a drain of the switching transistor 161 is connected to the second signal line 152 and the other of the source and drain is connected to a standard voltage line 119.; Paragraph 118: the control line 141 and the control line 144 in this embodiment are connected to each other to form one common control line; Fig. 3: 161, 141, 152, 119; Fig. 9A: 161, 144]
a fourth transistor [e.g., Fig. 3: 163]
connected between the first input node and a data line of the second pixel group and turned on in response to the gate-on voltage of the second switch signal. [e.g., Paragraph 115: Each of the switching transistors 163 is a second switch element having a gate connected to a control line 143. One of a source and a drain of the switching transistor 163 is connected to the second signal line 152 and the other of the source and the drain is connected to the data driver 153.; Paragraph 118: the scanning/control line driving circuit 14 changes mutually exclusively the voltage level of the control signal provided to the control line 141 and the control line 144 and the voltage level of the control signal provided to the control line 142 and the control line 143 to turn on/off the set of the switching transistors 161 and 164 and turn on/off the set of the switching transistors 162 and 163 mutually exclusively; Fig. 3: 163, 143, 152, 153; Fig. 9B: 163, 143] (e.g., see Paragraphs 108–121)
Matsui is analogous art because it is from the same field of endeavor, display panels in which one data driver output is switched between two signal lines and a fixed voltage is switched onto the line not being written.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to control the four transistors of each of Zhang’s switch parts, as applied to claim 5, with two common, mutually exclusive switch signals in Matsui’s cross-coupled arrangement — one signal turning on the transistor from the data input node to the first group’s line and the transistor from the black-voltage input node to the second group’s line, the other signal the complementary pair —
because Matsui teaches that the control unit then need not output control signals individually to the four switch elements and the output load of the control lines is reduced [e.g., Matsui, Paragraph 67: the control unit does not need to output control signals individually to the four switch elements but only needs to output a common control signal to the first switch element and the fourth switch element and a common control signal to the second switch element and the third switch element; Paragraph 119: only one output line of the signal line driving circuit 15 is provided for the two signal lines disposed for each pixel column because the selector circuit 16 is disposed between the signal line driving circuit 15 and the signal line group 12],
while the pairing provides the signal voltage and the fixed voltage to the two lines mutually exclusively, which is exactly the alternation of Kawano’s column sets; in the combination each color’s switch part is controlled by its own pair of common switch signals,
Matsui providing a selector for each subpixel column [e.g., Matsui, Paragraph 109: the selector circuit 16 includes switching transistors 161 to 164, each provided for each subpixel], and the fixed voltage terminal DH of Zhang remains the black-voltage input.
With the pairing, each color’s black switch conducts while that color’s data switch is off, so that the black state voltage is placed on the second group’s line of each color in turn as the colors are loaded from the data signal terminal, each data line retaining the voltage written to it until the row is scanned [e.g., Zhang, Paragraph 66: Because the data line 30 temporarily stores the data signal corresponding to the pixel units PU]; the continuous conduction of Zhang’s black state control units in the first display mode is replaced by that paired switching, which is the modification Matsui’s reason supports.
KSR, 550 U.S. 398; Graham, 383 U.S. 1.
Response to Arguments
Applicant’s arguments filed 28 September 2026 have been fully considered but they are not persuasive.
Applicant argues (Remarks, page 10) that “FIGS. 7, 10, 12, 13A, 13B of the Application and the related descriptions show that the signals in the data lines are not affected by the scan signals” and that “in Kim, the signal provided to the data lines depend on the scan signals”, citing paragraphs [0075]–[0083] of Kim. The argument is not persuasive.
As interpreted in paragraph 11 above, the added limitations require that the voltages the data lines of a pixel group receive be supplied to those lines, and selected between, other than by the gate signals of that group’s sub-pixels.
In Kim, the data voltages reach the data lines through the output buffers 112 selected by the load signal Load and the black voltage through the black buffers 122 selected by the black signal Bs, both of which are included in the data driver control signal DCS from the timing controller 50, and the black voltage is supplied from the power supply 60 [e.g., Kim, Paragraph 63: The load signal Load and the black signal Bs are included in the data driver control signal DCS.; Paragraph 52: The black voltage Vblack may be supplied from the power supply 60 that generates the first power source ELVDD and the second power source ELVSS.; Fig. 3: Load, Bs, 110, 120, Vblack];
the scan signal turns on the first transistor M1 of a pixel to transfer whatever voltage is on its data line [e.g., Kim, Paragraph 43: the first transistor M1 becomes a switching transistor and is turned on by the scan signal to transfer the data voltage to a driving transistor].
The passages applicant cites describe the timing of the data voltages relative to the scan signal within a sub-frame period [e.g., Kim, Paragraph 75: the data voltages Vd are only applied to the odd-numbered data lines in synchronization with the scan signal being supplied to the odd-numbered scan lines]; they do not describe the voltages on the data lines as being supplied or selected by the scan signals.
Applicant’s own disclosure has the same timing relationship: the sub-pixels are charged with the data voltage or the black grayscale voltage in response to the pulses of the gate signals, with the data lines D1 to D(m) refreshed at every pulse [e.g., Instant Specification Paragraph 103: The sub-pixels of the first and second pixel groups are charged with the data voltage Vdata or black grayscale voltage Vblack in response to the pulses of the gate signals SCAN1 to SCAN(n) that are sequentially shifted in units of one pixel line as illustrated in FIG. 7; Fig. 7: SCAN(1)–SCAN(n), D1–D(m), vdata or vblack], and
in the embodiment of FIGS. 9 and 10, which applicant identifies as support for the added limitations, one data line carries the data voltage for one pixel line and the black grayscale voltage for the next within the first sub-frame period [e.g., Instant Specification Paragraph 106: the first pixel group including odd-numbered sub-pixels of odd-numbered pixel lines L1, L3 . . . L7 and even-numbered sub-pixels of even-numbered pixel lines L2, L4 . . . L8 may be turned on during the first sub-frame period SF1 and turned off during the second sub-frame period SF2; Fig. 10: SF1, C1, L1 (turned-on), L2 (turned-off)] — the same alternation of a data line’s voltage with the pixel line being written that applicant attributes to Kim.
A limitation that applicant’s cited support satisfies cannot be read to exclude Kim for that alternation.
Claims 1–3 therefore remain anticipated by Kim. The alternative ground over Kim in view of Kawano in paragraph 18, and the grounds over Matsui and over Kawano in view of Zhang in paragraphs 17, 20 and 21, are set forth above; applicant’s arguments do not address them.
Applicant’s arguments with respect to claim(s) 1–6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
This applies to the grounds of paragraphs 17, 20 and 21, and to the alternative branches of paragraphs 18 and 19 that add Kawano: the distinctions applicant draws are specific to Kim’s supply of the data voltages in synchronization with its scan signal and do not address Matsui’s selector, which holds each signal line at one voltage for a whole block period whatever the state of the scanning lines [e.g., Matsui, Paragraph 133: the control line 144 is at a LOW level and the control line 143 is at a HIGH level in the period from T0 to T1 and the period from T2 to T3 to allow the first signal line 151 carry a standard voltage; Fig. 8: T0–T4, 151, 152], or
Zhang’s black state control units, which hold the black state voltage on one column set’s data lines through the entire scan [e.g., Zhang, Paragraph 104: the pixel units PU in an odd column may be lit, while the pixel units PU in an even column may always be in the black state].
Applicant’s statement that the dependent claims are allowable for their dependency on claim 1 (Remarks, page 10) is answered by the rejection of claim 1 above. The further statement that each is allowable for the additional features it recites identifies no feature and no reference. Applicant’s arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. See 37 CFR 1.111(b) (“A general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references does not comply with the requirements of this section.”).
Claims 2–6 are rejected above on their own recitations.
Election / Restrictions
Claims 7–17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species/invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 22 June 2026. The requirement was made final in the Office action mailed 29 June 2026.
Applicant requests that claims 7–17 be rejoined and allowed (Remarks, page 10).
Rejoinder is considered when the claims to the elected invention are in condition for allowance; claim 1 is rejected above.
Claims 13–17 were not amended and do not depend from claim 7: claim 13 is an independent claim that does not recite the limitations added to claim 1 by the amendment.
“A withdrawn claim that does not require all the limitations of an allowable claim will not be rejoined.” MPEP § 821.04. “In order to retain the right to rejoinder, applicant is advised that the claims to the nonelected invention(s) should be amended during prosecution to require the limitations of the elected invention. Failure to do so may result in a loss of the right to rejoinder.” Id.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Blank et al. (US 2020/0357331 A1) relates to dividing each emission frame of a light emitting diode array into sub-frames in which different portions of the diodes are turned on to reduce peak current.
Kim Yang Wan (US 2006/0114199 A1) relates to an organic light emitting display in which a black voltage is supplied to the data lines of a color group of columns during a non-emission sub-frame through a selector of the data driver.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached Monday - Friday (7:30AM - 4PM).
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Jeff Piziali/
Primary Examiner, Art Unit 2628
29 September 2026
