DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This Application is a continuation of Parent Application No. 18/626344, now US Patent 12,329,003. After comparison between pending claims and patent claims, the pending claims are not patentably distinct from the patent claims. Therefore, there are double patenting rejections below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11, and 13-19 of U.S. Patent No. 12,329,003.
Pending claims
Patent claims
1. An electronic device comprising a display device providing a screen wherein the display device comprises:
a substrate; a circuit layer disposed on the substrate, wherein the substrate comprises a display area in which emission areas are arranged, and a non-display area disposed around the display area, and
the circuit layer comprises:
data lines;
first dummy lines extending in a first direction intersecting the data lines;
second dummy lines extending parallel to the data lines, each of the second dummy lines neighboring one of the data lines; and
a reset control line extending in the first direction, and overlapping at least one of the first dummy lines.
2. The electronic device of claim 1, wherein the display device further comprises an element layer disposed on the circuit layer, wherein the display area comprises a non-emission area between the emission areas, and light sensing areas disposed in the non-emission area,
the element layer comprises light emitting elements disposed in the emission areas and light sensing elements respectively disposed in the light sensing areas,
the circuit layer further comprises: light emitting pixel drivers electrically connected to the data lines, each of
the light emitting pixel drivers electrically connected to one of the light emitting elements; and light sensing pixel drivers electrically connected to the reset control line, each of the light sensing pixel drivers electrically connected to one of the light sensing elements, and
wherein the light sensing pixel drivers are reset based on a reset control signal which is transmitted through the reset control line.
3. The electronic device of claim 2, wherein the display device further comprises a display driving circuit outputting data signals to the data lines, wherein the circuit layer further comprises data supply lines disposed in the non- display area, and electrically connected between the data lines and the display driving circuit,
a bypass area on one side of the display area comprises a bypass middle area at a center of the bypass area, a first bypass side area between the bypass middle area and the non-display area, and a second bypass side area disposed between the bypass middle area and the first bypass side area,
the data lines comprise a first data line disposed in the first bypass side area, and a second data line disposed in the second bypass side area,
the first dummy lines comprise a first transmission bypass line electrically connected to the first data line,
the second dummy lines comprise a second transmission bypass line paired with the second data line and electrically connected to the first transmission bypass line,
among the data supply lines, a first data supply line transmitting the data signal to
the first data line is electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line,
among the data supply lines, a second data supply line transmitting the data signal of the second data line is directly electrically connected to the second data line, and
among the first dummy lines, the first transmission bypass line overlaps the reset control line.
4. The electronic device of claim 3, wherein the circuit layer further comprises:
a first power supply line and a second power supply line disposed in the non- display area, and transmitting a first power and a second power for driving the light emitting elements, respectively; and
a first power line electrically connected between the light emitting pixel drivers and the first power supply line,
one of the light emitting elements is electrically connected between one of the light emitting pixel drivers and the second power, and
the one light emitting pixel driver comprises:
a first transistor generating a driving current for driving the one light emitting element;
a second transistor electrically connected between one of the data lines and a first electrode of the first transistor;
a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor;
a fourth transistor electrically connected between a first initialization power line for transmitting a first initialization power and the gate electrode of the first transistor;
a fifth transistor electrically connected between the first power line and the first electrode of the first transistor;
a sixth transistor electrically connected between the second electrode of the first transistor and the one light emitting element;
a seventh transistor electrically connected between a second initialization power line for transmitting a second initialization power and the one light emitting element; and
an eighth transistor electrically connected between a bias power line for transmitting a bias power and the first electrode of the first transistor.
5. The electronic device of claim 4, wherein the circuit layer further comprises a read-out line electrically connected to the light sensing pixel drivers,
one of the light sensing elements is electrically connected between an element output node of one of the light sensing pixel drivers and the second power, and
the one light sensing pixel driver comprises:
a ninth transistor configured to be turned on in response to a voltage level of the element output node;
a tenth transistor electrically connected between a reset voltage line for transmitting a reset voltage and the element output node, and configured to be turned on in response to the reset control signal of the reset control line; and
an eleventh transistor electrically connected between the read-out line and the ninth transistor.
6. The electronic device of claim 5, wherein the second transistor and the eleventh transistor are turned on in response to a scan write signal of a scan write line,
the scan write signal is transmitted to the light emitting pixel drivers and the light
sensing pixel drivers during each image frame,
a blank period in which a voltage level of the scan write line is maintained at a turn- off level is disposed between consecutive image frame periods, and
a voltage level of the reset control line varies during the blank period.
7. The electronic device of claim 6, wherein the reset control signal of the reset control line is transmitted to the light sensing pixel drivers during the blank period between consecutive image frame periods.
8. The electronic device of claim 6, wherein a voltage level of the reset control line varies in a first form during a first blank period, and varies in a second form opposite to the first form during a second blank period after the first blank period, and at least one image frame period is disposed between the first blank period and the second blank period.
9. The electronic device of claim 6, wherein the third transistor is turned on in response to a gate control signal of a gate control line, the fourth transistor is turned on in response to a scan initialization signal of a scan initialization line, and
the gate control signal and the scan initialization signal are transmitted to all of the light emitting pixel drivers during each image frame period.
10. The electronic device of claim 6, wherein the reset control line comprises:
an extension portion extending in the first direction; and
a protrusion branching out from the extension portion and overlapping a channel portion of the tenth transistor.
11. The electronic device of claim 10, wherein the protrusion forms a loop with two connection points to the extension portion.
12. The electronic device of claim 3, wherein the first dummy lines further comprise first auxiliary lines electrically connected to the second power supply line, and the second dummy lines further comprise second auxiliary lines electrically connected to the first auxiliary lines and the second power supply line.
13. A display device comprising:
a substrate; and
a circuit layer disposed on the substrate,
wherein the substrate comprises a display area in which emission areas are
arranged, and a non-display area disposed around the display area,
a bypass area on one side of the display area comprises a bypass middle area at a center of the bypass area, a first bypass side area between the bypass middle area and the non-display area, and a second bypass side area disposed between the bypass middle area and the first bypass side area, and
the circuit layer comprises:
data lines;
a first transmission bypass line extending in the first direction crossing the data lines, and electrically connected to a first data line disposed in the first bypass side area among the data lines;
a second transmission bypass line extending parallel to the data lines, paired with a second data line disposed in the second bypass side area among the data lines, and electrically connected to the first transmission bypass line; and
a reset control line extending in the first direction, and overlapping the first transmission bypass line.
14. The display device of claim 13, further comprising an element layer disposed on the circuit layer,
wherein the display area comprises a non-emission area between the emission areas,
and light sensing areas disposed in the non-emission area,
the element layer comprises light emitting elements disposed in the emission areas and light sensing elements respectively disposed in the light sensing areas,
the circuit layer further comprises:
light emitting pixel drivers electrically connected to the data lines, each of the light emitting pixel drivers electrically connected to one of the light emitting
elements; and
light sensing pixel drivers electrically connected to the reset control line, each of the light sensing pixel drivers electrically connected to one of the light sensing elements, and
wherein the reset control line transmits a reset control signal for resetting an
element output node of each of the light sensing pixel drivers.
15. The display device of claim 14, further comprising a display driving circuit outputting data signals of the data lines,
wherein the circuit layer further comprises data supply lines disposed in the non- display area, and electrically connected between the data lines and the display driving circuit,
among the data supply lines, a first data supply line transmitting the data signal to
the first data line is electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line, and
among the data supply lines, a second data supply line transmitting the data signal to the second data line is directly electrically connected to the second data line.
16. The display device of claim 15, wherein the circuit layer further comprises a read-out line electrically connected to the light sensing pixel drivers,
one of the light emitting elements is electrically connected between one of the light emitting pixel drivers and the second power,
one of the light sensing elements is electrically connected between an element output node of one of the light sensing pixel drivers and the second power,
the one light emitting pixel driver comprises:
a first transistor generating a driving current for driving the one light emitting element;
a second transistor electrically connected between one of the data lines and a first electrode of the first transistor;
a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor;
a fourth transistor electrically connected between a first initialization power line for transmitting a first initialization power and the gate electrode of the first transistor;
a fifth transistor electrically connected between a first power line for transmitting the first power and the first electrode of the first transistor;
a sixth transistor electrically connected between the second electrode of the first transistor and the one light emitting element;
a seventh transistor electrically connected between a second initialization power line for transmitting a second initialization power and the one light emitting element; and
an eighth transistor electrically connected between a bias power line for transmitting a bias power and the first electrode of the first transistor, and
the one light sensing pixel driver comprises:
a ninth transistor configured to be turned on in response to a voltage level of the element output node;
a tenth transistor electrically connected between a reset voltage line for transmitting a reset voltage and the element output node, and configured to be turned on in response to the reset control signal of the reset control line; and
an eleventh transistor electrically connected between the read-out line and the ninth transistor.
17. The display device of claim 16, wherein the second transistor and the eleventh transistor are turned on in response to a scan write signal of a scan write line,
the scan write signal is transmitted to the light emitting pixel drivers and the light sensing pixel drivers during each image frame,
a blank period in which a voltage level of the scan write line is maintained at a turn-off level is disposed between consecutive image frame periods, and
a voltage level of the reset control line varies during the blank period.
18. The display device of claim 17, wherein a voltage level of the reset control line varies in a first form during a first blank period, and varies in a second form opposite
to the first form during a second blank period after the first blank period, and
at least one image frame period is disposed between the first blank period and the second blank period.
19. The display device of claim 17, wherein the reset control line comprises:
an extension portion extending in the first direction; and
a protrusion branching out from the extension portion and overlapping a channel portion of the tenth transistor.
20. The display device of claim 19, wherein the protrusion forms a loop with two connection points to the extension portion.
1. A display device comprising:
a substrate; a circuit layer disposed on the substrate;
an element layer disposed on the circuit layer,
wherein the substrate comprises a display area in which emission areas are arranged, and a non-display area disposed around the display area,
the display area comprises a non-emission area between the emission areas, and light sensing areas disposed in the non-emission area,
the element layer comprises light emitting elements disposed in the emission areas and light sensing elements respectively disposed in the light sensing areas, and
the circuit layer comprises:
light emitting pixel drivers electrically connected to the light emitting elements; light sensing pixel drivers electrically connected to the light sensing elements, ;
data lines electrically connected to the light emitting pixel drivers;
first dummy lines extending in a first direction intersecting the data lines;
second dummy lines extending parallel to the data lines, each of the second dummy lines paired with one of the data lines; and
a reset control line electrically connected to the light sensing pixel drivers, extending in the first direction, transmitting a reset control signal for resetting the light sensing pixel drivers, and overlapping at least one of the first dummy lines.
2. The display device of claim 1, further comprising a display driving circuit outputting data signals to the data lines, wherein the circuit layer further comprises data supply lines disposed in the non-display area, and electrically connected between the data lines and the display driving circuit,
a bypass area on one side of the display area comprises a bypass middle area at a center of the bypass area, a first bypass side area between the bypass middle area and the non-display area, and a second bypass side area disposed between the bypass middle area and the first bypass side area,
the data lines comprise a first data line disposed in the first bypass side area, and a second data line disposed in the second bypass side area,
the first dummy lines comprise a first transmission bypass line electrically connected to the first data line,
the second dummy lines comprise a second transmission bypass line paired with the second data line and electrically connected to the first transmission bypass line,
among the data supply lines, a first data supply line transmitting the data signal to the first data line is electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line,
among the data supply lines, a second data supply line transmitting the data signal of the second data line is directly electrically connected to the second data line, and
among the first dummy lines, the first transmission bypass line overlaps the reset control line.
3. The display device of claim 2, wherein the circuit layer further comprises:
a first power supply line and a second power supply line disposed in the non-display area, and transmitting a first power and a second power for driving the light emitting elements, respectively; and
a first power line electrically connected between the light emitting pixel drivers and the first power supply line,
one of the light emitting elements is electrically connected between one of the light emitting pixel drivers and the second power, and
the one light emitting pixel driver comprises:
a first transistor generating a driving current for driving the one light emitting element;
a second transistor electrically connected between one of the data lines and a first electrode of the first transistor;
a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor;
a fourth transistor electrically connected between a first initialization power line for transmitting a first initialization power and the gate electrode of the first transistor;
a fifth transistor electrically connected between the first power line and the first electrode of the first transistor;
a sixth transistor electrically connected between the second electrode of the first transistor and the one light emitting element;
a seventh transistor electrically connected between a second initialization power line for transmitting a second initialization power and the one light emitting element; and
an eighth transistor electrically connected between a bias power line for transmitting a bias power and the first electrode of the first transistor.
4. The display device of claim 3, wherein the circuit layer further comprises a read-out line electrically connected to the light sensing pixel drivers,
one of the light sensing elements is electrically connected between an element output node of one of the light sensing pixel drivers and the second power, and
the one light sensing pixel driver comprises:
a ninth transistor configured to be turned on in response to a voltage level of the element output node;
a tenth transistor electrically connected between a reset voltage line for transmitting a reset voltage and the element output node, and configured to be turned on in response to the reset control signal of the reset control line; and
an eleventh transistor electrically connected between the read-out line and the ninth transistor.
5. The display device of claim 4, wherein the second transistor and the eleventh transistor are turned on in response to a scan write signal of a scan write line,
the scan write signal is transmitted to the light emitting pixel drivers and the light sensing pixel drivers during each image frame,
a blank period in which a voltage level of the scan write line is maintained at a turn-off level is disposed between consecutive image frame periods, and
a voltage level of the reset control line varies during the blank period.
6. The display device of claim 5, wherein the reset control signal of the reset control line is transmitted to the light sensing pixel drivers during the blank period between consecutive image frame periods.
7. The display device of claim 5, A voltage level of the reset control line varies in a first form during a first blank period, and varies in a second form opposite to the first form during a second blank period after the first blank period, and at least one image frame period is disposed between the first blank period and the second blank period.
8. The display device of claim 5, wherein the third transistor is turned on in response to a gate control signal of a gate control line, the fourth transistor is turned on in response to a scan initialization signal of a scan initialization line, and
the gate control signal and the scan initialization signal are transmitted to all of the light emitting pixel drivers during each image frame period.
9. The display device of claim 5, wherein the reset control line comprises:
an extension portion extending in the first direction; and
a protrusion branching out from the extension portion and overlapping a channel portion of the tenth transistor.
10. The display device of claim 9, wherein the protrusion forms a loop with two connection points to the extension portion.
11. The display device of claim 2, wherein the first dummy lines further comprise first auxiliary lines electrically connected to the second power supply line, and
the second dummy lines further comprise second auxiliary lines electrically connected to the first auxiliary lines and the second power supply line.
12. The display device of claim 11, wherein two of the first auxiliary lines extend from both sides of the first transmission bypass line to the non-display area, and
one of the second auxiliary lines extends from one side of the second transmission bypass line to the non-display area.
13. A display device comprising:
a substrate;
a circuit layer disposed on the substrate; and
an element layer disposed on the circuit layer,
wherein the substrate comprises a display area in which emission areas are arranged, and a non-display area disposed around the display area,
the display area comprises a non-emission area between the emission areas, and light sensing areas disposed in the non-emission area,
the element layer comprises light emitting elements disposed in the emission areas and light sensing elements respectively disposed in the light sensing areas,
a bypass area on one side of the display area comprises a bypass middle area at a center of the bypass area, a first bypass side area between the bypass middle area and the non-display area, and a second bypass side area disposed between the bypass middle area and the first bypass side area, and
the circuit layer comprises:
light emitting pixel drivers electrically connected to the light emitting elements, respectively;
light sensing pixel drivers electrically connected to the light sensing elements, respectively;
data lines electrically connected to the light emitting pixel drivers;
a first transmission bypass line extending in the first direction crossing the data lines, and electrically connected to a first data line disposed in the first bypass side area among the data lines;
a second transmission bypass line extending parallel to the data lines, paired with a second data line disposed in the second bypass side area among the data lines, and electrically connected to the first transmission bypass line; and
a reset control line electrically connected to the light sensing pixel drivers, extending in the first direction, transmitting a reset control signal for resetting an element output node of each of the light sensing pixel drivers, and overlapping the first transmission bypass line.
14. The display device of claim 13, further comprising a display driving circuit outputting data signals of the data lines,
wherein the circuit layer further comprises data supply lines disposed in the non-display area, and electrically connected between the data lines and the display driving circuit,
among the data supply lines, a first data supply line transmitting the data signal to the first data line is electrically connected to the first data line through the first transmission bypass line and the second transmission bypass line, and
among the data supply lines, a second data supply line transmitting the data signal to the second data line is directly electrically connected to the second data line.
15. The display device of claim 14, wherein the circuit layer further comprises a read-out line electrically connected to the light sensing pixel drivers,
one of the light emitting elements is electrically connected between one of the light emitting pixel drivers and the second power,
one of the light sensing elements is electrically connected between an element output node of one of the light sensing pixel drivers and the second power,
the one light emitting pixel driver comprises:
a first transistor generating a driving current for driving the one light emitting element;
a second transistor electrically connected between one of the data lines and a first electrode of the first transistor;
a third transistor electrically connected between a gate electrode of the first transistor and a second electrode of the first transistor;
a fourth transistor electrically connected between a first initialization power line for transmitting a first initialization power and the gate electrode of the first transistor;
a fifth transistor electrically connected between a first power line for transmitting the first power and the first electrode of the first transistor;
a sixth transistor electrically connected between the second electrode of the first transistor and the one light emitting element;
a seventh transistor electrically connected between a second initialization power line for transmitting a second initialization power and the one light emitting element; and
an eighth transistor electrically connected between a bias power line for transmitting a bias power and the first electrode of the first transistor, and
the one light sensing pixel driver comprises:
a ninth transistor configured to be turned on in response to a voltage level of the element output node;
a tenth transistor electrically connected between a reset voltage line for transmitting a reset voltage and the element output node, and configured to be turned on in response to the reset control signal of the reset control line; and
an eleventh transistor electrically connected between the read-out line and the ninth transistor.
16. The display device of claim 15, wherein the second transistor and the eleventh transistor are turned on in response to a scan write signal of a scan write line,
the scan write signal is transmitted to the light emitting pixel drivers and the light sensing pixel drivers during each image frame,
a blank period in which a voltage level of the scan write line is maintained at a turn-off level is disposed between consecutive image frame periods, and
a voltage level of the reset control line varies during the blank period.
17. The display device of claim 16, wherein a voltage level of the reset control line varies in a first form during a first blank period, and varies in a second form opposite to the first form during a second blank period after the first blank period, and
at least one image frame period is disposed between the first blank period and the second blank period.
18. The display device of claim 16, wherein the reset control line comprises:
an extension portion extending in the first direction; and
a protrusion branching out from the extension portion and overlapping a channel portion of the tenth transistor.
19. The display device of claim 18, wherein the protrusion forms a loop with two connection points to the extension portion.
As can be seen above, the same limitations (bold portions) between pending independent claims 1 and 13, and patent independent claims 1 and 13 are minimal. Thus, the pending independent claims 1 and 13 have been modified to become broader than the patent independent claims 1 and 13 by moving the features “none-bold portion” to the dependent claims 2 and 14, respectively. The motivation for doing so would protect the pending claims as broad as possible in order to have more products in the industrial applicability.
In regards to the pending dependent claim(s) 3-12 and 15-20, these limitations are not patentably distinct from the patent dependent claim(s) 2-11 and 14-19, respectively.
Allowable Subject Matter
Pending dependent claims 2 and 14 are objected and patentably distinct as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang (US 2023/0143358).
Regarding claim 1, Yang teaches an electronic device comprising a display device (an electronic device has a display panel. See ¶271 Figs 3) providing a screen (a full-screen, ¶ 79)
a substrate (a substrate 75, ¶253); and
a circuit layer disposed on the substrate (a circuit layer on the substrate 75, see ¶126)
a display area (a display area 2, Fig 3, ¶83) in which emission areas (two light transmitting holes 1, ¶84) are arranged, and a non-display area (a non-display region 71, ¶84 ) disposed around the display area (the display area 2), and
the circuit layer (the circuit layer, see ¶126) comprises:
Figures 58-59 of Yang teaches data lines (data lines 8 Data) ;
first dummy lines extending in a first direction intersecting the data lines (Par. 257 and Fig 58 explained first dummy lines 82 intersects data lines 8 Data in X direction );
second dummy lines extending parallel to the data lines, each of the second dummy lines neighboring one of the data lines; (Par. 261 and Fig 59 explained second dummy lines 82 extending parallel to the data lines 8 Data in parallel in Y direction, the second dummy lines 82 adjacent the data lines 8 Data);
a reset control line extending in the first direction, and overlapping at least
one of the first dummy lines (Par. 161 and Fig 59 explained a reset line Vref overlaps the dummy lines 82 in x direction).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2020/0394967) in view of Yang (US 2023/0143358)
Regarding claim 13, Park teaches a display device (abstract, Fig 1, ¶73)
a substrate (a substrate 100, ¶74); a circuit layer disposed on the substrate (Par. 41-49 explained circuit lines DL1 to DLk and bypass lines CL1 to CLk disposed on the substrate 100);
Figures 1-3 of Park shows a display area (a display device 1000 has display area DA) in which emission areas (pixels P1 to P8) and a non-display area (DA) disposed around the display area (DA),
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a bypass area on one side of the display area comprises a bypass middle area at a center of the bypass area, a first bypass side area between the bypass middle area and the non-display area, and a second bypass side area disposed between the bypass middle area and the first bypass side area (Par. 40-46 and Figs 1-2 explained the bypass area CLA has a center of the bypass area A2, the first bypass side area A1, the second bypass side area A2, and non-display area NDA2);
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a first transmission bypass line extending in the first direction crossing the data lines, and electrically connected to a first data line disposed in the first bypass side area among the data lines (Par. 47-50 and Figs 1-2 explained a first bypass lines CL1 in the first direction D2 crossing the data lines DLs and connected to the first data lines DL1 in the first bypass side area A1)
a second transmission bypass line extending parallel to the data lines, paired with a second data line disposed in the second bypass side area among the data lines, and electrically connected to the first transmission bypass line (Par. 47-50 and Figs 1-2 explained a second bypass line CL717 extending parallel to data lines DLs, paired with a second data line DL717 and connected to the first bypass line CL 1).
Park fails to teach a reset control line extending in the first direction, and overlapping the first transmission bypass line.
Yang teaches Par. 161 and Figs 58-59 explained a reset line Vref extending in the X direction overlaps the dummy lines 82 (interpreted the bypass lines as claimed).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement a reset line Vref extending in the X direction overlaps the dummy lines 82 (interpreted the bypass lines as claimed), as Yang teaches, to modify the display device of Park. The motivation for doing so would improve the full-screen display design where the light transmitting camera located in the display region. Yang ¶ 4.
Allowable Subject Matter
Claims 2-12 and 14-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN M NGUYEN whose telephone number is 571-272-7697, and email is kevin.nguyen2@uspto.gov. The examiner can normally be reached M-T 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin K Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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KEVIN M NGUYEN
Patent Examiner, Art Unit 2628
/Kevin M Nguyen/Primary Examiner, Art Unit 2628