CTFR 19/210,015 CTFR 82232 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This action is in response to the amendment filed by Applicant on 04/02/2026. This action is made FINAL. Examiner’s Notes The Applicant’s main argument is that the prior art does not teach delaying the phase of one the scan signals. However, the Applicant does not elaborate whether this means delaying the phase of one of the scan signals but not delaying the other scan signals. Paragraph 6 of the instant application states “modulating the delay period and phase of one gate scan signal among gate scan signals supplied to pixel circuits to supply the modulated gate scan signal as another gate scan signal.” It is not clear whether there are other signals that are supplied to the plurality of pixels that are not delayed. Figure 4 of the instant application shows scan2(n) that is phase shifted; and scan2 (n-1) is not shifted relative to scan2(n). Response to Arguments 07-37 AIA Applicant's arguments filed 04/02/2026 have been fully considered but they are not persuasive. The Applicant argues that “Lin does not disclose or suggest at least, "the gate driver is configured to ... generate a first gate scan signal by delaying a phase of one of the gate scan signals, and supply the first gate scan signal to the plurality of pixels." Lin merely describes different scan signals applied to row control terminals at set times. Lin is silent, ho wever, regarding "generating a first ga te scan signal by delayin g a phase of one of the gate scan signals" [emphasis added], as recited by amended claim 1. For example, Lin describes the scan control signal Scan2(n) being asserted after the scan control signal Scan2(n-1) has been asserted and deasserted. Lin is silent, ho wever,1 5 regarding "generat[ing]" the scan control signal Scan2(n) "by delaying a phase of" the scan control signal Scan2(n-1), as is the case with the claimed "first gate scan signal" and "one of the gate scan signals." However, the Examiner respectfully disagrees with Applicant’s interpretation since there is a clear phase shift of scan2(n) when compared to scan2(n-1) . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1 and 19 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Lin et al (Publication number: US 2021/0020109) . Consider Claim 1, Lin et al shows a display device (see figure 2), comprising: (a) A display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver supplying gate scan signals to the plurality of pixels in units of horizontal lines (see figures 2 and 7). (b) Wherein the plurality of pixels include: a first transistor connected between a driving voltage line and a second node (see figure 3; and paragraphs 54-56); (The first transistor is read as Tdrive, and the second node is read as Node3). (c) A sixth transistor connected between the second node and a common voltage line (see figure 3; and paragraphs 54-56); (The sixth transistor is read as Tem2). (d) A light emitting element connected between the sixth transistor and the common voltage line (see figure 3; and paragraph 57); (Read as OLED 304, and the common voltage line is read as VSSEL). (e) A fourth transistor connected between the second node and an initialization voltage line (see figure 3; the fourth transistor is read as Tini1). (f) The gate driver generates another gate scan signal by delaying a phase of one of the gate scan signals, and supplies the another gate scan signal of which the phase is delayed to the plurality of pixels (see figure 4; and paragraphs 65-69); (see scanning signals scan1(n); scan2(n-1); and scan2(n)). Consider Claim 19, Lin et al shows an electronic device including a display device, the electronic device (see figure 2) , comprising: (a) A display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver supplying gate scan signals to the plurality of pixels in units of horizontal lines (see figures 2 and 7). (b) Wherein the plurality of pixels include: a first transistor connected between a driving voltage line and a second node (see figure 3; and paragraphs 54-56); (The first transistor is read as Tdrive, and the second node is read as Node3). (c) A sixth transistor connected between the second node and a common voltage line (see figure 3; and paragraphs 54-56); (The sixth transistor is read as Tem2). (d) A light emitting element connected between the sixth transistor and the common voltage line (see figure 3; and paragraph 57); (Read as OLED 304, and the common voltage line is read as VSSEL). (e) A fourth transistor connected between the second node and an initialization voltage line (see figure 3; the fourth transistor is read as Tini1). (f) The gate driver generates another gate scan signal by delaying a phase of one of the gate scan signals, and supplies the another gate scan signal of which the phase is delayed to the plurality of pixels (see figure 4; and paragraphs 65-69); (see scanning signals scan1(n); scan2(n-1); and scan2(n)) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (Publication number: US 2021/0020109) in view of Sun et al (Publication number: US 2024/0257732) . Consider Claim 2, Lin et al shows that the plurality of pixels further include: (a) A second transistor connected between a data line and a first node (see figure 3); (The second transistor is read as Tdata). (b) A third transistor connected between a third node and the second node (see figure 3); (The third transistor is read as Toxide). (c) An eighth transistor connected between an anode electrode of the light emitting element and a light emitting initialization line (see figure 3); (The eighth transistor is read as Tini2). (d) The first transistor is connected between the first node and the second node, and a gate electrode of the first transistor is connected to the third node (see Tdrive that is connected between Node3 (read second node, and Node1 (read as first node). Further the gate of Tdrive is connected to Node2 (read as third node). However, Lin et al does not specifically show a fifth transistor connected between the driving voltage line and the first node; a seventh transistor connected between a bias voltage line and the first node. In related art, Sun et al shows a fifth transistor connected between the driving voltage line and the first node; a seventh transistor connected between a bias voltage line and the first node (see figure 54 and paragraphs 433-436); (see T5 in figure 5 of Sun et al that is connected in a similar manner to T5 of the instant application. Further, T0 is read as the seventh transistor). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate T5 and T0 of Sun et al into the driving circuit of Lin et al in order to improve hysteresis problems (see Sun et al; paragraphs 433-436). Consider Claim 13, Lin et al shows a display device (see figure 2) , comprising: (a) A display panel in which a plurality of pixels are arranged in a display area to display an image; and a gate driver supplying gate scan signals to the plurality of pixels in units of horizontal lines (see figures 2 and 7). (b) Wherein the gate driver generates another gate scan signal by delaying a phase of one of the gate scan signals, and supplies the another gate scan signal of which the phase is delayed to the plurality of pixels (see figure 4; and paragraphs 65-69); (see scanning signals scan1(n); scan2(n-1); and scan2(n)). (c) The plurality of pixels include: a first transistor connected between a driving voltage line and a second node (see figure 3; and paragraphs 54-56); (The first transistor is read as Tdrive, and the second node is read as Node3). (d) A second transistor connected between a data line and a first node (see figure 3); (The second transistor is read as Tdata). (e) A third transistor connected between a third node and the second node (see figure 3); (The third transistor is read as Toxide). (f) A fourth transistor connected between the second node and an initialization voltage line (see figure 3; the fourth transistor is read as Tini1). (g) A sixth transistor connected between the second node and a common voltage line (see figure 3; and paragraphs 54-56); (The sixth transistor is read as Tem2). (h) An eighth transistor connected between an anode electrode of a light emitting element and a light emitting initialization line (see figure 3); (The eighth transistor is read as Tini2). (i) The light emitting element connected between the sixth transistor and the common voltage line (see Tdrive that is connected between Node3 (read second node, and Node1 (read as first node). Further the gate of Tdrive is connected to Node2 (read as third node). However, Lin et al does not specifically show a fifth transistor connected between the driving voltage line and the first node; a seventh transistor connected between a bias voltage line and the first node. In related art, Sun et al shows a fifth transistor connected between the driving voltage line and the first node; a seventh transistor connected between a bias voltage line and the first node (see figure 54 and paragraphs 433-436); (see T5 in figure 5 of Sun et al that is connected in a similar manner to T5 of the instant application. Further, T0 is read as the seventh transistor). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate T5 and T0 of Sun et al into the driving circuit of Lin et al in order to improve hysteresis problems (see Sun et al; paragraphs 433-436) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 3-12, 14-18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A FARAGALLA whose telephone number is (571)270-1107. The examiner can normally be reached Mon-Fri 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 06/12/2026 Application/Control Number: 19/210,015 Page 2 Art Unit: 2624 Application/Control Number: 19/210,015 Page 3 Art Unit: 2624 Application/Control Number: 19/210,015 Page 4 Art Unit: 2624 Application/Control Number: 19/210,015 Page 5 Art Unit: 2624 Application/Control Number: 19/210,015 Page 6 Art Unit: 2624 Application/Control Number: 19/210,015 Page 7 Art Unit: 2624 Application/Control Number: 19/210,015 Page 8 Art Unit: 2624 Application/Control Number: 19/210,015 Page 9 Art Unit: 2624
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