Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Status of Claims
- Claim(s) 1-20 is/are pending in the application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
The application has claimed priority based on prior filed U.S. Application Serial No. 18086648 (now U.S. Patent No. 11984058) filed on December 22, 2022 and prior filed U.S. Application Serial No. 18662918 (now U.S. Patent No. 12307942) filed on May 13, 2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 16, 2025 and May 29, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 8-11, 13, 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, U.S. Patent Publication No. 20120194773 in view of ordinary skill.
Consider claim 1, Kim teaches a stage (see Kim figure 2, element SRC1-SRCn+1, detailed in figure 8) comprising: a first input terminal receiving a start pulse (see Kim figure 8, element IN1 and paragraph 0051 where first input terminal IN1 of the first stage SRC1 receives the start signal STV);
a second input terminal receiving a carry clock signal (see Kim figure 8, element CK2 and paragraph 0050 where a second clock signal CKVB is supplied to the second clock terminals CK2 of the odd-numbered stages SRC1, SRC3, . . . , SRCn+1, and the first clock signal CKV is supplied to the second clock terminals CK2 of the even-numbered stages SRC2, . . . , SRCn);
a fourth input terminal receiving a clock signal (see Kim figure 8, element CK1 and paragraph 0050 where a first clock signal CKV is supplied to the first clock terminals CK1 of odd-numbered stages SRC1, SRC3, . . . , SRCn+1, and a second clock signal CKVB having a different phase from the first clock signal CKV is supplied to the first clock terminals CK1 of even-numbered stages SRC2, . . . , SRCn));
an output terminal outputting an output signal (see Kim figure 8, element OUT and paragraph 0054);
a power input terminal receiving a power source of a low level (see Kim figure 8, element V1 and paragraph 0053 where an off voltage OFF is provided to the off-voltage terminals V1 of the first to (n+1)th stages SRC1 to SRCn+1);
a first transistor including a gate electrode connected to the second input terminal, and connected between the first input terminal and a first node (see Kim figure 8, element TR11, CK2, IN1, node connecting TR11 to TR6, TR10, TR4, TR1, TR15);
a twelfth transistor including a gate electrode connected to the first node (see Kim figure 8, element TR1);
a thirteenth transistor including a gate electrode connected to a second node, and connected between the power input terminal and the output terminal (see Kim figure 8, element TR2, OUT, V1, node connecting gate of TR2 to IN2); and
a
wherein each of the first transistor, the twelfth transistor, the thirteenth transistor, and the
Kim is silent regarding a nineteenth transistor. Examiner has construed “nineteenth” as used to distinguish one element from another element as indicated in Applicants original specification paragraph 0065. Further, Kim does not explicitly discuss what type of transistor is being used. However as indicated above, Kim’s figure 8 uses a traditional symbol for an n-type transistor.
Therefore, as best understood by Examiner, the features of claim 1 would have been obvious in view of ordinary skill.
Consider claim 2, Kim as modified by ordinary skill teaches all the limitations of claim 1 and further teaches further comprising a seventh input terminal receiving an initialization control signal, wherein the nineteenth transistor includes a gate electrode connected to the seventh input terminal (see Kim figure 8, element TR6, RE, and paragraph 0053, 0090-0091 where an (n+1)th gate signal output from the (n+1)th stage SRCn+1 is provided to the reset terminals RE of the first to (n+1)th stages SRC1 to SRCn+1. When the gate signal from the last stage is supplied to the sixth transistor TR6, the sixth transistor TR6 is turned on. Accordingly, the off voltage VSS is supplied to the gate electrode of the first transistor TR1, to thereby reset all stages).
Consider claim 3, Kim as modified by ordinary skill teaches all the limitations of claim 1 and further teaches wherein the twelfth transistor is a pull-up transistor (see Kim figure 8, element TR1 and paragraph 0078 where pull-up driver part S11 includes a first transistor TR1).
Consider claim 4, Kim as modified by ordinary skill teaches all the limitations of claim 1 and further teaches wherein the thirteenth transistor is a pull-down transistor (see Kim figure 8, element TR2 and paragraph 0080 where pull-down driver part S12 includes a second transistor TR2).
Consider claim 8, Kim as modified by ordinary skill teaches all the limitations of claim 1 and further teaches wherein the output terminal is a second output terminal, and wherein the stage further comprises a first output terminal outputting a carry signal (see Kim figure 8, element CR and paragraph 0054 where first clock signal CKV is output from the carry terminals CR and the output terminals OUT of the odd-numbered stages SRC1, SRC3, . . . , SRCn+1 as the gate signal. The second clock signal CKVB is output from the carry terminals CR and the output terminals OUT of the even-numbered stages SRC2, . . . , SRCn as the gate signal. The carry signal output from the carry terminals CR is provided to the second input terminals IN2 of previous stages).
Consider claim 9, Kim as modified by ordinary skill teaches all the limitations of claim 8 and further teaches further comprising a first capacitor, wherein the first capacitor includes a first electrode connected to the first node and a second electrode connected to the first output terminal (see Kim figure 8, capacitor connected to CR and node between TR11 and TR1, TR15).
Consider claim 10, Kim as modified by ordinary skill teaches all the limitations of claim 8 and further teaches further comprising a tenth transistor, wherein the tenth transistor includes a gate electrode connected to the second node and is connected between the first output terminal and the power input terminal (see Kim figure 8, element TR9, IN1, V1 and node between TR11 and TR9, TR1).
Consider claim 11, Kim as modified by ordinary skill teaches all the limitations of claim 10 and further teaches wherein the tenth transistor is a pull-down transistor (see Kim paragraph 0080 where pull-down driver part S12 includes a second transistor TR2, a ninth transistor TR9, and a fourteenth transistor TR14).
Consider claim 13, Kim as modified by ordinary skill teaches all the limitations of claim 8 and further teaches wherein the carry clock signal is a first carry clock signal, and wherein the stage further comprises a third input terminal receiving a second carry clock signal (see Kim figure 8, element CR and paragraph 0054 where first clock signal CKV is output from the carry terminals CR and the output terminals OUT of the odd-numbered stages SRC1, SRC3, . . . , SRCn+1 as the gate signal. The second clock signal CKVB is output from the carry terminals CR and the output terminals OUT of the even-numbered stages SRC2, . . . , SRCn as the gate signal. The carry signal output from the carry terminals CR is provided to the second input terminals IN2 of previous stages).
Consider claim 17, Kim teaches a scan driver (see Kim figure 1, element 150) comprising stages outputting output signals (see Kim figure 2, element SRC1-SRCn+1 detailed in figure 8), wherein at least one of the stages comprises:
a first input terminal receiving a start pulse or being connected to a preceding stage (see Kim figure 8, element IN1 and paragraph 0051 where first input terminal IN1 of the first stage SRC1 receives the start signal STV);
a second input terminal receiving a carry clock signal (see Kim figure 8, element CK2 and paragraph 0050 where a second clock signal CKVB is supplied to the second clock terminals CK2 of the odd-numbered stages SRC1, SRC3, . . . , SRCn+1, and the first clock signal CKV is supplied to the second clock terminals CK2 of the even-numbered stages SRC2, . . . , SRCn);
a fourth input terminal receiving a clock signal (see Kim figure 8, element CK1 and paragraph 0050 where a first clock signal CKV is supplied to the first clock terminals CK1 of odd-numbered stages SRC1, SRC3, . . . , SRCn+1, and a second clock signal CKVB having a different phase from the first clock signal CKV is supplied to the first clock terminals CK1 of even-numbered stages SRC2, . . . , SRCn));
an output terminal outputting an output signal (see Kim figure 8, element OUT and paragraph 0054);
a power input terminal receiving a power source of a low level (see Kim figure 8, element V1 and paragraph 0053 where an off voltage OFF is provided to the off-voltage terminals V1 of the first to (n+1)th stages SRC1 to SRCn+1);
a first transistor including a gate electrode connected to the second input terminal, and connected between the first input terminal and a first node (see Kim figure 8, element TR11, CK2, IN1, node connecting TR11 to TR6, TR10, TR4, TR1, TR15);
a twelfth transistor including a gate electrode connected to the first node (see Kim figure 8, element TR1);
a thirteenth transistor including a gate electrode connected to a second node, and connected between the power input terminal and the output terminal (see Kim figure 8, element TR2, OUT, V1, node connecting gate of TR2 to IN2); and
a
wherein each of the first transistor, the twelfth transistor, the thirteenth transistor, and the semiconductor (see Kim figure 8 where symbol for n-type transistor is used and paragraph 0092 where first to fifteenth transistors TR1.about.TR15 may include amorphous silicon, polysilicon, or oxide semiconductor).
Kim is silent regarding a nineteenth transistor. Examiner has construed “nineteenth” as used to distinguish one element from another element as indicated in Applicants original specification paragraph 0065. Further, Kim does not explicitly discuss what type of transistor is being used. However as indicated above, Kim’s figure 8 uses a traditional symbol for an n-type transistor.
Therefore, as best understood by Examiner, the features of claim 1 would have been obvious in view of ordinary skill.
Consider claim 18, Kim as modified by ordinary skill teaches all the limitations of claim 17 and further teaches wherein twelfth transistor is a pull-up transistor (see Kim figure 8, element TR1 and paragraph 0078 where pull-up driver part S11 includes a first transistor TR1), and
wherein the thirteenth transistor is a pull-down transistor (see Kim figure 8, element TR2 and paragraph 0080 where pull-down driver part S12 includes a second transistor TR2).
Consider claim 19, Kim teaches a display device (see Kim figure 1, element 100) comprising: a pixel portion include a pixel connected to a scan line (see Kim figure 1, element PX, GL11); and
a scan driver (see Kim figure 1, element 150) including a stage (see Kim figure 2, element SRC1-SRCn+1 detailed in figure 8) to output an output signal (see Kim paragraph 0010 where gate driver is connected to the gate lines, to output a gate signals),
wherein the stage comprises:
a first input terminal receiving a start pulse (see Kim figure 8, element IN1 and paragraph 0051 where first input terminal IN1 of the first stage SRC1 receives the start signal STV);
a second input terminal receiving a carry clock signal (see Kim figure 8, element CK2 and paragraph 0050 where a second clock signal CKVB is supplied to the second clock terminals CK2 of the odd-numbered stages SRC1, SRC3, . . . , SRCn+1, and the first clock signal CKV is supplied to the second clock terminals CK2 of the even-numbered stages SRC2, . . . , SRCn);
a fourth input terminal receiving a clock signal (see Kim figure 8, element CK1 and paragraph 0050 where a first clock signal CKV is supplied to the first clock terminals CK1 of odd-numbered stages SRC1, SRC3, . . . , SRCn+1, and a second clock signal CKVB having a different phase from the first clock signal CKV is supplied to the first clock terminals CK1 of even-numbered stages SRC2, . . . , SRCn));
an output terminal outputting the output signal (see Kim figure 8, element OUT and paragraph 0054);
a power input terminal receiving a power source of a low level (see Kim figure 8, element V1 and paragraph 0053 where an off voltage OFF is provided to the off-voltage terminals V1 of the first to (n+1)th stages SRC1 to SRCn+1);
a first transistor including a gate electrode connected to the second input terminal, and connected between the first input terminal and a first node (see Kim figure 8, element TR11, CK2, IN1, node connecting TR11 to TR6, TR10, TR4, TR1, TR15);
a twelfth transistor including a gate electrode connected to the first node (see Kim figure 8, element TR1);
a thirteenth transistor including a gate electrode connected to a second node, and connected between the power input terminal and the output terminal (see Kim figure 8, element TR2, OUT, V1, node connecting gate of TR2 to IN2); and
a
wherein each of the first transistor, the twelfth transistor, the thirteenth transistor, and the
Kim is silent regarding a nineteenth transistor. Examiner has construed “nineteenth” as used to distinguish one element from another element as indicated in Applicants original specification paragraph 0065. Further, Kim does not explicitly discuss what type of transistor is being used. However as indicated above, Kim’s figure 8 uses a traditional symbol for an n-type transistor.
Therefore, as best understood by Examiner, the features of claim 1 would have been obvious in view of ordinary skill.
Consider claim 20, Kim as modified by ordinary skill teaches all the limitations of claim 19 and further teaches further comprising a timing controller, wherein the timing controller output the start pulse, the clock signal, and the carry clock signal (see Kim figure 1, element 120 and paragraphs 0032, 0044, 0055 where gate driver 150 sequentially outputs the gate signal in response to the gate control signal supplied from the timing controller 120).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al, U.S. Patent Publication No. 20120194773 in view of Lee et al, U.S. Patent Publication No. 20060071923.
Consider claim 5, Kim as modified by ordinary skill teaches all the limitations of claim 1. Kim is silent regarding wherein at least one of the first transistor and the nineteenth transistor includes sub-transistors connected in series.
In the same field of endeavor, Lee teaches a transistor including sub-transistors connected in series so as to reduce gradual failure of connected transistors (see Lee paragraph 0058).
One of ordinary skill would have been motivated to have modified Kim with the teachings of Lee to have at least one of the first transistor and the nineteenth transistor includes sub-transistors connected in series so as to reduce gradual failure of connected transistors using known techniques with predictable results.
Allowable Subject Matter
Claims 6-7, 12, 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The claimed invention recites
Claim 6 “The stage of claim 1, further comprising a second capacitor, wherein the second capacitor includes a first electrode connected to the second node, and includes a second electrode connected to a first control node.”
Claim 7 “The stage of claim 1, further comprising a second transistor, wherein the second transistor includes a gate electrode connected to the first node, and is connected between the first control node and the power input terminal.”
Claim 12 “The stage of claim 8, further comprising a fourth capacitor, wherein the fourth capacitor includes a first electrode connected to the first output terminal and a second electrode connected to the power input terminal.”
Claim 14 “The stage of claim 13, further comprising a ninth transistor including, wherein the ninth transistor includes a gate electrode connected to the first node, and is connected between the third input terminal and the first output terminal.”
Claim 15 “The stage of claim 13, further comprising a sixth transistor, wherein the sixth transistor includes a gate electrode connected to the third input terminal, and is connected between the first node and a third control node.”
Claim 16 “The stage of claim 15 further comprising a seventh transistor, wherein the seventh transistor includes a gate electrode connected to the second node, and is connected between the third control node and the first output terminal.”
The following prior arts are representative of the state of the prior art:
Kim et al, U.S. Patent Publication No. 20120194773 (figure 8)
Han et al, U.S. Patent Publication No. 20150015562 (figure 3)
Hwang et al, U.S. Patent Publication No. 20170084245 (figure 6)
The prior arts cited fails to fairly teach or suggest the combined features of the invention including the features of dependent claims 6, 7, 12, 14-16.
These features find support at least at figures 3, 8, 9 of Applicant’s original specification.
As such, modification of the prior art of record can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior art themselves. Therefore, it is not clear that one of ordinary skill in the art would have made the necessary modifications to the prior art of record to encompass the limitations set forth in the present application. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the claimed inventions. Hence, claims 6-7, 12, 14-16 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ahn et al, U.S. Patent Publication No. 20180103231 (display device), Lee et al, U.S. Patent Publication No. 202000066211 (scan driver), Choi et al, U.S. Patent Publication No. 20200184898 (scan driver).
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/Dorothy Harris/Primary Examiner, Art Unit 2625