DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-6, 8, 10, 12, 14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2021/0201816; hereinafter Kim), in view of Li et al (US 2020/0202786; hereinafter Li).
• Regarding claim 1, Kim discloses a gate driver (figures 8, 10, and 11) comprising:
a plurality of stages (each of elements ST[1]-ST[m] in figures 8, 10, and 11), each comprising:
a control circuit configured to control a voltage of at least one control node and a voltage of at least one inversion control node (at least elements IC1, NCC1, NRC1, and SCC1 in figure 10 and ¶s 208-218);
an odd gate output circuit configured to output an odd gate signal in response to the voltage of the at least one control node and the voltage of the at least one inversion control node (element OBC1 in figures 10 and 11 outputting SS[n] and SS[n+2]); and
an even gate output circuit configured to output an even gate signal in response to the voltage of the at least one control node and the voltage of the at least one inversion control node (element OBC1 in figures 10 and 11 outputting SS[n+1] and SS[n+3]),
wherein:
the odd gate signal is applied to an odd pixel (elements P1 and P2 in figure 7A and ¶s 143-145),
the even gate signal is applied to an even pixel (elements P3 and P4 in figure 7B and ¶s 146-148),
the odd pixel and the even pixel are included in a same pixel row (elements P1-P4 located between elements GL1 and GL2 in figures 7A and 7B are located in the same row), and
the odd pixel and the even pixel share one data line (elements P1 and P3 share element DLa and elements P2 and P4 share element DLd in figures 7A and 7B).
However, Kim fails to disclose the additional details of the gate driver.
In the same field of endeavor, Li discloses where:
the odd pixel and the even pixel are arranged adjacent to each other (first and second sub-pixel circuits in at least figures 1 and 5) and
the one data line is disposed between the odd pixel and the even pixel (Data1 in figures 1 and 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim according to the teachings of Li, for the purposes of reducing the number of data lines, reducing a pixel layout space, achieving high resolution in a limited space, reducing the number of source drivers, and reducing the product cost (¶ 40).
• Regarding claims 2, 4-6, 8, 10, 12, and 14, Kim, in view of Li, discloses everything claimed, as applied to claim 1. Additionally, Kim discloses where:
Claim 2: a period in which the odd gate signal has an activation level differs from a period in which the even gate signal has the activation level (note SS[1]-SS[4] in figure 9).
Claim 4: the at least one inversion control node includes a first inversion control node and a second inversion control node (1Qbo and 1Qbe in figure 11), and
the control circuit comprises:
an input circuit configured to provide an input signal to the at least one control node (elements T1 and T2 in figures 10 and 11); and
a reset circuit configured to reset the voltage of the at least one control node (elements T21 and T22 in figures 10 and 11).
Claim 5: the input circuit comprises:
a first transistor pair including a gate receiving a first carry clock signal, a first electrode receiving an input signal, and a second electrode connected to the at least one control node (elements T1 and T2 in figure 11 and ¶ 244), and
the reset circuit comprises:
a second transistor pair including a gate receiving a reset signal, a first electrode receiving a first low gate voltage, and a second electrode connected to the at least one control node (elements T21 and T22 in figure 11 and ¶s 286 and 287).
Claim 6: the control circuit further comprises:
a deterioration prevention circuit configured to prevent a deterioration of the first transistor pair of the input circuit and a deterioration of the second transistor pair of the reset circuit (elements T3a, T3b, T4a, and T4b in figure 11 and ¶s 248-256).
Claim 8: the at least one inversion control node includes a first inversion control node and a second inversion control node (1Qbo and 1Qbe in figure 11 and ¶s 261-267), and
the control circuit further includes:
a first selection circuit configured to control a voltage of the first inversion control node in response to a first selection signal (element IC1 in figure 11); and
a second selection circuit configured to control a voltage of the second inversion control node in response to a second selection signal (element IC2 in figure 11; where 1Qbe and 2Qbo are connected in figure 11).
Claim 10: the gate driver further comprises:
a carry output circuit configured to output a carry signal in response to the voltage of the at least one control node and the voltage of the at least one inversion control node (element OBC1 in figures 10 and 11 and ¶ 219).
Claim 12: the at least one inversion control node includes a first inversion control node and a second inversion control node (1Qbo and 1Qbe in figure 11 and ¶s 261-267), and
the odd gate output circuit comprises:
a tenth odd transistor including a gate connected to the at least one control node, a first electrode receiving an odd clock signal, and a second electrode connected to an odd gate output node from which the odd gate signal is output (element T29 in figure 11);
a eleventh odd transistor including a gate connected to the first inversion control node, a first electrode receiving a first low gate voltage, and a second electrode connected to the odd gate output node (element T30 in figure 11); and
a twelfth odd transistor including a gate connected to the second inversion control node, a first electrode receiving the first low gate voltage, and a second electrode connected to the odd gate output node (element T31 in figure 11).
Claim 14: the at least one inversion control node includes a first inversion control node and a second inversion control node (1Qbo and 1Qbe in figure 11 and ¶s 261-267), and
the even gate output circuit comprises:
a tenth even transistor including a gate connected to the at least one control node, a first electrode receiving an even clock signal, and a second electrode connected to an even gate output node from which the even gate signal is output (element T32 in figure 11);
a eleventh even transistor including a gate connected to the first inversion control node, a first electrode receiving a low gate voltage, and a second electrode connected to the even gate output node (element T33 in figure 11); and
a twelfth even transistor including a gate connected to the second inversion control node, a first electrode receiving a first low gate voltage, and a second electrode connected to the even gate output node (element T34 in figure 11).
• Regarding claim 16, Kim discloses a display device (figures 1 and 7 and ¶s 3-5), comprising:
a display panel (figure 1) including an odd pixel and an even pixel included in a same pixel row and sharing one data line (elements P1 and P3 share element DLa and elements P2 and P4 share element DLd in figures 7A and 7B);
a data driver configured to provide an odd data voltage and an even data voltage to the one data line (element 700 in figure 1 ¶ 47 outputting data along at least elements DLa and DLd in figures 7A and 7B);
a gate driver configured to provide an odd gate signal and an even gate signal to the odd pixel and the even pixel, respectively (element 500 in figure 1 and ¶ 47); and
a driving controller configured to control the data driver and the gate driver (element 300 in figure 1 and ¶ 47),
wherein the odd pixel receives the odd data voltage in response to the odd gate signal, and the even pixel receives the even data voltage in response to the even gate signal (¶s 62 and 63),
wherein the gate driver comprises a plurality of stages (figure 8), and each of the plurality of stages comprises:
a control circuit configured to control a voltage of at least one control node and a voltage of at least one inversion control node (at least elements IC1, NCC1, NRC1, and SCC1 in figure 10 and ¶s 208-218);
an odd gate output circuit configured to output an odd gate signal in response to the voltage of the at least one control node and the voltage of the at least one inversion control node (element OBC1 in figures 10 and 11 outputting SS[n] and SS[n+2]); and
an even gate output circuit configured to output an even gate signal in response to the voltage of the at least one control node and the voltage of the at least one inversion control node (element OBC1 in figures 10 and 11 outputting SS[n+1] and SS[n+3]).
However, Kim fails to disclose the additional details of the gate driver.
In the same field of endeavor, Li discloses where:
the odd pixel and the even pixel are arranged adjacent to each other (first and second sub-pixel circuits in at least figures 1 and 5) and
the one data line is disposed between the odd pixel and the even pixel (Data1 in figures 1 and 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim according to the teachings of Li, for the purposes of reducing the number of data lines, reducing a pixel layout space, achieving high resolution in a limited space, reducing the number of source drivers, and reducing the product cost (¶ 40).
• Regarding claims 17-19, Kim, in view of Li, discloses everything claimed, as applied to claim 16. Additionally, Kim discloses where:
Claim 17: a period in which the odd gate signal has an activation level differs from a period in which the even gate signal has the activation level (note SS[1]-SS[4] in figure 9).
Claim 18: the at least one inversion control node includes a first inversion control node and a second inversion control node (1Qbo and 1Qbe in figure 11), and
the control circuit comprises:
an input circuit configured to provide an input signal to the at least one control node (element SCC1 in figures 10 and 11); and
a reset circuit configured to reset the voltage of the at least one control node (element NRC1 in figures 10 and 11).
Claim 19: the input circuit comprises:
a first transistor including a gate receiving a first carry clock signal, a first electrode receiving an input signal, and a second electrode connected to the at least one control node (elements T1 and T2 in figure 11 and ¶ 244), and
the reset circuit comprises:
a second transistor including a gate receiving a reset signal, a first electrode receiving a first low gate voltage, and a second electrode connected to the at least one control node (elements T21 and T22 in figure 11 and ¶s 286 and 287).
• Regarding claim 20, Kim discloses an electronic device (figures 1 and 7 and ¶s 3-5), comprising:
a display panel (figure 1) including an odd pixel and an even pixel [included] in a same pixel row and sharing one data line (elements P1 and P3 share element DLa and elements P2 and P4 share element DLd in figures 7A and 7B);
a data driver configured to provide an odd data voltage and an even data voltage to the one data line (element 700 in figure 1 ¶ 47 outputting data along at least elements DLa and DLd in figures 7A and 7B);
a gate driver configured to provide an odd gate signal and an even gate signal to the odd pixel and the even pixel, respectively (element 500 in figure 1 and ¶ 47);
a driving controller configured to control the data driver and the gate driver (element 300 in figure 1 and ¶ 47); and
a processor configured to control the driving controller (¶ 67),
wherein:
the odd pixel receives the odd data voltage in response to the odd gate signal (elements P1 and P2 in figure 7A and ¶s 62, 63, and 143-145), and
the even pixel receives the even data voltage in response to the even gate signal (elements P3 and P4 in figure 7A and ¶s 62, 63, and 143-145),
the gate driver comprises a plurality of stages (figure 8), and
each of the stages comprises:
a control circuit configured to control a voltage of at least one control node and a voltage of at least one inversion control node (at least elements IC1, NCC1, NRC1, and SCC1 in figure 10 and ¶s 208-218);
an odd gate output circuit configured to output an odd gate signal in response to the voltage of the at least one control node and the voltage of the at least one inversion control node (element OBC1 in figures 10 and 11 outputting SS[n] and SS[n+2]); and
an even gate output circuit configured to output an even gate signal in response to the voltage of the at least one control node and the voltage of the at least one inversion control node (element OBC1 in figures 10 and 11 outputting SS[n+1] and SS[n+3]).
However, Kim fails to disclose the additional details of the gate driver.
In the same field of endeavor, Li discloses where:
the odd pixel and the even pixel are disposed adjacent to one another in a same pixel row and share one data line (first and second sub-pixel circuits in at least figures 1 and 5);
the odd pixel and the even pixel are arranged adjacent to each other (first and second sub-pixel circuits in at least figures 1 and 5); and
the one data line is disposed between the odd pixel and the even pixel (Data1 in figures 1 and 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim according to the teachings of Li, for the purposes of reducing the number of data lines, reducing a pixel layout space, achieving high resolution in a limited space, reducing the number of source drivers, and reducing the product cost (¶ 40).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Li, and further in view of Jang (US 2015/0317954).
• Regarding claim 9, Kim, in view of Li, discloses everything claimed, as applied to claim 8. Additionally, Kim discloses where:
Claim 9: the first selection circuit comprises:
a thirteenth transistor pair including a gate receiving the first selection signal, a first electrode receiving the first selection signal, and a second electrode (elements T11a and T11b in figure 11);
a fourteenth transistor including a gate connected to the second electrode of the thirteenth transistor pair, a first electrode receiving the first selection signal, and a second electrode connected to the first inversion control node (element T12 in figure 11);
a fifteenth transistor including a gate connected to the at least one control node, a first electrode receiving a first low gate voltage, and a second electrode connected to the second electrode of the thirteenth transistor pair and the gate of the fourteenth transistor (element T14 in figure 11); and
a sixteenth transistor including a gate connected to the at least one control node, a first electrode receiving a second low gate voltage, and a second electrode connected to the first inversion control node (element T13 in figure 11), and
the second selection circuit comprises:
a seventeenth transistor pair including a gate receiving the second selection signal, a first electrode receiving the second selection signal, and a second electrode (elements T11a and T11b in figure 11);
an eighteenth transistor including a gate connected to the second electrode of the seventeenth transistor pair, a first electrode receiving the second selection signal, and a second electrode connected to the second inversion control node (element T12 in figure 11);
a nineteenth transistor including a gate connected to the at least one control node, a first electrode receiving the first low gate voltage, and a second electrode connected to the second electrode of the seventeenth transistor pair and the gate of the eighteenth transistor (element T14 in figure 11); and
a twentieth transistor including a gate connected to the at least one control node, a first electrode receiving the second low gate voltage, and a second electrode connected to the second inversion control node (element T13 in figure 11).
However, Kim, in view of Li, fails to disclose the additional details of the gate driver.
In the same field of endeavor, Jang discloses where:
Claim 9: the first selection circuit comprises:
a third capacitor including a first electrode connected to the second electrode of the thirteenth transistor pair, the gate of the fourteenth transistor, and a first electrode of the fifteenth transistor, and a second electrode connected to the first inversion control node (element C3 in figure 14 and ¶ 118), and
the second selection circuit comprises:
a fourth capacitor including a first electrode connected to the second electrode of the seventeenth transistor pair, the gate of the eighteenth transistor and a second electrode connected to the second inversion control node (element C3 in figure 14 and ¶ 118; where elements IC1 and IC2 in figure 11 of Kim are identical and would be modified identically by the structure of figure 14 of Jang).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim, as modified by Li, according to the teachings of Jang, for the purpose of bootstrapping the gate according to high logic levels applied to the drain of a transistor which supplies a high voltage to a QB node (¶s 104 and 118).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Li, and further in view of Choi et al (US 2021/0104197; hereinafter Choi).
• Regarding claim 11, Kim, in view of Li, discloses everything claimed, as applied to claim 10. Additionally, Kim discloses where:
Claim 11: the at least one inversion control node includes a first inversion control node and a second inversion control node (1Qbo and 1Qbe in figure 11 and ¶s 261-267), and
the carry output circuit comprises:
a seventh transistor including a gate connected to the at least one control node, a first electrode receiving the second carry clock signal, and a second electrode connected to the carry output node (element T41 in figure 11);
an eighth transistor including a gate connected to the first inversion control node, and a first electrode receiving a second low gate voltage, and a second electrode connected to the carry output node (element T42 in figure 11); and
a ninth transistor including a gate connected to the second inversion control node, a first electrode receiving the second low gate voltage, and a second electrode connected to the carry output node (element T43 in figure 11).
However, Kim, in view of Li, fails to disclose the additional details of the gate driver.
In the same field of endeavor, Choi discloses where:
Claim 11: [an inversion control node] (QB in figure 6), and the carry output circuit comprises:
a fourth transistor including a gate receiving a second carry clock signal, a first electrode connected to the at least one control node, and a second electrode (element T5 in figure 6 and ¶s 107-109 and 149);
a fifth transistor including a gate connected to the first inversion control node, a first electrode connected to the second electrode of the fourth transistor, and a second electrode connected to a carry output node from which a carry signal is output (element T6 in figure 6 and ¶s 107-109 and 149);
a sixth transistor including a gate connected to the second inversion control node, a first electrode connected to the second electrode of the fourth transistor and the first electrode of the fifth transistor, and a second electrode connected to the carry output node (element T5 in figure 6 and ¶s 107-109 and 149; where Kim provides the basic gate driver structure in figure 11).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim, as modified by Li, according to the teachings of Choi, for the purpose of integrating a scan driver in a narrower dead space in a display device (¶s 6-8).
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Li, and further in view of Nishikawa et al (US 2017/0186373; hereinafter Nishikawa).
• Regarding claims 13 and 15, Kim, in view of Li, discloses everything claimed, as applied to claims 12 and 14, respectively. However, Kim, in view of Li, fails to disclose the additional details of the gate driver.
In the same field of endeavor, Nishikawa discloses where:
Claim 13: the at least one control node includes a first control node and a second control node (N1 and N2 in figure 4 and ¶s 268 and 269), and
the odd gate output circuit further comprises:
an odd always-on transistor including a gate receiving a high gate signal, a first electrode connected to the first control node, and a second electrode connected to the second control node (element Q15 in figure 4 and ¶s 268 and 269).
Claim 15: the at least one control node includes a first control node and a third control node (N1 and N3 in figure 4 and ¶s 268 and 269), and
the even gate output circuit further comprises:
an even always-on transistor including a gate receiving a high gate signal, a first electrode connected to the first control node, and a second electrode connected to the third control node (element Q15 in figure 4 and ¶s 268 and 269; see also).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Kim according to the teachings of Nishikawa, for the purpose of assisting in an increase in the voltage of the node N2 by bootstrap by going into an off state and electrically disconnecting the nodes N1 and N2 when the voltage of the node N2 reaches a predetermined level or higher (¶ 269).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either alone or in combination, fails to teach or fairly suggest, in claim 7, where “the deterioration prevention circuit includes a third transistor pair including a first paired transistor and a second paired transistor each having a gate connected to the at least one control node, the first paired transistor having a source or drain directly connected to a source or drain of the second paired transistor, the first paired transistor having a first electrode receiving a high gate voltage, the second paired transistor having a second electrode connected to a middle node of the first transistor pair and a middle node of the second transistor pair”, in combination with all the limitations in all the claims from which it depends.
Response to Arguments
Applicant’s arguments with respect to claims 1, 16, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Closing Remarks/Comments
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622
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