DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The instant application having application No. 19/210,573 has a total of 20 claims pending in the application; there are 3 independent claim and 17 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING IDS:
3. The information disclosure statement (IDS) submitted on 05/30/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner and a copy (copies) of PTOL-1449(s) initiated and signed by the Examiner is/are attached.
INFORMATION CONCERNING DRAWING:
4. The applicant’s drawings submitted on 05/16/2025 are acceptable for examination purposes.
INFORMATION CONCERNING FOREIGN PRIORITY:
5. Acknowledgment is made of applicant’s claim for foreign priority based on an application fled in People’s Republic of China on 11/18/2022.
RELEVANT PRIOR ART THE EXAMINER:
6. The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Tidwell et al. (US 20180335978 A1) teaches “…the one or more command queues include a high priority queue for read commands and at least one low priority queue for write and erase commands” (par. 26).
SEN et al. (US 20200104275 A1) teaches “…In some examples, remote direct memory access semantics can use queue pairs (QP) associated with remote direct memory access (RDMA) as described at least in iWARP, InfiniBand, RDMA over converged Ethernet (RoCE) v2...” (par. 0017)
Xu et al. (US 12524360 B1) teaches the DMA queue can be implemented using a queue pair that includes a read descriptor queue 152 and a write descriptor queue 154. DMA engine 150 may also include multiple DMA queues and/or multiple queue pairs…” (col. 4, lines 5-10).
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 9, 12-15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Losh “Losh” (US 20170123730 A1) in view of Allison et al. “Allison” (US 20090307523 A1).
7. Regarding claim 1, Losh teaches or suggests:
“A data method (e.g., Fig. 7) comprising: receiving a first access command, wherein the first access command is a write command;” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests).
“placing the first access command in a first send queue;” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests and then place… write requests 516 in the write queue 514). Write queue represents the first send queue recited in the claim.
“receiving a second access command, wherein the second access command is a non-write command;” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests and then place read requests 506).
“and placing the second access command in a second send queue,” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests and then place read requests 506 in the read queue 506; method described in Fig. 7). However, Losh does not appear to expressly teach while Allison discloses:
“wherein a second processing priority of the second send queue is higher than a first processing priority of the first send queue.” (e.g., ¶ 0012, read operations typically have priority over write operations, such that the read queue 120 is serviced until all its entries have been processed or priority shifts to favor writes for cases such as write queue nearly or completely full).
Disclosures by Losh and Allison are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the Memory Input/Output Management taught by Losh to include the request and/or queue priority taught by Allison.
The motivation for including the priority as taught by paragraph [0011] of Allison is to improve system performance .
Therefore, it would have been obvious to combine teaching of Allison with Losh to obtain the invention as specified in the claim.
8. Regarding claim 9, Losh teaches or suggests:
“A storage device (e.g., server 104 in Fig. 1) comprising: a memory (e.g., memory 108 in Fig. 1) configured to store instructions;” (e.g., Fig. 1, ¶ 0024, The memory 108 may include machine readable instructions).
“and at least one processor (e.g., processor 016 in Fig. 1) coupled to the memory and configured to execute the instructions to cause (e.g., Abstract; ¶ 0024, memory 108 may include machine readable instructions for execution on the processor 106. Such instructions may be associated with various applications as well as an operating system 124) the storage device to: receive a first access command, wherein the first access command is a write command;” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests).
“place the first access command in a first send queue;” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests and then place… write requests 516 in the write queue 514). Write queue represents the first send queue recited in the claim.
“receive a second access command, wherein the second access command is a non-write command;” ;” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests and then place read requests 506).
“and place the second access command in a second send queue,” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests and then place read requests 506 in the read queue 506; method described in Fig. 7). However, Losh does not appear to expressly teach while Allison discloses:
“wherein a second processing priority of the second send queue is higher than a first processing priority of the first send queue.” the second send queue is higher than a first processing priority of the first send queue.” (e.g., ¶ 0012, read operations typically have priority over write operations, such that the read queue 120 is serviced until all its entries have been processed or priority shifts to favor writes for cases such as write queue nearly or completely full). The motivation for combining is based on the same rational presented above with respect to the independent claim 1.
9. Regarding claim 17, Losh teaches or suggests:
“A computer program product comprising computer-executable instructions that are stored on a non-transitory computer-readable medium and that, when executed by at least one processor (e.g., claim 1), cause an apparatus to: receive a first access command, wherein the first access command is a write command;” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests).
“place the first access command in a first send queue;” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests and then place… write requests 516 in the write queue 514). Write queue represents the first send queue recited in the claim.
“receive a second access command, wherein the second access command is a non-write command;” ;” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests and then place read requests 506).
“and place the second access command in a second send queue,” (e.g., Abstract; Fig. 5, ¶ 0047, the sorting module 204 may identify a type of received requests and then place read requests 506 in the read queue 506; method described in Fig. 7). However, Losh does not appear to expressly teach while Allison discloses:
“wherein a second processing priority of the second send queue is higher than a first processing priority of the first send queue.” (e.g., ¶ 0012, read operations typically have priority over write operations, such that the read queue 120 is serviced until all its entries have been processed or priority shifts to favor writes for cases such as write queue nearly or completely full). The motivation for combining is based on the same rational presented above with respect to the independent claim 1.
10. Regarding claims 4, 12, and 20, Losh further teaches:
“wherein the first access command comprises data, and wherein the method further comprises requesting to write the data using the first access command.” (e.g., Fig. 2, ¶ 0035, The peripheral driver places the I/O request into … write queue 208…Once the start routine is called, it will try to pull a request…from the write queue 208…An action routine is then called, which delivers the command to the hardware of the storage drive 212 to … write data to the storage drive 212).
11. Regarding claims 5, 13, and 20, Losh further teaches:
“wherein the second access command comprises requesting to read or complete reading data.” (e.g., Fig. 2, ¶ 0035, The peripheral driver places the I/O request into…read queue 206…Once the start routine is called, it will try to pull a request…from the read queue 206… An action routine is then called, which delivers the command to the hardware of the storage drive 212 to … read data from the storage drive 212).
12. Regarding claims 6 and 14, Allison further teaches:
“sending content in the first send queue when in the second send queue does not comprise to-be-sent content.” (e.g., ¶ 0012, read operations typically have priority over write operations, such that the read queue 120 is serviced until all its entries have been processed …at which time one or more entries in the write queue 130 may be processed) .
13. 7Regarding claims 7 and 15, Allison further teaches:
“sending content in the first send queue when a data amount of continuously sent content in the second send queue reaches a preset data amount or when a time for continuously sending content in the second send queue reaches a preset duration.” (e.g., ¶ 0012, read operations typically have priority over write operations, such that the read queue 120 is serviced until all its entries have been processed). The read operation (e.g., read access commands) in read queue have higher priority over write commands in the write queue. The read queue 120 is serviced until all its entries have been processed (e.g., it continuously processed until is empty—i.e., reaches a zero or preset amount of data).
Claims 2-3, 8, 10-11, and 16 are rejected as being unpatentable over Losh in view of Allisson, as applied to claims 1, 9, and 17 above, and further in view of RAMAKRISHNAN et al. “Ramakrishman” (US 20220239594 A1).
14. Regarding claims 2, 10, and 18 Losh in view of Allison teach all limitations included in claims 1, 9, and 17 but does appear to expressly teach while Ramakrishman discloses:
“wherein the first access command and the second access command are remote direct memory access over converged (RDMA) over Converged Ethernet (RoCE) access commands.” (e.g., ¶ 0030, Direct Memory Access (RDMA) over Converged Networks (NVMe/RoCE) (using any version of RoCE) are commonly-used Ethernet-based protocols currently available that enable the connectivity between NVMe-oF initiators and their targets; ¶ 0064, sending data in response to read requests…initiators sending write requests to targets; Fig. 5, ¶ 0100, FIG. 5 an NVMe-oF initiator is shown communicating with an NVMe-oF target…Using NVMe-oF, NVMe-oF initiator 105-1 and NVMe-oF target 105-2 may each have a number of queue pairs …and one (or more) queue pair used for input/output (I/O) purposes)
Disclosures by Losh, Allison and Ramakrishman are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the Memory Input/Output Management taught by Losh to include the request and/or queue priority taught by Allison; furthermore, to include RDMA over Converged Ethernet (RoCE) access disclosed by Ramakrishman.
The motivation for including the priority as taught by paragraph [0011] of Allison is to improve system performance; furthermore, the motivation for including the RDMA over Converged Ethernet (RoCE) access as taught by Ramakrishman is to improve overall efficiency of the target through better (e.g., see par. [0069] of Ramakrishman).
Therefore, it would have been obvious to combine teachings of Ramakrishman and Allison with Losh to obtain the invention as specified in the claim.
15. Regarding claims 3, 11, and 19 Ramakrishman further teaches:
“wherein the first send queue and the second send queue belong to a same send queue pair.” (e.g., ¶ 0033, the target may allow an initiator to open one or more NVMe-oF queue pairs for I/O command submissions. Each NVMe-oF queue pair may offer an independent and parallel network path to the NVMe queues in the storage device). The queue pairs for I/O command submissions represent send queue pair recited in the claim
16. Regarding claims 8 and 16 Allison further teaches:
“configuring the second processing priority to be higher than the first processing priority.” (e.g., ¶ 0012, read operations typically have priority over write operations, such that the read queue 120 is serviced until all its entries have been processed or priority shifts to favor writes).
Ramakrishman discloses: “receiving a connection establishment request for requesting to establish a connection; and in response to the connection establishment request, creating the first send queue and the second send queue,” (e.g., ¶ 0101, When a connection is established between NVMe-oF initiator 105-1 and NVMe-oF target 105-2, NVMe-oF initiator 105-1 and NVMe-oF target 105-2 each use a particular queue pair; ¶ 0037, An NVMe-oF controller may associate an NVMe queue pair with a network connection to create an NVMe-oF queue pair). Ramakrishman describes setting priority for queue pair (e.g., see ¶¶ 0036 and 0068 of Ramakrishman).
Direction OF FUTURE CORRESPONDENCES:
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
18. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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