DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1-3, 11-13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0162666 A1, hereinafter referred as “Kim2666”) in view of Kim et al. (US 2007/0103406 A1, hereinafter referred as “Kim3406”).
Regarding claim 1, Kim2666 discloses a pixel (title discloses pixel circuit) comprising:
a second transistor (T3) having a control electrode connected to a first node (N2) (Fig. 2 and ¶0056 discloses the third transistor T3… may include a gate electrode coupled to a second node N2), a first electrode for receiving a first power voltage (VDDL), and a second electrode connected to a second node (N1) (Fig. 2 and ¶0056 discloses third transistor T3 may be coupled between the first node N1 and the first power line VDDL);
a first transistor (T1) having a gate electrode connected to the second node (N1) (Fig. 2 and ¶0054 discloses first transistor T1 may include a gate electrode coupled to a first node N1), a first electrode for receiving the first power voltage (VDDL) (Fig. 2 and ¶0054 discloses a source electrode coupled to a first power line VDDL),…; and
a light-emitting element (LED) configured to be supplied with a driving current from the first transistor (T1) (Figs. 2, 3B and ¶0073 discloses a driving current Id may flow through the first transistor T1),
wherein a turn-on time point of the second transistor (T3) is determined by a data voltage (Fig. 2 and ¶0060 discloses when the voltage of the second node N2 is reduced to a value that is less than or equal to that of the threshold voltage of the third transistor T3, the third transistor T3 may be turned on; ¶0072, ¶0076 and ¶0094 discloses the voltage of the N2 is based on the magnitude of the second data voltage DAT2i), and
wherein the driving current supplied to the light-emitting element (LED) is configured to be interrupted as the second transistor (T3) is turned on (Fig. 4E and ¶0074-¶0075 discloses when the third transistor T3 is turned on, the first power line VDDL and the first node N1 are electrically connected to each other, and the first node N1 is set to the first power supply voltage VDD. The first power supply voltage VDD may be greater than the threshold voltage of the first transistor T1, and the first transistor T1 may be turned off, [and thus deactivating the light emitting element LED]).
Kim2666 doesn’t disclose a second electrode [of the first transistor] connected to a third node.
However, in the same field of endeavor, Kim3406 discloses a second electrode [of the first transistor] (M21) connected to a third node (Fig. 6 illustrates transistors M21, M23, M34 and M26 connected to a common node).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim2666 so that the voltage of the initialization power source Vint is supplied to the second node N22 (¶0064).
Regarding claim 2, Kim2666 discloses the pixel according to claim 1, further comprising:
a third transistor (T4) having a control electrode connected to a first scan line (SC2i) (Fig. 2 and ¶0057 discloses gate electrode of fourth transistor T4 coupled to a second scan line SC2i), a first electrode connected to the first node (N2) (Fig. 2 and ¶0057 discloses fourth transistor T4 may be coupled to second node N2), and a second electrode connected to a data line (Dj) for supplying the data voltage (Fig. 2 and ¶0057 discloses fourth transistor T4 may be coupled to the j-th data line Dj); and
a first capacitor (C2) having a first electrode connected to a third scan line (SWPL) (Fig. 2 and ¶0060 discloses second capacitor C2 may be coupled between the second node N2 and a first control line SWPL), and a second electrode connected to the first node (N2) (Fig. 2 and ¶0060 discloses second capacitor C2 may be coupled between the second node N2 and a first control line SWPL),
wherein the data voltage is configured to be written to the first node (N2) by the first capacitor (C2) as the third transistor (T4) is turned on (¶0070 discloses as the fourth transistor T4 is turned on, and the data line Dj and the second node N2 may be electrically connected to each other (e.g., refer to FIG. 4C). At this time, the second data voltage DAT2i may have a second voltage level V2).
Regarding claim 3, Kim2666 discloses the pixel according to claim 2, wherein the third transistor (T4) is configured to be turned off during an emission period (P1) (Figs. 3A-3B illustrates the data writing period in which the transistor T4 is turned on doesn’t overlap with the first period P1),
wherein a duty control signal decreasing over time during the emission period (P1) is configured to be supplied from the third scan line (SWPL) (Figs. 3A-3B and ¶0072 discloses the first control line SWPL may supply the first control voltage SWP that is gradually reduced during a first period P1), and
wherein a voltage of the first node (N2) is configured to decrease over time by the first capacitor (C2) in response to the decreasing duty control signal (¶0072 discloses as the first control voltage SWP is variously changed (e.g., varies), the voltage of the second node N2 may also be changed by the coupling of the second capacitor C).
Regarding claim 11, Kim2666 discloses a display device (Fig. 1, display device 10) comprising:
a display panel comprising pixels (Figs. 1-2 and ¶0049 discloses pixel unit 14 includes a plurality of pixels PXij);
a scan driver (14) connected to the display panel through scan lines (SC1 to SCm) (Fig. 1 and ¶0047 discloses scan driver 13 may receive a clock signal, a scan start signal, and/or the like from the timing controller 11, and may generate scan signals to be provided to the scan lines SC1 to SCm);
a data driver (10) connected to the display panel through data lines (D1 to Dn) (Fig. 1 and ¶0046 discloses data driver 12 may generate data voltages to be provided to data lines D1 to Dn); and
a timing controller (11) for receiving image data (¶0045 discloses timing controller 11 may receive gray scale values and control signals for each image frame from an external processor (e.g., a host processor or a host device)), and for controlling driving of the scan driver (14) and the data driver (10) to display an image corresponding to the image data (¶0047 discloses the scan driver 13 may receive a clock signal, a scan start signal, and/or the like from the timing controller 11; and ¶0046 discloses the data driver 12 may generate data voltages to be provided to data lines D1 to Dn using the gray scale values and the control signals),
wherein the pixels (PXij) comprise:
a second transistor (T3) having a control electrode connected to a first node (N2) (Fig. 2 and ¶0056 discloses the third transistor T3… may include a gate electrode coupled to a second node N2), a first electrode for receiving a first power voltage (VDDL), and a second electrode connected to a second node (N1) (Fig. 2 and ¶0056 discloses third transistor T3 may be coupled between the first node N1 and the first power line VDDL);
a first transistor (T1) having a gate electrode connected to the second node (N1) (Fig. 2 and ¶0054 discloses first transistor T1 may include a gate electrode coupled to a first node N1), a first electrode for receiving the first power voltage (VDDL) (Fig. 2 and ¶0054 discloses a source electrode coupled to a first power line VDDL),…; and
a light-emitting element (LED) configured to be supplied with a driving current from the first transistor (T1) (Figs. 2, 3B and ¶0073 discloses a driving current Id may flow through the first transistor T1),
wherein a turn-on time point of the second transistor (T3) is configured to be determined by a data voltage supplied through a data line (Dj) among the data lines (D1 to Dn) (Fig. 2 and ¶0060 discloses when the voltage of the second node N2 is reduced to a value that is less than or equal to that of the threshold voltage of the third transistor T3, the third transistor T3 may be turned on; ¶0072, ¶0076 and ¶0094 discloses the voltage of the N2 is based on the magnitude of the second data voltage DAT2i), and
wherein the driving current supplied to the light-emitting element (LED) is configured to be interrupted as the second transistor (T3) is turned on (Fig. 4E and ¶0074-¶0075 discloses when the third transistor T3 is turned on, the first power line VDDL and the first node N1 are electrically connected to each other, and the first node N1 is set to the first power supply voltage VDD. The first power supply voltage VDD may be greater than the threshold voltage of the first transistor T1, and the first transistor T1 may be turned off, [and thus deactivating the light emitting element LED]).
Kim2666 doesn’t disclose a second electrode [of the first transistor] connected to a third node.
However, in the same field of endeavor, Kim3406 discloses a second electrode [of the first transistor] (M21) connected to a third node (Fig. 6 illustrates transistors M21, M23, M34 and M26 connected to a common node).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim2666 so that the voltage of the initialization power source Vint is supplied to the second node N22 (¶0064).
Regarding claim 12, Kim2666 discloses the display device according to claim 11, wherein the scan lines comprise a first scan line (SC2i), a second scan line (RSTL), and a third scan line (SWPL), wherein the pixels further comprise:
a third transistor (T4) having a control electrode connected to the first scan line (SC2i) (Fig. 2 and ¶0057 discloses gate electrode of fourth transistor T4 coupled to a second scan line SC2i), a first electrode connected to the first node (N2), and a second electrode connected to the data line (Dj) (Fig. 2 and ¶0057 discloses fourth transistor T4 may be coupled to the j-th data line Dj); and
a first capacitor (C2) having a first electrode connected to a third scan line (SWPL) (Fig. 2 and ¶0060 discloses second capacitor C2 may be coupled between the second node N2 and a first control line SWPL), and a second electrode connected to the first node (N2) (Fig. 2 and ¶0060 discloses second capacitor C2 may be coupled between the second node N2 and a first control line SWPL),
wherein the data voltage is configured to be written to the first node (N2) by the first capacitor (C2) as the third transistor (T4) is turned on (¶0070 discloses as the fourth transistor T4 is turned on, and the data line Dj and the second node N2 may be electrically connected to each other (e.g., refer to FIG. 4C). At this time, the second data voltage DAT2i may have a second voltage level V2).
Regarding claim(s) 13, this/these apparatus claim(s) has/have similar limitations as apparatus claim(s) 3, and therefore rejected on similar grounds.
Regarding claim 20, Kim2666 discloses an electronic device (Fig. 1, display device 10) comprising:
a processor for providing input image data (¶0045 discloses timing controller 11 may receive gray scale values and control signals for each image frame from an external processor (e.g., a host processor or a host device)); and
a display device for displaying an image based on the input image data (¶0045 discloses gray scale values that have been rendered or have not been rendered may be provided to the data driver 12), wherein the display device comprises:
a display panel comprising pixels (Figs. 1-2 and ¶0049 discloses pixel unit 14 includes a plurality of pixels PXij);
a scan driver (14) connected to the display panel through scan lines (SC1 to SCm) (Fig. 1 and ¶0047 discloses scan driver 13 may receive a clock signal, a scan start signal, and/or the like from the timing controller 11, and may generate scan signals to be provided to the scan lines SC1 to SCm);
a data driver (10) connected to the display panel through data lines (D1 to Dn) (Fig. 1 and ¶0046 discloses data driver 12 may generate data voltages to be provided to data lines D1 to Dn); and
a timing controller (11) for receiving image data (¶0045 discloses timing controller 11 may receive gray scale values and control signals for each image frame from an external processor (e.g., a host processor or a host device)), and for controlling driving of the scan driver (14) and the data driver (10) to display an image corresponding to the image data (¶0047 discloses the scan driver 13 may receive a clock signal, a scan start signal, and/or the like from the timing controller 11; and ¶0046 discloses the data driver 12 may generate data voltages to be provided to data lines D1 to Dn using the gray scale values and the control signals),
wherein the pixels (PXij) comprise:
a second transistor (T3) having a control electrode connected to a first node (N2) (Fig. 2 and ¶0056 discloses the third transistor T3… may include a gate electrode coupled to a second node N2), a first electrode for receiving a first power voltage (VDDL), and a second electrode connected to a second node (N1) (Fig. 2 and ¶0056 discloses third transistor T3 may be coupled between the first node N1 and the first power line VDDL);
a first transistor (T1) having a gate electrode connected to the second node (N1) (Fig. 2 and ¶0054 discloses first transistor T1 may include a gate electrode coupled to a first node N1), a first electrode for receiving the first power voltage (VDDL) (Fig. 2 and ¶0054 discloses a source electrode coupled to a first power line VDDL),…; and
a light-emitting element (LED) configured to be supplied with a driving current from the first transistor (T1) (Figs. 2, 3B and ¶0073 discloses a driving current Id may flow through the first transistor T1),
wherein a turn-on time point of the second transistor (T3) is configured to be determined by a data voltage supplied through a data line (Dj) among the data lines (D1 to Dn) (Fig. 2 and ¶0060 discloses when the voltage of the second node N2 is reduced to a value that is less than or equal to that of the threshold voltage of the third transistor T3, the third transistor T3 may be turned on; ¶0072, ¶0076 and ¶0094 discloses the voltage of the N2 is based on the magnitude of the second data voltage DAT2i), and
wherein the driving current supplied to the light-emitting element (LED) is configured to be interrupted as the second transistor (T3) is turned on (Fig. 4E and ¶0074-¶0075 discloses when the third transistor T3 is turned on, the first power line VDDL and the first node N1 are electrically connected to each other, and the first node N1 is set to the first power supply voltage VDD. The first power supply voltage VDD may be greater than the threshold voltage of the first transistor T1, and the first transistor T1 may be turned off, [and thus deactivating the light emitting element LED]).
Kim2666 doesn’t disclose a second electrode [of the first transistor] connected to a third node.
However, in the same field of endeavor, Kim3406 discloses a second electrode [of the first transistor] (M21) connected to a third node (Fig. 6 illustrates transistors M21, M23, M34 and M26 connected to a common node).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim2666 so that the voltage of the initialization power source Vint is supplied to the second node N22 (¶0064).
4. Claim(s) 4-10 and 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim2666 in view of Kim3406, in further view of Wang et al. (US 2025/0378783 A1, hereinafter referred as “Wang”) and still in further view of Wei et al. (US 2023/0038017 A1, hereinafter referred as “Wei”).
Regarding claim 4, Kim2666 discloses the pixel according to claim 2, further comprising:
a second capacitor (C1) having a first electrode for receiving the first power voltage (VDDL) (Fig. 2 and ¶0059 discloses first capacitor C1 may be coupled between the first node N1 and the source electrode of the first transistor T1 (e.g., via the first power line VDDL)), and a second electrode connected to the second node (N1) (Fig. 2 and ¶0059 discloses first capacitor C1 may be coupled between the first node N1 and the source electrode of the first transistor T1 (e.g., via the first power line VDDL)).
Kim2666 doesn’t disclose a current source for supplying a constant current; a fourth transistor having a control electrode connected to a second scan line, a first electrode connected to the second node, and a second electrode connected to the third node; and a fifth transistor having a control electrode connected to the first scan line, a first electrode connected to the third node, and a second electrode connected to the current source.
However, in the same field of endeavor, Kim3406 discloses, a first electrode [of the fourth transistor] (M23) connected to the second node (Fig. 6 illustrates transistor M23 connected to node N23), and a second electrode [of the fourth transistor] (M23) connected to the third node (Fig. 6 illustrates transistor M23, M24 and M21 connected to a common node); and… a first electrode [of the fifth transistor] (M24) connected to the third node (Fig. 6 illustrates transistor M23, M24 and M21 connected to a common node).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim2666 so that the voltage of the initialization power source Vint is supplied to the second node N22 (¶0064).
Kim2666 as modified doesn’t disclose a current source for supplying a constant current; a fourth transistor having a control electrode connected to a second scan line; a fifth transistor having a control electrode connected to the first scan line; and a second electrode [of the fifth transistor] connected to the current source.
However, in the same field of endeavor, Wang discloses a fourth transistor (T9) having a control electrode connected to a second scan line (R0) (Fig. 36 and ¶0370 discloses gate electrode of the ninth transistor T9 is electrically connected to the reset terminal R0); and a fifth transistor (T7) having a control electrode connected to the first scan line (G1) (Fig. 36 and ¶0366 discloses gate electrode of the seventh transistor T7 is electrically connected to the first scanning terminal G1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Kim2666 for the purpose of binding the gate signal G1 to control two different elements and thereby reducing the pre-emission driving period.
Kim2666 as modified still doesn’t disclose a current source for supplying a constant current; and a second electrode [of the fifth transistor] connected to the current source.
However, in the same field of endeavor, Wei discloses a current source for supplying a constant current (¶0070 discloses the display panel 100 further includes a power source (not illustrated) to supply the above-described voltage signal, which may be a voltage source or a current source…; the power source is configured to supply the … the initialization signal Vint, etc., to the pixel unit 101 through … the first initialization signal line 212); a second electrode [of the fifth transistor] (T7) connected to the current source (Fig. 1, ¶0070 and ¶0079 discloses second reset transistor T7 is electrically connected with the first initialization signal line 212 through a third connection electrode 31c).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Kim2666 so that the initialization voltage is a function of the Vth rather than a fixed external voltage.
Regarding claim 5, Kim2666 doesn’t disclose the pixel according to claim 4, wherein the fourth transistor and the fifth transistor are configured to be turned on, and the gate electrode and the second electrode of the first transistor are configured to be electrically connected to each other, during a first period in a non-emission period.
However, in the same field of endeavor, Kim3406 discloses wherein the fourth transistor (M23) and the fifth transistor (M24) are configured to be turned on (Figs. 6-7 illustrate the third transistor M23 and the fourth transistor M24 are turned on simultaneously), and the gate electrode and the second electrode of the first transistor are configured to be electrically connected to each other (¶0057 discloses The third transistor M23 is turned on when the first scan signal is supplied to the first scan line S1n. When the third transistor M23 is turned on, the first transistor M21 serves as a diode), during a first period in a non-emission period (Fig. 7 and ¶0067 discloses periods T2 and T3 occurring outside of the emission period T5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim2666 so that the driving transistor turns on according to the data voltage during the emission period irrespective of the threshold voltage.
Regarding claim 6, Kim2666 doesn’t disclose the pixel according to claim 5, wherein the constant current is configured to be supplied to a drain of the first transistor, and wherein a voltage at which a threshold voltage of the first transistor is compensated is configured to be written to the second node by the second capacitor.
However, in the same field of endeavor, Kim3406 discloses wherein the [initialization voltage] (Vint) is configured to be supplied to a drain of the first transistor (M21) (Fig. 6 and ¶0064 discloses when the third and fourth transistors M23, M24 are turned on together, the voltage of the initialization power source Vint is supplied to the [drain of the transistor M21]), and wherein a voltage at which a threshold voltage of the first transistor (M11) is compensated is configured to be written to the second node by the second capacitor (C1st) (Fig. 3 and ¶0036 discloses when the scan signal is supplied to the (n-1)th scan line Sn-1, the fourth transistor M14 is turned on to change the voltages of the terminal of the storage capacitor C1st coupled to the fourth transistor M14 and the gate electrode of the first transistor M11 to the voltage of the initialization power source Vint.).
Kim2666 as modified doesn’t disclose wherein the constant current is configured to be supplied...
However, in the same field of endeavor, Wei discloses wherein the constant current is configured to be supplied (¶0070 discloses the display panel 100 further includes a power source (not illustrated) to supply the above-described voltage signal, which may be a voltage source or a current source…; the power source is configured to supply the … the initialization signal Vint, etc., to the pixel unit 101 through … the first initialization signal line 212)…
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Kim2666 so that the initialization voltage is a function of the Vth rather than a fixed external voltage.
Regarding claim 7, Kim2666 doesn’t disclose the pixel according to claim 5, wherein the fourth transistor and the fifth transistor are configured to be turned off during an emission period.
However, in the same field of endeavor, Kim3406 discloses wherein the fourth transistor (M23) and the fifth transistor (M24) are configured to be turned off during an emission period (T5) (Fig. 7 and ¶0067 discloses periods T2 and T3 occurring outside of the emission period T5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim2666 so that the driving transistor turns on according to the data voltage during the emission period irrespective of the threshold voltage.
Regarding claim 8, Kim2666 doesn’t disclose the pixel according to claim 4, further comprising a sixth transistor having a control electrode connected to an emission control line, a first electrode connected to the third node, and a second electrode connected to an anode electrode of the light-emitting element.
However, in the same field of endeavor, Kim3406 discloses further comprising a sixth transistor (M26) having a control electrode connected to an emission control line (En) (Fig. 6 and a gate electrode of the sixth transistor M26 is coupled to the emission control line En), a first electrode connected to the third node (Fig. 6 and ¶0060 discloses first electrode of the sixth transistor M26 is coupled to the second electrode of the first transistor M21), and a second electrode connected to an anode electrode of the light-emitting element (OLED) (Fig. 6 and ¶0060 discloses a second electrode of the sixth transistor M26 is coupled to the anode electrode of the OLED).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim2666 for the purpose of absolute suppression of unintended emission.
Regarding claim 9, Kim2666 doesn’t disclose the pixel according to claim 8, wherein the sixth transistor is configured to be turned off during a non-emission period, and is configured to be turned on during an emission period.
However, in the same field of endeavor, Kim3406 discloses wherein the sixth transistor (M26) is configured to be turned off during a non-emission period (Fig. 7 illustrates emission control signal En is off during the period outside of the emission period T5), and is configured to be turned on during an emission period (Fig. 7 and ¶0068 discloses the first transistor M21 supplies current corresponding to the value of the voltage applied to the second node N22 to the OLED through the sixth transistor M26 during the fifth period T5 so that light of controlled brightness is generated by the OLED).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim2666 for the purpose of absolute suppression of unintended emission.
Regarding claim 10, Kim2666 discloses the pixel according to claim 8, wherein the first transistor (T1) is configured to be turned off at the turn-on time point of the second transistor (T3) during an emission period (P1) (Fig. 4E and ¶0075 discloses When the third transistor T3 is turned on, the first power line VDDL and the first node N1 are electrically connected to each other… the first transistor T1 may be turned off), and wherein the driving current to the light-emitting element (LED) is configured to be interrupted as the first transistor (T1) is turned off (Figs. 2, 4E, ¶0073-¶0074 and ¶0076 discloses when the third transistor T3 is turned [on] by a reduction in the voltage of the second node N2, the driving current Id no longer flows through the light emitting element LED, and thus, the light emitting element LED does not emit light).
Regarding claim(s) 14-19, this/these apparatus claim(s) has/have similar limitations as apparatus claim(s) 4-9, respectively, and therefore rejected on similar grounds.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYANK J SHAH whose telephone number is (571)270-3732. The examiner can normally be reached on 10:00 - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached on 5712727671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRIYANK J SHAH/Primary Examiner, Art Unit 2621