DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-3 and 15-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Regarding claims 1-3 and 15-20, the phrase “a terminal of the second transistor” in Claim 1 and the phrase “the terminal of the first transistor” in claim 15 lack proper specification of which multi-terminal node (e.g., source or drain) is being connected, leaving the circuit topology ambiguous. A person having ordinary skill in the art would not know the objective boundary of the claim because it is entirely unclear whether the selection transistor is arranged in series with the second transistor or in a parallel secondary routing path. Without identifying the precise nodes, the claims fail to define the exact metes and bounds of the circuit.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tanada (US 2001/0048106, hereinafter "Tanada").
With respect to Claim 4, Tanada teaches a display device comprising:
a data driver comprising a first channel configured to output a first data voltage for a first color, and a second channel configured to output a second data voltage for a second color (Tanada: Para. [0104], "The structure shown in FIG. 6A can readily be applied to a color electronic device having pixels for three colors of R, G and B.... Signals of R and G are inputted to a source signal line 635");
a first data line connected to the first channel and configured to transmit the first data voltage, and a second data line configured to transmit the second data voltage (Tanada: Para. [0104], "signals of B and R are inputted to a source signal line 645"); and
first light-emitting elements connected to pixel circuits (Tanada: Para. [0080], "The pixel A has a... first EL element 105").
Tanada further teaches pixel circuits arranged in rows, connected to the data lines, and positioned at sides of the data lines (Tanada: Para. [0100], "Two pixels are put by the side of a source signal line 610 with a pixel A placed to the left and a pixel B to the right").
Tanada fails to expressly disclose the specific arrangement of a first-first pixel circuit and a first-second pixel circuit arranged in a first row and positioned at a first side of the first data line; and a first-third pixel circuit and a first-fourth pixel circuit arranged in a second row and positioned at a second side of the first data line.
However, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the spatial arrangement of the pixel circuits in Tanada to group multiple pixel circuits on a first side in a first row and on a second side in a second row. The motivation to do so would be to optimize routing traces and sub-pixel geometries to further maximize the aperture ratio and accommodate specific color filter patterns (e.g., PenTile or staggered layouts), which is a routine and predictable variation of Tanada's shared-data-line architecture.
With respect to Claim 5, Tanada teaches the display device of claim 4, further comprising pixel circuits connected to a second data line and second light-emitting elements (Tanada: Para. [0081], "When the electronic device has m.times.k pixels, it has m/2 source signal lines and k gate signal lines"). While Tanada fails to expressly detail the exact grouping of second-first through second-fourth pixel circuits mirroring the first data line, it would have been obvious to a person of ordinary skill in the art to identically scale the staggered arrangement established in Claim 4 across adjacent columns to form a uniform display matrix.
With respect to Claim 6, Tanada teaches the display device of claim 5, further comprising a first scan line in the first row... and a second scan line in the second row (Tanada: Para. [0103], "The rest of the gate signal lines are selected one by one and now the gate signal line on the last row is selected"). It would have been obvious to one of ordinary skill in the art to connect these sequential scan lines to the staggered pixel circuits of Claims 4 and 5 to enable predictable, sequential row-by-row data writing.
With respect to Claim 7, Tanada teaches the display device of claim 5, further comprising a third data line configured to transmit a third data voltage for a third color and third light-emitting elements (Tanada: Para. [0104], "signals of G and B are inputted to a source signal line 655"). Modifying the array to include the third-first through third-fourth pixel circuits would have been an obvious design choice to a person of ordinary skill in the art to accommodate the third primary color required in a full-color RGB display matrix.
With respect to Claim 8, Tanada teaches the display device of claim 7, wherein the first light-emitting elements and the second light-emitting elements are respectively arranged in a same one of the rows as a corresponding one of the pixel circuits connected thereto (Tanada: Fig. 6A-B, standard alignment of pixels and elements). Tanada fails to expressly disclose wherein the third light-emitting elements are arranged in a different one of the rows from their corresponding pixel circuits. However, it would have been obvious to one of ordinary skill in the art to modify the apparatus of Tanada to offset the third light-emitting elements into a different row. The motivation for this modification is to accommodate different physical sizes for different color sub-pixels based on their varying light emission efficiencies (Tanada: Para. [0104], "The voltage-luminance characteristic of the EL element varies depending upon which color of light out of R, G and B the element emits").
With respect to Claim 9, Tanada teaches the display device of claim 7, wherein the second light-emitting elements are respectively arranged in a same one of the rows as a corresponding one of the pixel circuits connected thereto (Tanada: Para. [0080], "The pixel A has a first switching TFT 101... a first EL element 105").
With respect to Claim 10, Tanada teaches the display device of claim 7, wherein the data driver further comprises a third channel configured to output the third data voltage, and connected to the third data line (Tanada: Para. [0104], "pixels for three colors of R, G and B").
With respect to Claim 11, Tanada teaches the display device of claim 4, further comprising a second-first data line configured to transmit the second data voltage; a second-first pixel circuit and a second-second pixel circuit arranged in the first row, connected to the second-first data line, and positioned with the second-first data line therebetween; and second-first light-emitting elements (Tanada: Para. [0081], "Two adjacent pixels with a source signal line interposed therebetween are electrically connected to the source signal line"). To the extent Tanada does not explicitly spell out the specific nomenclature of "second-first data line," "second-second data line," and their associated pixel groupings, it would have been obvious to one of ordinary skill in the art to duplicate and scale the shared-line architecture across the entire active matrix area. The motivation would be to provide a complete, functioning high-resolution display panel with uniform multiplexing logic.
With respect to Claim 12, Tanada teaches the display device of claim 11, further comprising a first scan line in the first row... and a second scan line in the second row (Tanada: Para. [0088], "In an address (writing) period, gate signal lines are selected one by one starting from the line on the first row").
With respect to Claim 13, Tanada teaches the display device of claim 11, further comprising a second-second data line configured to transmit the second data voltage; a second-third pixel circuit and a second-fourth pixel circuit arranged in the second row, connected to the second-second data line, and positioned with the second-second data line therebetween; and second-second light-emitting elements (Tanada: Para. [0081], "When the electronic device has m.times.k pixels, it has m/2 source signal lines and k gate signal lines").
With respect to Claim 14, Tanada teaches the display device of claim 13, wherein the data driver further comprises a second-first channel configured to output the second data voltage, and connected to the second-first data line; and a second-second channel configured to output the second data voltage, and connected to the second-second data line (Tanada: Para. [0083], "A source signal line side driver circuit 200 has a plurality of stages").
Claims 1-3 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tanada (US 2001/0048106, hereinafter "Tanada") in view of Kim et al. (US 2022/0084472, hereinafter "Kim").
With respect to Claim 1, Tanada teaches a display panel comprising:
a data line configured to transmit a data voltage for a color (Tanada: Para. [0025], one source signal line 110 is provided between two adjacent pixels so that a pixel A and a pixel B share the one source signal line);
a first pixel circuit and a second pixel circuit connected to the data line and positioned at a side of the data line (Tanada: Para. [0080], [0100], Fig. 6B, pixel A and pixel B); and
one or more light-emitting elements connected to the first pixel circuit and the second pixel circuit (Tanada: Para. [0080], [0100], first EL element 105 and second EL element 106),
wherein the first pixel circuit and the second pixel circuit comprise:
a first transistor configured to control a driving current flowing to a corresponding light-emitting element of the one or more light-emitting elements (Tanada: Para. [0080], [0100], Fig. 1B, first EL driver TFT 103 and second EL driver TFT 104);
a second transistor configured to transmit the data voltage to a first terminal of the first transistor based on a scan signal (Tanada: Para. [0080], [0100], first switching TFT 101 and second switching TFT 102); and
a selection transistor configured to connect the first terminal of the first transistor and a terminal of the second transistor based on a selection signal (Tanada: Para. [0100], Fig. 6b, pixel selecting portion 613 is composed of an n-channel TFT 615, a p-channel TFT 616 and a pixel selecting signal 614)
Tanada fails to expressly disclose:
a third transistor configured to connect a second terminal and a gate of the first transistor based on the scan signal; and the specific topological arrangement where the selection transistor connects the first terminal of the first transistor and a terminal of the second transistor.
However, Kim discloses:
a third transistor configured to connect a second terminal and a gate of the first transistor based on the scan signal (Kim: Abstract, a third transistor configured to diode-connect the first transistor); and the specific topological arrangement where a selection transistor connects the first terminal of the first transistor and a terminal of the second transistor (Kim: Abstract, a second transistor configured to transfer a data voltage to a first node).
Therefore, it would be obvious to one of ordinary skill in the art to modify the apparatus, as taught by Tanada, to incorporate the diode-connecting third transistor and series selection topology, as taught by Kim, in order to compensate for threshold voltage variations of the driving transistor (Kim: Para. [0012]).
With respect to Claim 2, the combination of Tanada as modified by Kim teaches the display panel of claim 1, wherein the data voltage is configured to be written to the first pixel circuit in a period that the scan signal is at an activation level and the selection signal is at a logic low level,
wherein the data voltage is configured to be written to the second pixel circuit in a period that the scan signal is at the activation level and the selection signal is at a logic high level,
wherein the selection transistor of the first pixel circuit comprises a P-type Metal Oxide Semiconductor (PMOS) transistor, and
wherein the selection transistor of the second pixel circuit comprises an N-type Metal Oxide Semiconductor (NMOS) transistor (Tanada: Para. [0100], Fig. 6B, a Hi signal is inputted to the pixel selecting signal line 614 to turn the n-channel TFT 615 conductive to write a signal in pixel A, and a LO signal is inputted to turn the p-channel TFT 616 conductive to write a signal in pixel B).
With respect to Claim 3, the combination of Tanada as modified by Kim teaches the display panel of claim 1, wherein the first pixel circuit and the second pixel circuit further comprise:
a storage capacitor configured to store a signal of the gate of the first transistor;
a fourth transistor configured to initialize the storage capacitor based on an initialization gate signal;
a fifth transistor configured to transmit a power voltage to the first terminal of the first transistor based on an emission signal;
a sixth transistor configured to connect the second terminal of the first transistor
and a terminal of the corresponding light-emitting element based on the emission signal; and
a seventh transistor configured to initialize the corresponding light-emitting element based on a bypass gate signal (Kim: Abstract, Para. [0031], a fourth transistor configured to transfer an initialization voltage, a fifth transistor configured to transfer a reference voltage, a sixth transistor configured to couple a drain of the first transistor and an anode of an organic light emitting diode.)
With respect to Claim 15, this claim depends on claim 4 and further recites the internal pixel circuit transistors (the first, second, third, and selection transistors). This claim is rejected under 35 U.S.C. 103 for the same reasons of obviousness as Claim 1 and Claim 2, as it merely duplicates the core pixel circuit and PMOS/NMOS limitations applied to the display device of claim 4.
With respect to Claim 16, this claim is rejected under 35 U.S.C. 103 for the same reasons of obviousness as Claim 2. Claim 16 merely duplicates the activation timing and complementary PMOS/NMOS selection transistor limitations applied to the display device of claim 15.
With respect to Claim 17, this claim depends on claim 4 and further recites the first, second, and selection transistors. This is a sub-combination of the components rejected in Claim 1. Claim 17 is rejected under 35 U.S.C. 103 for the same reasons of obviousness as Claim 1.
With respect to Claim 18, this claim is rejected under 35 U.S.C. 103 for the same reasons of obviousness as Claim 2. Claim 18 merely duplicates the logic high/low activation timing applied to the display device of claim 17. While Tanada fails to teach the exact asymmetrical logic sequence where data is written to both circuits in a high period and to one in a low period, altering the complementary toggling sequences for staggered data writing is a well-known multiplexing design choice to one of ordinary skill in the art (Tanada: Para. [0082], "in a gate signal line selecting period, a signal is inputted to the pixel selecting portion 113 in the former half thereof to write the signal only in the pixel A and then a signal is again inputted to the pixel selecting portion in the latter half thereof").
With respect to Claim 19, this claim is rejected under 35 U.S.C. 103 for the same reasons of obviousness as Claim 1. Claim 19 merely duplicates the core pixel circuit limitations applied to an “electronic apparatus.” The additional limitations of a processor and a data driver are standard display system components as expressly disclosed by Tanada (Tanada: Para. [0249], Fig. 23F).
With respect to Claim 20, this claim is rejected under 35 U.S.C. 103 for the same reasons of obviousness as Claim 2. Claim 20 merely duplicates the activation timing and complementary PMOS/NMOS selection transistor limitations applied to the electronic apparatus of claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN EARLES whose telephone number is (571)272-4628. The examiner can normally be reached on Monday - Thursday at 7:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached on 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRYAN EARLES/Primary Examiner, Art Unit 2625
Prosecution Insights