DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been examined.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(a)-(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application claims priority to U.S. Application 18/400,294 (now US Patent 12,436,771), filed December 29, 2023.
Information Disclosure Statement
The Applicant's submission of the Information Disclosure Statement dated August 6, 2025 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending. A copy of the PTOL-1449 initialed and dated by the Examiner is attached to the instant office action.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use the word “means” and are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Such claim limitation(s) is/are: means for performing in claim 11—limited to shift/logical circuit 126 disclosed at Figure 1 and related description.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims of U.S. Patent No. 12,436,771. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the reference patent anticipate those of the instant application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8, 10-15, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent No. 12,217,060 by Spadini et al. (hereinafter referred to as “Spadini”).
Regarding claims 1, 11, and 12, taking claim 1 as representative, Spadini discloses:
a shift/logical circuit of a processor-based device, configured to perform a shift operation and a subsequent logical operation in a single processor clock cycle, wherein the shift operation and the subsequent logical operation correspond to one or more instructions to perform the shift operation and the subsequent logical operation (Spadini discloses, at Figure 5 and related description, an execution circuit, which discloses a shift/logical circuit. The circuit is configured to perform a first operation followed by a second operation. As disclosed at Figure 8 and related description, the first operation can be a bitwise shift and the second operation can be an AND operation. As disclosed at col. 2, lines 34-42, two instructions to implement a simple function can be implemented in a single cycle.).
Regarding claims 2 and 13, taking claim 2 as representative, Spadini, as modified, discloses the elements of claim 1, as discussed above. Spadini also discloses:
the shift/logical circuit is configured to perform the shift operation and the subsequent logical operation in the single processor clock cycle responsive to an instruction processing circuit of the processor-based device detecting the one or more instructions in an instruction stream (Spadini discloses, at Figure 5 and related description, a pair detector circuit that detects the instructions).
Regarding claims 3 and 14, taking claim 3 as representative, Spadini discloses the elements of claim 1, as discussed above. Spadini also discloses:
the instruction processing circuit is configured to detect the one or more instructions by being configured to identify a shift instruction and a subsequent logical instruction that is adjacent to the shift instruction in the instruction stream (Spadini discloses, at col. 12, lines 25-29, the instructions are consecutive.).
Regarding claims 4 and 15, taking claim 4 as representative, Spadini discloses the elements of claim 1, as discussed above. Spadini also discloses:
the instruction processing circuit is configured to detect the one or more instructions by being configured to: determine that a first destination register of the shift instruction and a second destination register of the subsequent logical instruction are the same (Spadini discloses, at Figure 8 and related description, the destination of the first instruction and the second instruction is the same.); and
determine that the first destination register of the shift instruction is a source register for the subsequent logical instruction (Spadini discloses, at Figure 8 and related description, the destination of the first instruction is a source for the second instruction.).
Regarding claims 8 and 19, taking claim 8 as representative, Spadini discloses the elements of claim 1, as discussed above. Spadini also discloses:
perform the shift operation by being configured to perform a right shift operation using a barrel shifter circuit of the shift/logical circuit (Spadini discloses, at Figure 3 and related description, using barrel shifters in the context of division, which discloses right shifting.).
Regarding claim 10, Spadini, as modified, discloses the elements of claim 1, as discussed above. Spadini also discloses:
integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter (Spadini discloses, at Figure 13 and related description, a computer.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Spadini in view of US Publication No. 2005/0198474 by Nancekievill et al. (hereinafter referred to as “Nancekievill”).
Regarding claims 5 and 16, taking claim 5 as representative, Spadini, as modified, discloses the elements of claim 1, as discussed above. Spadini also discloses:
the instruction processing circuit is configured to detect the one or more instructions by being configured to identify a logical instruction …shift operation (Spadini discloses, at Figure 5 and related description, a pair detector circuit that detects logical and shift instructions.).
Spadini does not explicitly disclose the aforementioned shift operation is embedded.
However, in the same field of endeavor (e.g., processing) Nancekievill discloses:
an embedded shift operation (Nancekievill discloses, at Figure 2A and related description, a bit field extraction instruction that includes a shift operation, which discloses an embedded shift.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Spadini to include embedded shifts, as disclosed by Nancekievill because such “operations enable a wide range of useful data manipulation operations.” See Nancekievill, ¶ [0007].
Claims 6, 7, 17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Spadini.
Regarding claims 6 and 17, taking claim 6 as representative, Spadini, as modified, discloses the elements of claim 1, as discussed above. Spadini also discloses:
perform the shift operation and the subsequent logical operation in the single processor clock cycle by being configured to apply a logical AND mask to a final …stage of the shift/logical circuit (Spadini discloses, at Figure 5 and related description, applying masking after performing an operation, which discloses applying a logical AND mask to a final stage of the shift/logical circuit.).
Spadini does not explicitly disclose the aforementioned final stage is a final multiplexer stage.
However, Spadini discloses, e.g., at Figure 3 and related description, barrel shifters and multiplexers. It would have been obvious to implement the shift operations using a barrel shifter comprised of multiplexers because such circuitry is well-known to enable fast data manipulation.
Regarding claims 7 and 18, taking claim 7 as representative, Spadini, as modified, discloses the elements of claim 1, as discussed above. Spadini also discloses:
perform the shift operation and the subsequent logical operation in the single processor clock cycle by being configured to apply …[a logical] circuit following a final … stage of the shift/logical circuit.
Spadini does not explicitly disclose the logical circuit is OR/XOR and the aforementioned final stage is a final multiplexer stage.
However, Spadini discloses, e.g., at Figure 4 and related description, OR/XOR circuitry. It would have been obvious to use OR/XOR circuitry because OR and XOR are fundamental logic operations that can be useful in enabling a wide range of logical operations.
Spadini also discloses, e.g., at Figure 3 and related description, barrel shifters and multiplexers. It would have been obvious to implement the shift operations using a barrel shifter comprised of multiplexers because such circuitry is well-known to enable fast data manipulation.
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Spadini in view of US Patent No. 4,829,460 by Ito (hereinafter referred to as “Ito”).
Regarding claims 9 and 20, taking claim 9 as representative, Spadini, as modified, discloses the elements of claim 1, as discussed above. Spadini also discloses:
the shift/logical circuit is configured to perform the shift operation by being configured to perform a …shift operation using a barrel shifter circuit of the shift/logical circuit (Spadini discloses, at Figure 3 and related description, using barrel shifters.).
Spadini does not explicitly disclose the aforementioned shift is a left shift and performing the left shift by reversing an input value; performing, using the barrel shifter circuit of the shift/logical circuit, a right shift operation on the input value; and reverse the result of the right shift operation.
However, in the same field of endeavor (e.g., bit manipulation) Ito discloses:
performing a left shift by reversing, shifting right, then reversing (Ito discloses, at col. 2, lines 7-48, reversing input data, shifting right, and reversing the shifted data to perform the equivalent left shift.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Spadini to include the shifting mechanism of Ito in order to provide relatively small and fast circuitry for bit manipulation. See Ito, col. 1, lines 30-47.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 5729482 by Worrell discloses left shifting and right shifting, single cycle rotate and mask.
US 20140040604 by Ould discloses masked packed rotate.
US 4569016 by Hao discloses single cycle rotate and insert with mask (AND operation).
US 20190065145 by Robinson discloses barrel shifting, right, left, and reverse.
US 5265259 by Satou discloses barrel shifting, right, left, and reverse.
US 20180129498 by Levison discloses fusion.
US 5805913 by Guttag discloses shift and mask.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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