Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendments and Arguments
Amendments and arguments filed on 06/25/2026 have been fully considered and are not found to place the application in a condition for allowance. According to the newly provided limitation a search was performed based on which a new reference is found to teach the limitations regarding changing the emission time during the holding cycle. Accordingly, arguments regarding the independent claims and dependent claims 4-5, 7, 12-13 and 17-18 are not persuasive because such limitations would have been obvious based on the teachings of Chung in view of the new reference (see the following action for more details).
Regarding claims 3 and 16, the Office maintains that Chung teaches the limitations. The applicant asserts “Chung does not disclose increasing or otherwise varying the bias voltage between individual holding cycles”. Such a limitation is not provided in the claim language. The Office maintains that Chung teaches that when the holding cycle number of the present holding cycle is equal to or greater than the predetermined holding cycle reference number, the display panel driver is configured to increase a bias voltage applied to a driving switching element of the pixel to be greater than a reference bias voltage (fig. 7, see V1 levels, ¶ 132-133). Specifically, after a certain number of holding cycles have passed a bias voltage such as V1 is increased. While further clarifying limitations may provide a distinction between “a bias voltage” and V1 of Chung, such limitations are absent from the claims. Accordingly, Chung is found to teach such limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8-11, 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al., US 2023/0088459 A1, hereinafter “Chung”, in view of Noh et al., US 2020/0193915 A1, hereinafter “Noh”.
Regarding claim 1, Chung teaches a display apparatus (fig. 1, element 100, ¶ 28) comprising: a display panel (fig. 1, element 110, ¶ 28) including a pixel (fig. 1, element P, ¶ 28); and a display panel driver including a gate driver (fig. 1, element 130, ¶ 28), a data driver (fig. 1, element 140, ¶ 28), and an emission driver (fig. 1, element 150, ¶ 28), in which the gate driver, the data driver, and the emission driver are configured to generate a gate signal, a data voltage, and an emission signal respectively (see ¶ 28), and to provide the gate signal, the data voltage, and the emission signal to the display panel (¶ 28), wherein the display panel driver is further configured to: determine whether a driving cycle in a driving sequence is a writing cycle or a holding cycle (¶ 102), in which, during the writing cycle, the display panel is configured to receive the data voltage and write the data voltage into the pixel (fig. 3A-3J, specifically fig. 3F, ¶ 78), and to drive a light emitting element of the pixel to emit light based on the received data voltage (fig. 3K, ¶ 85), and during the holding cycle, the display panel is configured to drive the light emitting element of the pixel to emit light based on the data voltage stored in the pixel (fig. 4A-4C, ¶ 89); determine a holding cycle number of a present holding cycle when holding cycles are repeated in the driving sequence (¶ 105); and determine an emission off time based on the holding cycle number of the present holding cycle by adjusting at least one of an end point of an off duration of the emission signal and a start point of the off duration of the emission signal according to a setting value (¶ 135, see W1/W2 for example).
Chung does not specifically teach that when the holding cycles are repeated in the driving sequence between two adjacent writing cycles, at least one of the holding cycles has a light emission time that differs from a light emission time of another one of the holding cycles.
Noh, however, teaches that when the holding cycles are repeated in the driving sequence between two adjacent writing cycles, at least one of the holding cycles has a light emission time that differs from a light emission time of another one of the holding cycles (fig. 6, ¶ 75).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Chung in view of Noh. The references teach display devices with hold periods for driving the display device at different refresh frequencies. Noh further teaches that by modifying the length of the emission time “luminance deterioration and an occurrence of a flicker in the variable frame mode may be reduced or prevented” (see ¶ 76). Accordingly, one would have been motivated to make such a combination in order to achieve a higher quality display device having improved luminance characteristics.
Regarding claim 14, Chung teaches a method of driving a display apparatus (fig. 1, element 100, ¶ 28), the method comprising: determining whether a driving cycle in a driving sequence is a writing cycle or a holding cycle (¶ 102), in which, during the writing cycle, the display apparatus is configured to generate a data voltage and write the data voltage into a pixel (fig. 3A-3J, specifically fig. 3F, ¶ 78), and to drive a light emitting element of the pixel to emit light based on the received data voltage (fig. 3K, ¶ 85), and during the holding cycle, the display apparatus is configured to drive the light emitting element of the pixel to emit light based on the data voltage stored in the pixel (fig. 4A-4C, ¶ 89); determining a holding cycle number of a present holding cycle when holding cycles are repeated in a driving sequence (¶ 105); determining an emission off time based on the holding cycle number of a present holding cycle by adjusting at least one of an end point of an off duration of an emission signal and a start point of the off duration of the emission signal according to a setting value; and generating the emission signal based on the emission off time and the setting value, and providing the emission signal to the pixel (¶ 135, see W1/W2 for example).
Chung does not specifically teach that when the holding cycles are repeated in the driving sequence between two adjacent writing cycles, at least one of the holding cycles has a light emission time that differs from a light emission time of another one of the holding cycles.
Noh, however, teaches that when the holding cycles are repeated in the driving sequence between two adjacent writing cycles, at least one of the holding cycles has a light emission time that differs from a light emission time of another one of the holding cycles (fig. 6, ¶ 75).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Chung in view of Noh. The references teach display devices with hold periods for driving the display device at different refresh frequencies. Noh further teaches that by modifying the length of the emission time “luminance deterioration and an occurrence of a flicker in the variable frame mode may be reduced or prevented” (see ¶ 76). Accordingly, one would have been motivated to make such a combination in order to achieve a higher quality display device having improved luminance characteristics.
Regarding claim 20, Chung teaches an electronic apparatus (fig. 1, element 100, ¶ 28) comprising: a processor (fig. 1, element 120, ¶ 29 and/or fig. 6C, element 210, ¶ 100) configured to output input image data (RGB data) and an input control signal (¶ 100-101 flags 211 and 212); a display panel (fig. 1, element 110, ¶ 28) including a pixel (fig. 1, element P, ¶ 28); and a display panel driver including a gate driver (fig. 1, element 130, ¶ 28), a data driver (fig. 1, element 140, ¶ 28), and an emission driver (fig. 1, element 150, ¶ 28), in which the gate driver, the data driver, and the emission driver are configured to generate a gate signal, a data voltage and an emission signal respectively, and to provide the gate signal, the data voltage, and the emission signal to the pixel (¶ 28), wherein the display panel driver is further configured to: determine whether a driving cycle in a driving sequence is a writing cycle or a holding cycle (¶ 102), in which, during the writing cycle, the display panel is configured to receive the data voltage, write the data voltage into the pixel (fig. 3A-3J, specifically fig. 3F, ¶ 78), and to drive a light emitting element of the pixel to emit light based on the received data voltage (fig. 3K, ¶ 85), and during the holding cycle, the display panel is configured not to receive the data voltage, and to drive the light emitting element of the pixel to emit light based on the data voltage stored in the pixel (fig. 3K, ¶ 85); determine a holding cycle number of a present holding cycle when holding cycles are repeated in the driving sequence (¶ 105); and determine an emission off time based on the holding cycle number of the present holding cycle by adjusting at least one of an end point of an off duration of the emission signal and a start point of the off duration of the emission signal according to a setting value (¶ 135, see W1/W2 for example), wherein the display panel driver is further configured to determine whether the driving cycle is the writing cycle or the holding cycle based on the input control signal from the processor (¶ 100-102).
Chung does not specifically teach that when the holding cycles are repeated in the driving sequence between two adjacent writing cycles, at least one of the holding cycles has a light emission time that differs from a light emission time of another one of the holding cycles.
Noh, however, teaches that when the holding cycles are repeated in the driving sequence between two adjacent writing cycles, at least one of the holding cycles has a light emission time that differs from a light emission time of another one of the holding cycles (fig. 6, ¶ 75).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Chung in view of Noh. The references teach display devices with hold periods for driving the display device at different refresh frequencies. Noh further teaches that by modifying the length of the emission time “luminance deterioration and an occurrence of a flicker in the variable frame mode may be reduced or prevented” (see ¶ 76). Accordingly, one would have been motivated to make such a combination in order to achieve a higher quality display device having improved luminance characteristics.
Regarding claims 2 and 15, Chung teaches that when the holding cycle number of the present holding cycle is equal to or greater than a predetermined holding cycle reference number, the display panel driver is configured to decrease the emission off time by advancing the end point of the off duration of the emission signal and/or by delaying the start point of the off duration of the emission signal according to the setting value (fig. 7, note that at R0 of 2set the emission off time has been reduced).
Regarding claims 3 and 16, Chung teaches that when the holding cycle number of the present holding cycle is equal to or greater than the predetermined holding cycle reference number, the display panel driver is configured to increase a bias voltage applied to a driving switching element of the pixel to be greater than a reference bias voltage (fig. 7, see V1 levels, ¶ 132-133).
Regarding claims 4 and 17, Chung does not specifically teach that when the setting value is a first value, the display panel driver is configured to advance the end point of the off duration of the emission signal to decrease the emission off time, and when the setting value is a second value, the display panel driver is configured to delay the start point of the off duration of the emission signal to reduce the emission off time.
Chung, however, clearly teaches that the pulse width of the emission signal may be modified. In other words, according to a setting value such as 100 micro seconds, the end point and or the starting point are advanced and or delays respectively in order to change the pulse width of the emission signal (see fig. 7, ¶ 135).
Noh, further, teaches that when the holding cycles are repeated in the driving sequence between two adjacent writing cycles, at least one of the holding cycles has a light emission time that differs from a light emission time of another one of the holding cycles (fig. 6, ¶ 75).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Chung. Chung teaches that the pulse width of the emission signal may be changed in a display panel. Chung further teaches that “the pulse width is not limited thereto and may be changed according to the design” (see ¶ 135). Noh further teaches changing the off period of the emission signal (see ¶ 75-76). Accordingly, one would have been motivated to modify the pulse width of Chung by modifying the start and/or end points of the pulse width, thereby changing the length of the pulse width (as also performed by Chung), “so that the fine luminance deviation can be additionally compensated” (see ¶ 135).
Regarding claims 5 and 18, Chung teaches that when the setting value is a third value, the display panel driver is configured to advance the end point of the off duration of the emission signal and to delay the start point of the off duration of the emission signal to reduce the emission off time (see W2 at R0 of 2set compared to W1 at R0 of 1set wherein the pulse width has been reduced from both ends).
Regarding claims 6 and 19, Chung teaches that the display panel driver further includes: a signal generator configured to generate a vertical start signal (¶ 29: Vsync) and a data enable signal (¶ 29: data-enable signal DE); and a cycle counter configured to determine whether a present driving cycle is the writing cycle or the holding cycle based on the vertical start signal and the data enable signal (fig. 7, note that each frame is determined based on the Vsync signal and each R0 frame is indicative of a data-enable signal because data is loaded into the frame), and the cycle counter is further configured to determine the holding cycle number of the present holding cycle based on the vertical start signal and the data enable signal when the holding cycles are repeated in the driving sequence (fig. 7, note the count numbers related to refresh frames (data write frames including data enable signals) and hold frames which are counted based on the number of frames each of which begins with a vertical start signal or Vsync).
Regarding claim 8, Chung teaches that the display panel driver further includes a lookup table configured to store the emission off time corresponding to the holding cycle number (fig. 6B, element 250, ¶ 125; note that each refresh rate corresponds to a holding cycle number).
Regarding claim 9, Chung teaches that the display panel driver further includes a register configured to determine the emission off time corresponding to the holding cycle number based on an emission off setting, and to output the emission off time corresponding to the holding cycle number from the lookup table (fig. 6B, element 250 wherein emission off time is output according to the flags 211/212 and counter values based on which the register 250 outputs an emission signal having an appropriate emission off time; see ¶ 124-127).
Regarding claim 10, Chung teaches that the display panel driver further includes an emission off time output circuit configured to receive the holding cycle number of the present holding cycle from the cycle counter, and to output the emission off time corresponding to the holding cycle number from the lookup table (see circuit of fig. 6B which includes the counter 220 according to which an emission signal having an appropriate emission off time is output based on the lookup table 250; ¶ 124-127).
Regarding claim 11, Chung teaches that the display panel driver further comprises: a position setter configured to output the setting value with which the emission driver determines whether to change the end point of the off duration of the emission signal or to change the start point of the off duration of the emission signal (circuit of fig. 6B performs such position setting according to the output of the elements 210, 220 and 230; for example setting value of 100 micro seconds or 300 micro seconds are provided which set the start and or end positions of the emission signal); and an emission driver configured to generate the emission signal based on the emission off time received from the emission off time output circuit and the setting value received from the position setter, and to provide the emission signal to the pixel (fig. 6B, elements 260 and/or 270 may be such an emission driver; ¶ 124-127).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chung and Noh, as applied above, further in view of Kim et al., US 2022/0101794 A1, hereinafter “Kim”.
Regarding claim 7, Chung and Noh do not specifically teach that the cycle counter determines the present driving cycle as the writing cycle when the cycle counter receives pulses of the data enable signal repeatedly after receiving the vertical start signal, and the cycle counter determines the present driving cycle as the holding cycle when the cycle counter does not receive the pulses of the data enable signal after receiving the vertical start signal.
Kim teaches that each active period or writing cycle includes pulses of the data enable signal input repeatedly after the vertical start signal (fig. 2, see inputting of DE pulses at the beginning of each frame or after the vertical start signal). Kim further teaches that the blanking period similar to a holding period does not include such data enable pulses.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Chung, Noh and Kim. Chung clearly teaches “A counter 220 counts by distinguishing between the refresh frame and the hold frame for each refresh rate on the basis of the flag value output from the flag unit 210, thereby distinguishing between the driving timing for each frame and outputting the accumulated count values” (see ¶ 102). Kim further teaches that a data writing frame similar to R0 of Chung is clearly distinguished by the inputting of DE pulses after a Vsync signal. Accordingly, one would have been motivated to utilize the DE and Vsync signals as taught by both Chung and Kim in order to distinguish between the refresh frame and hold frames as required by Chung, thereby reliably distinguishing refresh frames from hold frames and accurately counting the frames.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chung and Noh, as applied above, further in view of Wang et al., US 2024/0363073 A1, hereinafter “Wang”.
Regarding claim 12, Chung and Noh do not specifically teach the pixel circuit as claimed.
Wang, however, clearly teaches such a pixel circuit (see fig. 11). Specifically, Wang teaches that the pixel comprises: a driving switching element (fig. 11, TD) including a control electrode of the driving switching element connected to a first node (N1), a first electrode of the driving switching element connected to a second node (N2) and a second electrode of the driving switching element connected to a third node (N3); a bias switching element (T2) including a control electrode of the bias switching element configured to receive a bias gate signal (Gate2), a first electrode of the bias switching element configured to receive a bias voltage (Vinit3) and a second electrode of the bias switching element connected to the second node; a first emission switching element (T5) including a control electrode of the first emission switching element configured to receive the emission signal (EM1), a first electrode of the first emission switching element configured to receive a first power voltage (VDD) and a second electrode of the first emission switching element connected to the second node; a second emission switching element (T6) including a control electrode of the second emission switching element configured to receive the emission signal (EM1), a first electrode of the second emission switching element connected to the third node and a second electrode of the second emission switching element connected to a first electrode of the light emitting element (see fig. 11); a data writing switching element (T3) including a control electrode of the data writing switching element configured to receive a data writing gate signal (Gate1), a first electrode of the data writing switching element configured to receive the data voltage (Data) and a second electrode of the data writing switching element connected to the second node; a compensation switching element (T1) including a control electrode of the compensation switching element configured to receive a compensation gate signal (Gate1), a first electrode of the compensation switching element connected to the first node and a second electrode of the compensation switching element connected to the third node (fig. 11, T1); a data initialization switching element (T4) including a control electrode of the data initialization switching element configured to receive a data initialization gate signal (Reset1), a first electrode of the data initialization switching element configured to receive an initialization voltage (Vinit1) and a second electrode of the data initialization switching element connected to the first node; and a light emitting element initialization switching element (T7) including a control electrode of the light emitting element initialization switching element configured to receive the bias gate signal (Gate2), a first electrode of the light emitting element initialization switching element configured to receive a light emitting element initialization voltage (Vinit2) and a second electrode of the light emitting element initialization switching element connected to the first electrode of the light emitting element (see fig. 11).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Chung, Noh and Wang. The references teach display devices including pixels that are to be driven in refresh and hold frames. While Chung teaches a pixel circuit including a similar pixel configuration as claimed, Wang teaches a pixel circuit having an identical pixel configuration as claimed. One would have been motivated to utilize the pixel configuration of Wang as the pixel of the display device while expecting the same result of providing a display device capable of being driven at different refresh frequencies including refresh and hold frames as taught by the references.
Regarding claim 13, Chung and Noh do not teach that the compensation switching element includes two transistors connected to each other in series, and the data initialization switching element includes two transistors connected to each other in series.
Wang, however, clearly teaches that the compensation switching element includes two transistors connected to each other in series (fig. 11, T11 transistors), and the data initialization switching element includes two transistors connected to each other in series (fig. 11, T41 transistors).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Chung, Noh and Wang. The references teach display devices including pixels that are to be driven in refresh and hold frames. While Chung teaches a pixel circuit including a similar pixel configuration as claimed, Wang teaches a pixel circuit having an identical pixel configuration as claimed. One would have been motivated to utilize the pixel configuration of Wang as the pixel of the display device while expecting the same result of providing a display device capable of being driven at different refresh frequencies including refresh and hold frames as taught by the references.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEPEHR AZARI/ Primary Examiner, Art Unit 2621
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