Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claims 14-15 are objected to because of the following informalities:
Regarding claim 14, it recites “a plurality of pixels a plurality of scan lines” in line 2, which appears to be “a plurality of pixels, a plurality of scan lines”. Appropriate correction is required.
Regarding claim 15, it is objected based on its dependence from claim 14.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 12 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gu et al. (US 2020/0066207), in view of Park (US 2018/0226028).
Regarding claim 1, Gu discloses a pixel (see pixel PX in Figs. 1-2) comprising:
a first transistor including a gate electrode connected to a first node, wherein the first transistor is connected between a first power line and a second node (para[0034]; see transistor T1 in Fig. 2 with a gate electrode connected to N1, and connected between voltage line to which ELVDD is applied and N3);
a second transistor including a gate electrode connected to an i-th scan
line, wherein the second transistor is connected between the first node and a
third node, and i is an integer equal to or greater than 1 (para[0035]; see transistor T2 in Fig. 2 with “a gate electrode electrically connected to the i.sup.th scan line (e.g., the selected one of the first to n.sup.th scan lines SL1 to SLn shown in FIG. 1) to receive a scan signal GW[i]”, and connected between N1 and N2);
a third transistor including a gate electrode connected to a common control line,
wherein the third transistor is connected between the second node and the
third node (para[0036]; see transistor T3 in Fig. 2 with a gate connected to common control line providing voltage GC and connected between N3 and N2);
a light-emitting element connected between the second node and a
second power line (para[0040]; see light-emitting element OLED in Fig. 2, connected between N3 and voltage line to which ELVSS is applied);
a first capacitor including a first electrode connected to the first node
and a second electrode connected to a third power line (para[0037]; see first capacitor Cst in Fig. 2, connected between N1 and VINT); and
a second capacitor including a first electrode connected to the third
node and a second electrode connected to a data line (para[0038]; see second capacitor Cpr in Fig. 2, connected between N2 and data line DL to which data signal D[j] is applied).
However, Gu does not appear to expressly disclose the gate electrode of the third transistor connected to a j-th scan line, and j is an integer different from i.
Park discloses a second transistor including a gate electrode connected to an i-th scan line, wherein the second transistor is connected between a first node and a third node, and i is an integer equal to or greater than 1 (para[0043]; para[0073]; see transistor T2 in Fig. 8 with “a gate electrode receiving the (i)th scan signal S[i] from the (i)th scan line, a first electrode connected to… first node N1, and a second electrode connected to… third node N3”, “where i is between 1 and n”); and a third transistor including a gate electrode connected to a j-th scan line,
wherein the third transistor is connected between a second node and the
third node, and j is an integer different from i (para[0043]; para[0074]; see transistor T3 in Fig. 8 with “a gate electrode receiving the (i+1)th scan signal S[i+1] from the (i+1)th scan line, a first electrode connected to the third node N3, and a second electrode connected to… second node N2”, i+1 being the claimed j, which is clearly an integer different from i).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Gu’s invention, with the teachings in Park’s invention, to have the gate electrode of the third transistor connected to a j-th scan line, and j is an integer different from i, as a feasible alternative to using a common control line and signal (para[0081]; para[0083]).
Regarding claim 2, Gu and Park discloses all the claim limitations as applied above (see claim 1). In addition, the combination already discloses j is an integer greater than i (see in Park’s para[0043] and para[0074], transistor T3 in Fig. 8 with “a gate electrode receiving the (i+1)th scan signal S[i+1] from the (i+1)th scan line, a first electrode connected to the third node N3, and a second electrode connected to… second node N2”, i+1 being the claimed j, which is clearly an integer greater than i).
Regarding claim 3, Gu and Park discloses all the claim limitations as applied above (see claim 2). In addition, the combination already discloses j is equal to (i+1) (see in Park’s para[0043] and para[0074], transistor T3 in Fig. 8 with “a gate electrode receiving the (i+1)th scan signal S[i+1] from the (i+1)th scan line, a first electrode connected to the third node N3, and a second electrode connected to… second node N2”, i+1 being the claimed j).
Regarding claim 4, Gu and Park discloses all the claim limitations as applied above (see claim 1). In addition, Gu discloses the first to third transistors are P-type
Transistors (para[0033]; see in Fig. 2, “each of the first switching element T1, the second switching element T2, and the third switching element T3 may be a PMOS transistor”).
Regarding claim 5, Gu and Park discloses all the claim limitations as applied above (see claim 1). In addition, Gu discloses a first power supply voltage is applied to the first power line (para[0034]; see voltage ELVDD in Fig. 2);
a second power supply voltage is applied to the second power line (para[0040]; see voltage ELVSS in Fig. 2);
a third power supply voltage is applied to the third power line (para[0037]; see voltage VINT in Fig. 2);
an i-th scan signal is applied to the i-th scan line (para[0035]; see scan signal GW[i] in Fig. 2); and
each of the first to third power supply voltages has a varying voltage level (as shown in Fig. 3, voltages ELVDD, ELVSS and VINT have varying voltage levels).
In addition, in the combination, Park already discloses an (i+1)-th scan signal is applied to the j-th scan line (para[0043]; para[0074]; regarding Figs. 3-4 and 8, see (i+1)th scan signal S[i+1] from an (i+1)th scan line).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have an (i+1)-th scan signal is applied to the j-th scan line, as also taught by Park, as a feasible alternative to using a common control signal (para[0081]; para[0083]).
Regarding claim 6, Gu and Park discloses all the claim limitations as applied above (see claim 5). In addition, Gu discloses in a first period of a frame period (para[0043]; see period F1 in Fig. 3):
the first power supply voltage has a first voltage at a high level (para[0048]; “In the first initialization period F1, the first supply voltage ELVDD may have the first high voltage level VH1”, as shown in Fig. 3);
the second power supply voltage has a third voltage at a high level (para[0048]; “In the first initialization period F1,… the second supply voltage ELVSS may have the… high voltage level VH2”, as shown in Fig. 3);
the third power supply voltage has a sixth voltage at a low level (para[0050]; in the period F1, “The initializing voltage VINT may have… initializing voltage level VINT_L”, as shown in Fig. 3);
the i-th scan signal has an off level (para[0049]; in the period F1, “The scan signal GW[i] may have an “off” voltage level (a turn-“off” voltage level, a turn-off voltage, or a logic high level)”); and
a common control signal [the (i+1)-th scan signal in the combination] has the off level (see in Gu’s para[0049], in the period F1 in Fig. 3, “the common control signal GC may have an “off” voltage level”; see in Park’s para[0052], para[0074], in the period PA1 in Fig. 3 (or Fig. 4), scan signal S[i+1] has an off-level).
Regarding claim 7, Gu and Park discloses all the claim limitations as applied above (see claim 5). In addition, Gu discloses in a second period of a frame period (para[0043]; see period F2 in Fig. 3):
the first power supply voltage has a second voltage at a low level (para[0052]; ELVDD has a “low voltage level VL1 during the second initialization period F2”, as shown in Fig. 3);
the second power supply voltage has a third voltage at a high level (ELVSS has the high voltage level VH2 during the second initialization period F2, as shown in Fig. 3);
the third power supply voltage has a sixth voltage at a low level (para[0053]; the initializing voltage VINT has a low voltage level VINT_L in the initialization period F2, as shown in Fig. 3);
the i-th scan signal transitions to the on level (para[0051]; “scan signal GW[i]… may transition from the turn-off voltage to the turn-“on” voltage level at the start of the second initialization period F2”);
a common control signal [the (i+1)-th scan signal in the combination] transitions to the on level (see in Gu’s para[0051], as shown in Fig. 3, “the common control signal GC may transition from the turn-off voltage to the turn-“on” voltage level at the start of the second initialization period F2”; see in Park’s para[0053], para[0074], in the period PA2 in Fig. 3 (or Fig. 4), scan signal S[i+1] transitions to an on-level)); and
the first to third nodes are electrically connected to each other (as shown in Figs. 2-3, N1, N3 and N2 are electrically connected during initialization period F2; para[0054]).
Regarding claim 8, Gu and Park discloses all the claim limitations as applied above (see claim 5). In addition, Gu discloses in a third period of a frame period (para[0043]; see period F3 in Fig. 3):
the first power supply voltage has a first voltage at a high level (para[0055]; ELVDD has the first high voltage level VH1 during the threshold voltage compensation period F3, as shown in Fig. 3);
the second power supply voltage has a third voltage at a high level (ELVSS has the high voltage level VH2 during the threshold voltage compensation period F3, as shown in Fig. 3);
the third power supply voltage has a fifth voltage at a high level (para[0055]; the initializing voltage VINT has a high voltage level VINT_H in the threshold voltage compensation period F3, as shown in Fig. 3);
the i-th scan signal has an on level (para[0055]; “The scan signal GW[i]… may have the “on” voltage level” during the threshold voltage compensation period F3, as shown in Fig. 3);
a common control signal [the (i+1)-th scan signal in the combination] has the on level (para[0055]; “the common control signal GC may have the “on” voltage level” during the threshold voltage compensation period F3, as shown in Fig. 3; see in Park’s para[0054], para[0074], in the threshold voltage compensation period F3 in Fig. 3 (or Fig. 4), scan signal S[i+1] has an on-level); and
the first power line is electrically connected to the first node through the
second and third nodes (according to Figs. 2-3, the voltage line to which ELVDD is applied is electrically connected to N1 through N3 and N2 during the threshold voltage compensation period F3).
Regarding claim 9, Gu and Park discloses all the claim limitations as applied above (see claim 5). In addition, Gu discloses at least a part of a fourth period of a frame period (para[0043]; see period F4 in Fig. 3):
the first power supply voltage has a second voltage at a low level (para[0056]; “At the start of the data write period F4, the first supply voltage ELVDD may have the first low voltage level VL1”, as shown in Fig. 3);
the second power supply voltage has a third voltage at a high level (para[0056]; “At the start of the data write period F4,… the second supply voltage ELVSS may have the second high voltage level VH2”, as shown in Fig. 3);
the third power supply voltage has a fifth voltage at a high level (para[0059]; the initializing voltage VINT has a high voltage level VINT_H in the data write period F4, as shown in Fig. 3);
the i-th scan signal has an on level (para[0057]; see in Fig. 3 when “the scan signal GW[i] has the “on” voltage level” during the data write period F4);
a common control signal [the (i+1)-th scan signal in the combination] has an off level (see in Gu’s para[0056], in the data write period F4 in Fig. 3, “the common control signal GC has the “off” voltage level”; see in Park para[0074], and when in the period PA4 in Fig. 3 (or Fig. 4) scan signal S[i+1] has an off-level); and
the first node and the third node are electrically connected to each other (according to Figs. 2-3, N1 and N2 are connected during the data write period F4).
Regarding claim 10, Gu and Park discloses all the claim limitations as applied above (see claim 9). In addition, Gu discloses in a remaining part of the fourth
period of the frame period (para[0043]; see remaining parts of period F4 in Fig. 3):
the first power supply voltage has the second voltage (see the first supply voltage ELVDD at the first low voltage level VL1 during other portions of the data write period F4, as shown in Fig. 3);
the second power supply voltage has the third voltage (see the second supply voltage ELVSS has the second high voltage level VH2 during other portions of the data write period F4, as shown in Fig. 3);
the third power supply voltage has the fifth voltage (para[0059]; see the initializing voltage VINT has a high voltage level VINT_H during other portions of the data write period F4, as shown in Fig. 3);
the i-th scan signal has the off level (para[0057]; see in Fig. 3 that GW[i] has the “off” voltage level during another portion of the data write period F4).
In addition, Park discloses in a remaining part of the fourth period of the frame period: the (i+1)-th scan signal has an on level (para[0055]; “The panel driver may progressively provide the scan signals S[1] through S[n] having an on-level to the scan lines” during another portion of the on-level, and accordingly, see that during another portion of the period PA4 in Fig. 3 (or Fig. 4), scan signal S[i+1] has an on-level); and the second node and the third node are electrically connected to each other (para[0055]; para[0074]; regarding Figs. 3(or 4) and 8, it is clear that when S[i+1] has an on-level, N2 and N3 are connected to each other through transistor T3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the (i+1)-th scan signal has the on level; and the second node and the third node are electrically connected to each other, as also taught by Park, as a consequence of using the (i+1)-th scan signal as the feasible alternative to using the common control line and signal, and still be able to drive the pixel in substantially the same manner (para[0081]; para[0083]).
Regarding claim 12, Gu and Park discloses all the claim limitations as applied above (see claim 9). In addition, Gu discloses in a sixth period of a frame period (para[0043]; see period F5 in Fig. 3):
the first power supply voltage has a first voltage at a high level (para[0064]-para[0065]; see the first supply voltage ELVDD has the first high voltage level VH1 during emission period F5, as shown in Fig. 3);
the second power supply voltage has a fourth voltage at a low level (para[0064]-para[0065]; see the second supply voltage ELVSS has the second low voltage level VL2 during emission period F5, as shown in Fig. 3);
the third power supply voltage has a fifth voltage at a high level (para[0065]; see “the initializing voltage VINT may remain at the first initializing voltage level VINT_H”, as shown in Fig. 3);
a common control signal [the (i+1)-th scan signal in the combination] has the off level (see in Gu’s para[0065], in the period F5 in Fig. 3, “the common control signal GC may have the “off” voltage level”; see in Park’s para[0060], para[0074], in the period PA5 in Fig. 3 (or Fig. 4), scan signal S[i+1] has an off-level); and
a driving current flows through the light-emitting element (para[0065]; regarding Figs. 2-3, “During the emission period F5, the driving current I_OLED is generated in the first switching element T1 according to the change of the first supply voltage ELVDD and the second supply voltage ELVSS, and the driving current I_OLED may flow to the light-emitting element OLED through the first switching element T1”).
In addition, Park discloses in a sixth period of a frame period: the i-th scan signal has an off level (regarding Figs. 3 (or 4) and 8, “During the emission period PA5… scan signal S[i] has an off-level”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have the i-th scan signal has an off level, as the feasible alternative while still being able to drive the pixel in substantially the same manner.
Regarding claim 14, Gu discloses a display device (see display device 1 in Fig. 1) comprising:
a display panel comprising a plurality of pixels a plurality of scan lines
connected to the plurality of pixels, and a plurality of data lines connected to the
plurality of pixels (see display panel 10 in Fig. 1, comprising pixels PX, and scan lines SL and data lines DL connected to the pixels PX);
a scan driving circuit which supplies a scan signal to the plurality of
scan lines (see scan driver 20 in Fig. 1; para[0025]); and
a data driving circuit which supplies a data voltage to the plurality of
data lines (see data driver 30 in Fig. 1; para[0026]),
wherein a first pixel of the plurality of pixels is connected to an i-th scan
line of the plurality of scan lines, a common control line, and a j-th data line of the plurality of data lines, wherein i is an integer equal to or greater than 1, and j is an integer equal to or greater than 1 (see in Figs. 1-2, e.g. first pixel PX connected to scan line SL1, a common control line providing voltage GC, and data line DL1, wherein i=j=1; transistor T2 of the pixel PX includes “a gate electrode electrically connected to the i.sup.th scan line (e.g., the selected one of the first to n.sup.th scan lines SL1 to SLn shown in FIG. 1) to receive a scan signal GW[i]” and transistor T3 includes a gate connected to common control line providing voltage GC; para[0035]-para[0036]),
wherein a second pixel of the plurality of pixels is connected to the i-th
scan line, the common control line, and a (j+1)-th data line of the plurality of data
lines (regarding Figs. 1-2, see e.g. a second pixel PX connected to scan line SL1, the common control line providing voltage GC, and data line DL2),
wherein a third pixel of the plurality of pixels is connected to the (i+1)-th
scan line, the common control line, and the j-th data line (regarding Figs. 1-2, see e.g. a third pixel PX connected to scan line SL2, the common control line providing voltage GC, and data line DL1),
wherein a fourth pixel of the plurality of pixels is connected to the (i+1)-th scan line, the common control line, and the (j+1)-th data line (regarding Figs. 1-2, see e.g. a fourth pixel PX connected to scan line SL2, the common control line providing voltage GC, and data line DL2),
wherein the first pixel and the second pixel receive corresponding data voltages in response to a scan signal supplied to the i-th scan line (regarding Figs. 1-2, the pixel PX connected to scan line SL1 and data line DL1, and the pixel PX connected to scan line SL1 and data line DL2, receive corresponding data voltages in response to a scan signal supplied to scan line SL1), and
wherein the third pixel and the fourth pixel receive corresponding data voltages in response to a scan signal supplied to the (i+1)-th scan line (regarding Figs. 1-2, the pixel PX connected to scan line SL2 and data line DL1, and the pixel PX connected to scan line SL2 and data line DL2, receive corresponding data voltages in response to a scan signal supplied to scan line SL2).
However, Gu does not appear to expressly disclose the first pixel of the plurality of pixels is connected to an (i+1)-th scan line of the plurality of scan lines, the second pixel of the plurality of pixels is connected to the (i+1)-th scan line, the third pixel of the plurality of pixels is connected to the (i+2)-th scan line, and the fourth pixel of the plurality of pixels is connected the (i+2)-th scan line.
Park discloses first pixel of a plurality of pixels is connected to an (i+1)-th scan line of the plurality of scan lines, second pixel of the plurality of pixels is connected to the (i+1)-th scan line, third pixel of the plurality of pixels is connected to an (i+2)-th scan line, and fourth pixel of the plurality of pixels is connected the (i+2)-th scan line (para[0043]; para[0071]; para[0073]-para[0074]; “FIG. 8 illustrates… a pixel PXE, which may be representative of the pixels in the display device in FIG. 1”; accordingly, regarding Figs. 1 and 8, see first pixel PX connected to SL1, SL2, and DL1; second pixel PX connected to SL1, SL2, and DL2; third pixel PX connected to SL2, SL3, and DL1; fourth pixel PX connected to SL2, SL3, and DL2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Gu’s invention, with the teachings in Park’s invention, to have the first pixel of the plurality of pixels is connected to an (i+1)-th scan line of the plurality of scan lines, the second pixel of the plurality of pixels is connected to the (i+1)-th scan line, the third pixel of the plurality of pixels is connected to the (i+2)-th scan line, and the fourth pixel of the plurality of pixels is connected the (i+2)-th scan line, as a feasible alternative to using a common control line and signal (para[0081]; para[0083]).
Regarding claim 15, Gu and Park discloses all the claim limitations as applied above (see claim 14). In addition, the claim recites limitations of the first pixel which are analogous to the pixel of claim 3, and therefore it is rejected for the same reasons as claim 3 above.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gu et al. (US 2020/0066207), in view of Park (US 2018/0226028), as applied to claim 1 above, and further in view of Kim (US 2023/0267884).
Regarding claim 13, Gu and Park discloses all the claim limitations as applied above (see claim 1). However, Gu and Park do not appear to expressly disclose semiconductor layers of the first transistor and the third transistor are defined by a first active pattern, and wherein a semiconductor layer of the second transistor is defined by a second active pattern spaced apart from the first active pattern.
Kim discloses semiconductor layers of a first transistor and a third transistor are defined by a first active pattern (regarding Figs. 4-7, and based on the broadest reasonable interpretation of the claimed limitations, see semiconductor layers of driving transistor DT and transistor ST1-2 defined e.g. by active patterns DT_ACT and ACT1-2 adjacent to each other and connected through driving sub-active pattern 51 and first sub-active pattern 52), and wherein a semiconductor layer of a second transistor is defined by a second active pattern spaced apart from the first active pattern (regarding Figs. 4-5A, and based on the broadest reasonable interpretation of the claimed limitations, see a semiconductor layer of transistor ST1-1 defined by active pattern ACT1-1 which spaced apart from active pattern DT_ACT).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Gu’s and Park’s combination, with the teachings in Kim’s invention, to have semiconductor layers of the first transistor and the third transistor are defined by a first active pattern, and wherein a semiconductor layer of the second transistor is defined by a second active pattern spaced apart from the first active pattern, for the advantage of a configuration that suppresses leakage currents and would prevent display luminance from decreasing when a display device is driven with a low frame frequency when displaying a still image to reduce power consumption, such that flicking is not recognized (para[0027]).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gu et al. (US 2020/0066207), in view of Park (US 2018/0226028), and further in view of Takasugi (US 2019/0180691).
Regarding claim 16, Gu discloses an electronic device (para[0114]; e.g. “a cellular phone, smart phone, smart pad, and personal digital assistant”) comprising:
input image data (para[0030]; “The timing controller 50 may generate image data suitable for the display panel 10 based on… input image data to provide the image data to the data driver 30”); and
a display device (see display device 1 in Fig. 1) comprising a plurality of pixels for displaying an image based on the input image data, and a plurality of scan lines connected to the plurality of pixels (see in Fig. 1 pixels PX for displaying an image and scan lines SL connected to the pixels PX; para[0023]; para[0030]; para[0043]).
In addition, claim 16 recites pixel limitations analogous to those of the pixel of claim 3, and therefore it is rejected for the reasons provided for claim 3 above.
However, Gu and Park do not appear to expressly disclose a host which provides the input image data.
Takasugi discloses a host which provides input image data (para[0046]; “timing controller 110 receives image data RGB from an external host system through various known interface methods”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Gu’s and Park’s combination, with the teachings in Takasugi’s invention, to have a host which provides the input image data, for the known advantage of sending high-quality image data from a host to a timing controller which then processes the received image data (para[0046]).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the prior art, taken alone or in combination, fails to teach or suggest the following limitations in combination with the rest of the claim, that is, the claim as a whole: “in a fifth period of a frame period:
the first power supply voltage has a second voltage at a low level;
the second power supply voltage transitions to a fourth voltage at a low
the third power supply voltage transitions to a sixth voltage at a low level;
the i-th scan signal has an off level; and
the (i+ 1 )-th scan signal has the off level”, as claimed in claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GLORYVID FIGUEROA-GIBSON whose telephone number is (571)272-5506. The examiner can normally be reached on 9am-5pm, Monday -Friday, Eastern Time.
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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