Amazon - chipsNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1 – 20 are presented for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 120 is acknowledged.
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/19/2025 was received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1 – 20 are rejected on the ground of nonstatutory double patenting over claims 1 – 20 of U.S. Patent No. 12,340,124 since the claims, if allowed, would improperly extend the “right to exclude” already granted in the patent.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows:
Claim 1 – Application 19/212375
Claim 1 – Patent 12,340,124
A memory system comprising:
A method of controlling
a semiconductor memory device including a bit line, a plurality of memory cells, a first select transistor, a first select gate line, and a plurality of word lines, the memory cells being connected in series, the first select transistor being connected in series with the memory cells, the first select transistor being electrically connected to the bit line, the first select gate line being electrically connected to a gate of the first select transistor, each of the plurality of word lines being electrically connected to a gate of each of the plurality of memory cells, each of the plurality of memory cells being configured to store n- bit data, the n being an integer larger than or equal to three; and
a semiconductor memory device including a bit line, a plurality of memory cells, a first select transistor, a first select gate line, and a plurality of word lines, the memory cells being connected in series, the first select transistor being connected in series with the memory cells, the first select transistor being electrically connected to the bit line, the first select gate line being electrically connected to a gate of the first select transistor, each of the plurality of word lines being electrically connected to a gate of each of the plurality of memory cells, each of the plurality of memory cells being configured to store n-bit data, the n being an integer larger than or equal to three,
a controller configured to control the semiconductor memory device, wherein
the method comprising:
the controller is configured to send a first command to the semiconductor memory device, the controller is configured to send a second command to the semiconductor memory device,
in response to the first command, the semiconductor memory device is configured to apply a first voltage to a first word line of the word lines, a second voltage to a second word line of the word lines and a third voltage to a third word line of the word lines to read data from a first memory cell of the memory cells as first data, the first word line being electrically connected to a gate of the first memory cell, the second word line being electrically connected to a gate of a second memory cell of the memory cells, the third word line being electrically connected to a gate of a third memory cell of the memory cells, the second memory cell being connected in series with the first memory cell, the third memory cell being connected in series with the second memory cell; and
in response to a first command, applying a first voltage to a first word line of the word lines, a second voltage to a second word line of the word Tines and a third voltage to a third word line of the word lines to read data from a first memory cell of the memory cells as first data, the first word line being electrically connected to a gate of the first memory cell, the second word line being electrically connected to a gate of a second memory cell of the memory cells, the third word line being electrically connected to a gate of a third memory cell of the memory cells, the second memory cell being connected in series with the first memory cell, the third memory cell being connected in series with the second memory cell; and
in response to the second command, the semiconductor memory device is configured to apply a fourth voltage to the first word line, a fifth voltage to the second word line, and a sixth voltage to the third word line,
in response to a second command, applying a fourth voltage to the first word line, applying a fifth voltage to the second word line, and applying a sixth voltage to the third word line,
the n-bit data corresponds to a first through a 2n-th threshold voltage ranges,
wherein the n-bit data corresponds to a first through a 2n-th threshold voltage ranges,
the (i+1)-th threshold voltage range is greater than the i-th threshold voltage range, the i being an integer larger than or equal to one and smaller than or equal to (2n -1)
the (i+1)-th threshold voltage range is greater than the i-th threshold voltage range, the i being an integer larger than or equal to one and smaller than or equal to (2n−1),
the first voltage is at least one of first through (2n -1)-th threshold voltages,
the first voltage is at least one of first through (2n−1)-th threshold voltages,
the j-th threshold voltage is a boundary voltage between the j-th threshold voltage range and the j-th threshold voltage range and the (j+1) threshold voltage range, the j being an integer larger than or equal to one and smaller than or equal to (2n–1), and
the j-th threshold voltage is a boundary voltage between the j-th threshold voltage range and the (j+1) threshold voltage range, the j being an integer larger than or equal to one and smaller than or equal to (2n−1), and
each of the second through the sixth voltages is larger than the (2n -1)-th threshold voltage.
each of the second through the sixth voltages is larger than the (2n−1)-th threshold voltage.
One of ordinary skill in the art would clearly recognize independent claim 1, of application 19/212375 is an obvious variation of the claimed subject matter of independent claim 1, of patent 12,340,124. Specifically, both claim 1, of the current application 19/212375, and claim 1, of patent 12,340,124 discloses: controlling “a semiconductor memory device including a bit line, a plurality of memory cells, a first select transistor, a first select gate line, and a plurality of word lines, the memory cells being connected in series, the first select transistor being connected in series with the memory cells, the first select transistor being electrically connected to the bit line, the first select gate line being electrically connected to a gate of the first select transistor, each of the plurality of word lines being electrically connected to a gate of each of the plurality of memory cells, each of the plurality of memory cells being configured to store n- bit data, the n being an integer larger than or equal to three”, comprising such steps as “in response to the first command, the semiconductor memory device is configured to apply a first voltage to a first word line of the word lines, a second voltage to a second word line of the word lines and a third voltage to a third word line of the word lines to read data from a first memory cell of the memory cells as first data, the first word line being electrically connected to a gate of the first memory cell, the second word line being electrically connected to a gate of a second memory cell of the memory cells, the third word line being electrically connected to a gate of a third memory cell of the memory cells, the second memory cell being connected in series with the first memory cell, the third memory cell being connected in series with the second memory cell”, and “in response to the second command, the semiconductor memory device is configured to apply a fourth voltage to the first word line, a fifth voltage to the second word line, and a sixth voltage to the third word line”.
One of ordinary skill in the art would recognize the memory system disclosed by claim 1, of the current application 19/212375, as a direct recitation of the operations performed by the method disclosed in claim 1 of Patent 12,340,124. A memory system performing operations and a method capable of performing the operation of the disclosed memory system would be recognize by one of ordinary skill in the art as obvious variants of each other.
Therefore, one of ordinary skill in the art would recognize the memory system of claim 1, of the current application 19/212375, as performing the operations of the method of claim 1, of U.S. Patent 12,340,124, and as such are obvious variants of each other.
Claim 2 – Application 19/212375
Claim 2 – Patent 12,340,124
Claim 3 – Application 19/212375
Claim 3 – Patent 12,340,124
Claim 4 – Application 19/212375
Claim 4 – Patent 12,340,124
Claim 5 – Application 19/212375
Claim 5 – Patent 12,340,124
Claim 6 – Application 19/212375
Claim 6 – Patent 12,340,124
Claim 7 – Application 19/212375
Claim 7 – Patent 12,340,124
Claim 8 – Application 19/212375
Claim 8 – Patent 12,340,124
Claim 9 – Application 19/212375
Claim 9 – Patent 12,340,124
Claim 10 – Application 19/212375
Claim 10 – Patent 12,340,124
Claim 11 – Application 19/212375
Claim 11 – Patent 12,340,124
Claim 12 – Application 19/212375
Claim 12 – Patent 12,340,124
Claim 13 – Application 19/212375
Claim 13 – Patent 12,340,124
Claim 14 – Application 19/212375
Claim 14 – Patent 12,340,124
Claim 15 – Application 19/212375
Claim 15 – Patent 12,340,124
Claim 16 – Application 19/212375
Claim 16 – Patent 12,340,124
Claim 17 – Application 19/212375
Claim 17 – Patent 12,340,124
Claim 18 – Application 19/212375
Claim 18 – Patent 12,340,124
Claim 19 – Application 19/212375
Claim 19 – Patent 12,340,124
Claim 20 – Application 19/212375
Claim 20 – Patent 12,340,124
Claim 1 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of commonly owned patent no. 11,561,736. Although the conflicting claims are not identical, they are not patentably distinct from each other because as shown in the chart and explanation below:
Clm
Instant application
Clm
US Patent no. 11,561,736
1
A method of controlling a semiconductor memory device including a bit line, a plurality of memory cells, a first select transistor, a first select gate line, and a plurality of word lines, the memory cells being connected in series, the first select transistor being connected in series with the memory cells, the first select transistor being electrically connected to the bit line, the first select gate line being electrically connected to a gate of the first select transistor, each of the plurality of word lines being electrically connected to a gate of each of the plurality of memory cells, each of the plurality of memory cells being configured to store n-bit data, the n being an integer larger than or equal to three, the method comprising: in response to a first command, applying a first voltage to a first word line of the word lines, a second voltage to a second word line of the word lines and a third voltage to a third word line of the word lines to read data from a first memory cell of the memory cells as first data, the first word line being electrically connected to a gate of the first memory cell, the second word line being electrically connected to a gate of a second memory cell of the memory cells, the third word line being electrically connected to a gate of a third memory cell of the memory cells, the second memory cell being connected in series with the first memory cell, the third memory cell being connected in series with the second memory cell; and in response to a second command, applying a fourth voltage to the first word line, applying a fifth voltage to the second word line, and applying a sixth voltage to the third word line, wherein the n-bit data corresponds to a first through a 2n-th threshold voltage ranges, the (i+1)-th threshold voltage range is greater than the i-th threshold voltage range, the i being an integer larger than or equal to one and smaller than or equal to (2n-1), the first voltage is at least one of first through (2n -1)- th threshold voltages, the j-th threshold voltage is a boundary voltage between the j-th threshold voltage range and the (j+1) threshold voltage range, the being an integer larger than or equal to one and smaller than or equal to (2n -1), and each of the second through the sixth voltages is larger than the (2ⁿ-1)-th threshold voltage.
1
A method of controlling a semiconductor memory device including a bit line, a plurality of memory cells, a first select transistor, a first select gate line, and a plurality of word lines, the memory cells being connected in series, the first select transistor being connected in series with the memory cells, the first select transistor being electrically connected to the bit line, the first select gate line being electrically connected to a gate of the first select transistor, each of the plurality of word lines being electrically connected to a gate of each of the plurality of memory cells, the method comprising: in response to a first command, applying a first voltage to a first word line of the word lines, a second voltage to a second word line of the word lines and a third voltage to a third word line of the word lines to read data from a first memory cell of the memory cells as first data, the first word line being electrically connected to a gate of the first memory cell, the second word line being electrically connected to a gate of a second memory cell of the memory cells, the third word line being electrically connected to a gate of a third memory cell of the memory cells, the second memory cell being connected in series with the first memory cell, the third being connected in series with the second memory cell; and in response to a second command, applying a fourth voltage to the first word line, applying a fifth voltage to the second word line, and applying a sixth voltage to the third word line, wherein the first memory cell is turned on by the applying the fourth voltage regardless of data stored in the first memory cell, the second memory cell is turned on by the applying the second voltage regardless of data stored in the second memory cell, the second memory cell is turned on by the applying the fifth voltage regardless of data stored in the second memory cell, the third memory cell is turned on by the applying the third voltage regardless of data stored in the third memory cell, and the third memory cell is turned on by the applying the sixth voltage memory cell regardless of data stored in the third memory cell.
Similarly, Claims 1 and 2 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1 and 2 of commonly owned patent no 11,561,736. Although, the conflicting claims are not identical, they are not patentably distinct from each other.
Similarly, claims 3-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 3-19 of commonly owned patent no 11,561,736. Although, the conflicting claims are not identical, they are not patentably distinct from each
other.
Claim 1 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of commonly owned patent no. 11,086,573. Although, the conflicting claims are not identical, they are not patentably distinct from each other because as shown in the chart and explanation below:
Clm
Instant application
Clm
US Patent no. 11,561,736
1
A method of controlling a semiconductor memory device including a bit line, a plurality of memory cells, a first select transistor, a first select gate line, and a plurality of word lines, the memory cells being connected in series, the first select transistor being connected in series with the memory cells, the first select transistor being electrically connected to the bit line, the first select gate line being electrically connected to a gate of the first select transistor, each of the plurality of word lines being electrically connected to a gate of each of the plurality of memory cells, each of the plurality of memory cells being configured to store n-bit data, the n being an integer larger than or equal to three, the method comprising: in response to a first command, applying a first voltage to a first word line of the word lines, a second voltage to a second word line of the word lines and a third voltage to a third word line of the word lines to read data from a first memory cell of the memory cells as first data, the first word line being electrically connected to a gate of the first memory cell, the second word line being electrically connected to a gate of a second memory cell of the memory cells, the third word line being electrically connected to a gate of a third memory cell of the memory cells, the second memory cell being connected in series with the first memory cell, the third memory cell being connected in series with the second memory cell; and in response to a second command, applying a fourth voltage to the first word line, applying a fifth voltage to the second word line, and applying a sixth voltage to the third word line, wherein the n-bit data corresponds to a first through a 2n-th threshold voltage ranges, the (i+1)-th threshold voltage range is greater than the i-th threshold voltage range, the i being an integer larger than or equal to one and smaller than or equal to (2n-1), the first voltage is at least one of first through (2n -1)- th threshold voltages, the j-th threshold voltage is a boundary voltage between the j-th threshold voltage range and the (j+1) threshold voltage range, the being an integer larger than or equal to one and smaller than or equal to (2n -1), and each of the second through the sixth voltages is larger than the (2ⁿ-1)-th threshold voltage.
1
A memory system comprising: a semiconductor memory device including a bit line, a plurality of memory cells, a first select transistor, a first select gate line, and a plurality of word lines, the memory cells being connected in series, the first select transistor being connected in series with the memory cells, the first select transistor being electrically connected to the bit line, the first select gate line being electrically connected to a gate of the first select transistor, each of the plurality of word lines being electrically connected to a gate of each of the plurality of memory cells; and a controller configured to send a first command to the semiconductor memory device and send a second command to the semiconductor memory device, wherein in response to the first command, the semiconductor memory device applies a first voltage to a first word line of the word lines, a second voltage to a second word line of the word lines and a third voltage to a third word line of the word lines to read data from a first memory cell of the memory cells, and sends the read data as first data to the controller, the first word line being electrically connected to a gate of the first memory cell, the second word line being electrically connected to a gate of a second memory cell of the memory cells, the third word line being electrically connected to a gate of a third memory cell of the memory cells, the second memory cell being connected in series with the first memory cell, the third memory cell being connected in series with the second memory cell, in response to the second command, the semiconductor memory device applies a fourth voltage to the first word line, applies a fifth voltage to the second word line, and applies a sixth voltage to the third word line after sending the first data, the first memory cell is turned on by the applying the fourth voltage regardless of data stored in the first memory cell, the second memory cell is turned on by the applying the second voltage regardless of data stored in the second memory cell, the second memory cell is turned on by the applying the fifth voltage regardless of data stored in the second memory cell, the third memory cell is turned on by the applying the third voltage regardless of data stored in the third memory cell, and the third memory cell is turned on by the applying the sixth voltage regardless of data stored in the third memory cell.
Similarly, claims 2-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 2-19 of commonly owned patent no 11,086,573. Although the conflicting claims are not identical, they are not patentably distinct from each other.
Closest Prior Arts of Record
Darragh et al., U.S. Publication 2017/0221573 (herein Darragh) teaches: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.
Darragh fails to disclose a “second command” as claimed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Takada; Marie et al. US 10635354 B2
Fifield; John A. et al. US 10446239 B1
MAEJIMA; Hiroshi US 20190146685 A1
Darragh; Neil Richard et al. US 20170221573 A1
Cohen; Earl T. et al. US 20170206979 A1
Chen; Shih-Hsien et al. US 9384815 B2
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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