Prosecution Insights
Last updated: July 17, 2026
Application No. 19/212,655

ADAPTIVE MEMORY ADDRESS COMPUTATION BASED ON TENSOR DIMENSIONS

Non-Final OA §112
Filed
May 19, 2025
Priority
Jul 16, 2024 — provisional 63/671,776
Examiner
VICARY, KEITH E
Art Unit
2183
Tech Center
2100 — Computer Architecture & Software
Assignee
Tenstorrent Usa Inc.
OA Round
3 (Non-Final)
58%
Grant Probability
Moderate
3-4
OA Rounds
2y 9m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 58% of resolved cases
58%
Career Allowance Rate
398 granted / 690 resolved
+2.7% vs TC avg
Strong +41% interview lift
Without
With
+41.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
36 currently pending
Career history
732
Total Applications
across all art units

Statute-Specific Performance

§101
7.4%
-32.6% vs TC avg
§103
48.1%
+8.1% vs TC avg
§102
7.1%
-32.9% vs TC avg
§112
33.0%
-7.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 690 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-5, 7-13, and 15-29 are pending in this office action and presented for examination. Claims 3-4, 7, 11, 17, 19-22, 26, and 28 are newly amended by the response received March 19, 2026. In paragraph [0054] as amended, “section” appears to be newly added without appropriate underlining. Specification The disclosure is objected to because of the following informalities. Appropriate correction is required. In amended paragraph [0054], line 1, the “selection section” portion of “the first tile selection section address logic pipeline” does not appear to track other instances of similar language; it is unclear as to whether “selection” was intended to be deleted. Drawings The drawings are objected to because: MPEP 608.02, section V, states that “[l]ead lines are required for each reference character except for those which indicate the surface or cross section on which they are placed. Such a reference character must be underlined to make it clear that a lead line has not been left out by mistake." In FIG. 4, reference characters 301 and 400 appear to be indicate a same surface section. In addition, reference character 301 appears to be associated with both an underline and a lead line. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 19-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 19 recites the limitation “selecting a tile section address logic pipeline from a first address logic pipeline and a fast address logic pipeline based on the tensor dimension, the fast address logic pipeline being faster than the first address logic pipeline for a set of tensor dimensions” in lines 5-8. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., FIG. 7, steps 712 and 714) does not appear to provide support for selecting a tile section address logic pipeline from a first address logic pipeline and a fast address logic pipeline. Claim 19 recites the limitation “inputting, into the selected tile section address logic pipeline, an unpack instruction” in line 9. However, the original disclosure (e.g., FIG. 7, step 714) does not appear to provide support for this limitation. Claim 19 recites the limitation “outputting, from the selected tile section address logic pipeline and based on the unpack instruction, an address output” in lines 10-11. However, the original disclosure (e.g., FIG. 7, step 716) does not appear to provide support for this limitation. Claim 20 is rejected for failing to alleviate the rejections of claim 19 above. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 19 recites the limitation “selecting a tile section address logic pipeline from a first address logic pipeline and a fast address logic pipeline based on the tensor dimension” in lines 5-6. However, the metes and bounds of this limitation are indefinite. For example, it is indefinite as to whether the recited first address logic pipeline is a tile section address logic pipeline. For example, it is indefinite as to whether the recited fast address logic pipeline is a tile section address logic pipeline. Claim 20 is rejected for failing to alleviate the rejection of claim 19 above. Claim 20 recites the limitation “The method of claim 19, further comprising: selecting the tile section address logic pipeline from one of a first tile section address logic pipeline and a fast tile section address logic pipeline based on the tensor dimension, wherein the fast tile section address logic pipeline is faster than the first tile section address logic pipeline for the set of tensor dimensions; inputting, into the selected tile section address logic pipeline, the tensor dimension; and outputting, by the selected tile section address logic pipeline and based on the tensor dimension, a tile section address output; wherein generating the memory address is based on the tile section address output” in lines 1-11. Claim 19, upon which claim 20 is dependent, recites the limitation “selecting a tile section address logic pipeline from a first address logic pipeline and a fast address logic pipeline based on the tensor dimension, the fast address logic pipeline being faster than the first address logic pipeline for a set of tensor dimensions; inputting, into the selected tile section address logic pipeline, an unpack instruction; outputting, from the selected tile section address logic pipeline and based on the unpack instruction, an address output; and generating the memory address based on the address output” in lines 5-12. However, the metes and bounds of the aforementioned limitation of claim 20 are indefinite in the context of the aforementioned limitation of claim 19. For example, it is indefinite as to whether the tile section address logical pipeline is selected from a first address logic pipeline and a fast address logic pipeline, or from one of a first tile section address logic pipeline and a fast tile section address logic pipeline. The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. Claim 20 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Claim 20 recites the limitation “The method of claim 19, further comprising: selecting the tile section address logic pipeline from one of a first tile section address logic pipeline and a fast tile section address logic pipeline based on the tensor dimension, wherein the fast tile section address logic pipeline is faster than the first tile section address logic pipeline for the set of tensor dimensions; inputting, into the selected tile section address logic pipeline, the tensor dimension; and outputting, by the selected tile section address logic pipeline and based on the tensor dimension, a tile section address output; wherein generating the memory address is based on the tile section address output” in lines 1-11. Claim 19, upon which claim 20 is dependent, recites the limitation “selecting a tile section address logic pipeline from a first address logic pipeline and a fast address logic pipeline based on the tensor dimension, the fast address logic pipeline being faster than the first address logic pipeline for a set of tensor dimensions; inputting, into the selected tile section address logic pipeline, an unpack instruction; outputting, from the selected tile section address logic pipeline and based on the unpack instruction, an address output; and generating the memory address based on the address output” in lines 5-12. However, claim 20 fails to include all the limitations of the claim upon which it depends, because claim 20 no longer requires selecting a tile section address logic pipeline from a first address logic pipeline and a fast address logic pipeline, which is recited in claim 19; rather, claim 20 instead requires selecting the tile section address logic pipeline from one of a first tile section address logic pipeline and a fast tile section address logic pipeline. Allowable Subject Matter Claims 1-5, 7-13, 15-18, and 21-29 are allowed. Response to Arguments Applicant on page 16 argues: “While these informalities were addressed in an earlier response, the removal of the hyphens was previously indicated via strikethrough. For clarity, the updated marked specification indicates the removal of the hyphens identified in paragraph [0029] with double brackets in accordance with MPEP 714 and 37 CFR 1.121.” In view of the aforementioned amendments, the previously presented objections to the specification are withdrawn. Applicant across pages 16-17 argues: ‘Additionally, a typographical error has been corrected in paragraphs [0052], [0054]- [0057], [0068], [0069], and [0073]. For example, in paragraph [0052], the phrase "the first tile selection address logic pipeline" and "the fast tile selection address logic pipeline" have been amended to recite "the first tile section address logic pipeline and the fast tile section address logic pipeline" (emphases added). The Applicants submit that these specification amendments are limited to the correction of typographical errors and do not constitute the addition of new subject matter. In each instance, the intended wording would have been apparent from the original disclosure as filed.’ Examiner agrees with Applicants that the aforementioned amendments merely appear to correct typographical errors. Applicant on page 17 argues: “In response, Figures 3 and 4 have been amended as recommended by the Examiner. For example, lead lines have been added, and underlines have been removed from letters and numbers that are not reference characters. Underlines have also been removed from reference characters that do not, in fact, refer to a surface or cross section.” In view of the aforementioned amendments, most previously presented objections to the drawings are overcome — see the drawings section above for a lingering issue and a newly catalyzed issue. Applicant on page 18 argues: ‘Additionally, Figures 5 and 7 have been amended to correct a typographical error. For example, "Fast Tile Selection Address Logic Pipeline" at 502 has been amended to recite "Fast Tile Section Address Logic Pipeline" (emphases added). Similar amendments have been made at 512 of Figure 5 and at 708 and 710 of Figure 7.’ Examiner agrees with Applicants that the aforementioned amendments merely appear to correct typographical errors. Applicant on page 18 argues: “To address this issue, a typographical error has been corrected in the specification, in Figures 5 and 7, and in claims 19 and 20. For example, "a tile selection address logic pipeline" in claim 19 has been amended to recite "a tile section address logic pipeline" (emphases added). Similar amendments have been made throughout claims 19 and 20.” However, the aforementioned amendments do not appear to wholly overcome the written description issue — see the Claim Rejections - 35 USC § 112 section above. Applicant across pages 18-19 argues: ‘The Office Action specifically rejected claim 19 for a lack of support for the previously-recited limitation "selecting a tile selection address logic pipeline from one of a first address logic pipeline or a fast address logic pipeline based on the tensor dimension, the fast address logic pipeline being faster than the first address logic pipeline for a set of tensor dimensions." However, the amended specification provided herewith does provide support for the amended limitation in claim 19, "selecting a tile section address logic pipeline from one of a first address logic pipeline or a fast address logic pipeline based on the tensor dimension, the fast address logic pipeline being faster than the first address logic pipeline for a set of tensor dimensions" (emphasis added). For example, paragraph [0067] recites that "at step 706, either a first tile section address logic pipeline or a fast tile section address logic pipeline may be selected based on the tensor dimension (e.g., determined at step 704)." Since both the first tile section address logic pipeline and the fast tile section address logic pipeline may be considered to be tile section address logic pipelines, the amended limitation from claim 19, "selecting a tile section address logic pipeline," is now fully supported by the amended specification.’ However, the reproduced portion of paragraph [0067] is directed to “a first tile section address logic pipeline” and “a fast tile section address logic pipeline”, whereas the cited portion of claim 19 merely recites “a first address logic pipeline” and “a fast address logic pipeline”. Applicant on page 19 argues: ‘Claims 3 and 7 were rejected for the limitation "a configuration register storing a tensor dimension for the tensor," since claim 1 now recites the phrase "a tensor dimension of the tensor." The antecedent basis has now been corrected in claims 3 and 7 to clarify that the tensor dimension recited in claims 3 and 7 refers to the same tensor dimension introduced in claim 1. These amendments also remove any indefiniteness of claims 4, 5, 11, and 12, which also refer to the same tensor dimension as recited in claim 1.’ In view of the aforementioned amendments, the associated previously presented indefinite rejections are withdrawn. Applicant on page 19 argues: ‘Claims 4, 11, 17, 26, and 28 were rejected for reciting the limitation "a common dimension." The Examiner alleges that "it would not be clear to a hypothetical person possessing the ordinary level of skill in the pertinent art whether a particular dimension would be considered to be 'common."' Although the Applicants respectfully believe the pending claim language would have been understood by a person of ordinary skill in the art, the Applicants have amended the claims to further clarify the recited phrase and facilitate examination. For example, claim 4 has been amended to specify that "the common dimension is a power of two." Similar amendments have been made to claims 11, 17, 26, and 28. Support for these amendments can be found throughout the specification, including at least at paragraphs [0037], [0040], [0042], [0046], [0047], [0050], and [0053].’ In view of the aforementioned amendments, the associated previously presented indefinite rejections are withdrawn. Applicant across pages 19-20 argues: ‘Finally, the Applicants appreciate the Examiner's observations regarding claims 19 and 20. The issues noted in the § 112(b) rejection of claims 19 and 20 arose from a typographical error, namely, the recitation of 'selection' instead of 'section' in the phrase "tile section address logic pipeline." Claims 19 and 20 have been amended to correct this error, which the Applicants respectfully submit resolves the Examiner's indefiniteness concerns.’ Various facets of the aforementioned indefinite rejections are overcome in view of the aforementioned amendments; however, various facets of the aforementioned indefinite rejections remain applicable — see the Claim Rejections - 35 USC § 112 section above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH E VICARY whose telephone number is (571)270-1314. The examiner can normally be reached Monday to Friday, 9:00 AM to 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571)270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEITH E VICARY/ Primary Examiner, Art Unit 2183
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Prosecution Timeline

May 19, 2025
Application Filed
Dec 05, 2025
Non-Final Rejection mailed — §112
Feb 05, 2026
Response Filed
Mar 05, 2026
Final Rejection mailed — §112
Mar 19, 2026
Request for Continued Examination
Mar 24, 2026
Response after Non-Final Action
Jun 17, 2026
Non-Final Rejection mailed — §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
58%
Grant Probability
99%
With Interview (+41.1%)
3y 11m (~2y 9m remaining)
Median Time to Grant
High
PTA Risk
Based on 690 resolved cases by this examiner. Grant probability derived from career allowance rate.

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