DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
This Office Action is sent in response to Applicant’s Communication received on 05/20/2025 for application number 19/213,294.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “chiplet synchronization module” in claim 10.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7, 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "respective module control signal" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 18 recites the limitation "the same order" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 11, 15-17, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Aronheim et al. (US 2025/0062610 A1) in view of Karnik et al. (US 2003/0176982 A1).
Regarding claim 1, Aronheim teaches An electronic device (Figure 1), comprising:
a control signal interface configured to provide control data indicating one or more dynamic current characteristics of a load component (“as shown in FIG. 2 , controller 232 may be configured to receive the event indications 220 from the IC 210, for example, via an event-indications bus [control signal interface], and/or via any other suitable communication interface.” Par 0191 and “the digital integrated circuit 210 may be configured to generate one or more event indications 220 [control data], for example, to indicate one or more predefined events, which may be associated with current demand changes [dynamic current characteristics], e.g., instant current demand changes, of the integrated circuit 210 [load component].” Par 0190); and
a load controller coupled to the control signal interface, the load controller configured to generate, based on the control data, a plurality of load control signals that are synchronized according to a temporal pattern (“as shown in FIG. 2 , controller 232 [load controller] may be configured to receive the event indications 220 from the IC 210, for example, via an event-indications bus [control signal interface], and/or via any other suitable communication interface.” Par 0191 and “ controller 232 may be configured to generate the control signals 234 [load control signals] to control the activation/de-activation of the artificial load 236, for example, based on the digital integrated circuit event indications 220, e.g., provided by the integrated circuit 210,” par 0195 and “controller 432 (FIG. 4 ) may be configured to selectively activate the banks 437 (FIG. 4 ), for example, according to the load current pattern 500.” Par 0246 and par 267 and Fig. 1-2, 5) [this shows generating control signals (load control signals) to synchronize load activations based on a load current pattern (temporal pattern)].
However, Aronheim does not explicitly teach a clock signal interface configured to provide an operating clock signal; a set of load modules coupled to the clock signal interface and the load controller, each load module configured to, based on a respective load control signal, generate an output signal that switches with respect to a plurality of clock edges of the operating clock signal; and wherein the load controller is configured to control the set of load modules via the plurality of load control signals to generate respective output signals according to the temporal pattern, thereby allowing the set of load modules to operate jointly with respect to the plurality of clock edges to emulate the dynamic current characteristics of the load component.
In the analogous art, Karnik teaches a clock signal interface configured to provide an operating clock signal (“An input for selecting an external clock signal may be provided to synchronize the current sink 200 with test equipment or other current sinks.” Par 0036 and “The clock output 213A of sink 501A is shown feeding the synchronization clock inputs 275 of the current sinks 501 via clock line 513 to synchronize the test-current waveforms.” Par 0048 and Figure 15) [the clock input line/clock input 275 (via line 513) corresponds to the clock singal interface and external clock signal/synchronization clock corresponds to the operating clock signal];
a set of load modules coupled to the clock signal interface and the load controller (“Referring back to FIG. 15, a plurality (having a number, N) of the programmable current sinks 501 [load modules], for example the staggered or pulsed type discussed above, may be distributed along the power supply grid for testing… The clock output 213A of sink 501A [load controller] is shown feeding the synchronization clock inputs 275 of the current sinks 501 via clock line 513 to synchronize the test-current waveforms.” Par 0048 and Figure 15) [the clock inputs 275 coupled via clock line 513 may correspond to the clock signal interface], each load module configured to, based on a respective load control signal, generate an output signal that switches with respect to a plurality of clock edges of the operating clock signal (“The drain of each transistor may be connected to the output 115 at which point the transistor sink currents are summed.” Par 0029 and “As a pulse propagates through the delay line, the sink elements 100 may be turned on in succession and then off in succession.” Par 0033 and “An input for selecting an external clock signal may be provided to synchronize the current sink 200 with test equipment or other current sinks.” Par 0036 and paragraph 44 and Figures 6, 10, 16) [clock edges correspond to the inputs 275 which synchronizers the pulse propagation through the delay line so that each sink element turns on and off to switch its current into the summed output; each load module generates its own output signal by drawing current at its output terminal when enabled before outputs are summed]; and
wherein the load controller is configured to control the set of load modules via the plurality of load control signals to generate respective output signals according to the temporal pattern, thereby allowing the set of load modules to operate jointly with respect to the plurality of clock edges to emulate the dynamic current characteristics of the load component (“The enable input, 110A, 110B, . . . 110N, of each sink element 100A, 100B, . . . 100N, may be connected to the output of its respective delay element, 201A, 201B [controlling load modules via control signals], . . . 201N. As a pulse propagates through the delay line, the sink elements 100 may be turned on in succession and then off in succession. [generating output signals based on temporal pattern]” Par 0033 and “The drain of each transistor may be connected to the output 115 at which point the transistor sink currents are summed.” Par 0029 and “The clock output 213A of sink 501A is shown feeding the synchronization clock inputs 275 of the current sinks 501 via clock line 513 to synchronize the test-current waveforms [operating jointly with clock edges to emulate dynamic current characteristics].” Par 0048).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Aronheim and Karnik before him before the effective filing date of the claimed invention, to have modified Aronheim to incorporate the teachings of Karnik to achieve more accurate modeling and testing of in die power distribution grid by distributing time varying loads along the grid according to circuit requirements. (Karnik, paragraph 23)
Regarding claim 2, Aronheim and Karnik teach the electronic device of claim 1. Aronheim further teaches wherein the load controller further comprises:
a load profile modulator coupled to the control signal interface (“controller 232 may be configured to tune and/or shape one or more artificial load profile parameters of the artificial load applied by load 236, for example, per event.” Par 0197) [the profile tuning and load shaping logic of the controller may correspond to the load profile modulator], the load profile modulator configured to select a subset of load modules by enabling a subset of load control signals corresponding to the subset of load modules and determine a switching time for each of the subset of load modules (“the load controller 232 may be configured to control a load level of the load to be applied by artificial load 236 to the power supply 270 of the IC 210, for example, by selectively activating or de-activating load banks of the artificial load 236,” par 0179) [the controller generating control signals to selectively enable a subset of load banks and determine their respective start and end times for activation].
Karnik further teaches a set of programmable delay modules coupled to the load profile modulator (“The delay elements 201 (each of which may comprise two 20 pico-second-propagation-delay inverters to create a 40 pico-second delay) are connected to form a delay line. The delay select switches 202, which may be 1-to-2 demultiplexers, may route the output of each delay element to the next delay element or to OR gate 203.” Par 0033 and Figure 7) [the feedback/routing mechanism (switches and or gate 203) may correspond to the load profile modulator which controls the delay stages and modules the timing of the load profile], the set of programmable delay modules are configured to generate the plurality of load control signals based on the switching time of each of the subset of load modules (“The enable input, 110A, 110B, . . . 110N, of each sink element 100A, 100B, . . . 100N, may be connected to the output of its respective delay element, 201A, 201B, . . . 201N. As a pulse propagates through the delay line, the sink elements 100 may be turned on in succession and then off in succession.” Par 0033) [each delay element corresponds to a enable control signal that triggers its respective current sink element in sequential order according to its propagation delay switching time].
Regarding claim 3, Aronheim and Karnik teach the electronic device of claim 1. Aronheim further teaches wherein the plurality of load control signals include a first subset of load control signals (“the load controller 232 may be configured to activate a first set of one or more load banks of the artificial load 236, for example, to apply a first load level to the power supply 270 of the IC 210.” Par 0180), and each of the first subset of load control signals is configured to select a respective load module to operate with a respective switching time of the respective load module (“controller 232 may be configured to generate control signals 234 to control a start time and/or end time of an activation of the artificial load 236 at various magnitudes, e.g., as described below.” Par 0194 and “ the plurality of banks of the load array 238 may be operated by controller 232, e.g., activated or deactivated, separately and/or independently,” par 0219) [the individual start/end time for activating each load bank corresponds to the respective switching time for each respective load module].
Regarding claim 4, Aronheim and Karnik teach the electronic device of claim 3. Karnik further teaches wherein the first subset of load control signals are applied to enable a subset of load modules according to an ordered sequence based on their respective switching times (“The enable input, 110A, 110B, . . . 110N, of each sink element 100A, 100B, . . . 100N, may be connected to the output of its respective delay element, 201A, 201B, . . . 201N. As a pulse propagates through the delay line, the sink elements 100 may be turned on in succession and then off in succession.” Par 0033) [outputs from the sequential delay elements make enable inputs (control signals) activate each current sink element (load module) in a time-ordered sequence], and currents of the subset of load modules are gradually aggregated to provide a stair-like current ramping profile (“Referring to FIG. 3, six time-staggered vertically stacked rectangular areas representing the current presented by each current sink element, Is 1-Is6, to the power supply under test are shown.” Par 0026 and Figures 3, 4) [aggregating individual currents from time-staggered sink elements creates a step like current ramping profile as shown in Fig. 3].
Regarding claim 5, Aronheim and Karnik teach the electronic device of claim 1. Aronheim further teaches wherein the plurality of load control signals include a second subset of load control signals, and each of the second subset of load control signals is configured to disable the respective load module (“the load controller 232 may be configured to control a load level of the load to be applied by artificial load 236 to the power supply 270 of the IC 210, for example, by selectively activating or de-activating load banks of the artificial load 236,” par 0179 and “the plurality of banks of the load array 238 may be operated by controller 232, e.g., activated or deactivated, separately and/or independently,” par 0219 and “controller 232 may be configured to generate the control signals 234 to control the activation/de-activation of the artificial load 236,” par 0196) [second subset of control signals deactivates respective load modules by driving independent deactivation of specific load bank within the artificial load].
Regarding claim 6, Aronheim and Karnik teach the electronic device of claim 1. Karnik teaches wherein the clock signal interface further includes a clock generator configured to receive a reference clock signal (“The multiplexer 271 may include inputs 272A-272N for connection to a respective delay element 201A-201N, input 272ND connected to the output of the variable delay 251, input 275 for connection to an external clock, selector control lines 274, and an output 273.” Par 0042) and generate the operating clock signal based on the reference clock signal and the control data (“an external clock (e.g., from test equipment or from another current sink 200) may be provided on input 275 and selected using the selection lines 274.” Par 0042 and “A pulse generator 302 produces pulses having a duration set to determine the desired current pulse duration (e.g., the period to-t1 in FIG. 4) and a period set to determine the frequency (repetition rate) of the test-current waveform. The pulse generator may feed a delay line having a series of delay elements 301A-301N.” par 0043 and Figure 9, 14) [the pulse generator/delay-line oscillator loop (delay elements, inverter, mux, gate 203) corresponds to the clock generator which receives an external clock at input 275 (reference clock signal) and uses selection lines 274 (control data) to output the clock signal at 273 (operating clock signal)].
Regarding claim 11, Aronheim and Karnik teach the electronic device of claim 1. Karnik further teaches further comprising:
a power rail to which the set of load modules are coupled (“The outputs 115A, 115B, 115N of the sink elements 100 may be connected to the current sink output 215 (actually the element outputs 115 and the sink output 215 sink current and may be connected directly to the power supply grid being tested” par 0031 and Figure 15) [power supply grid 515 corresponds to the power rail]; and
a voltage drop monitoring component coupled to the power rail, wherein the voltage drop monitoring component is configured to generate a droop readout signal indicating a voltage drop at the power rail (“The oscillator waveform on the output of the inverter 204 may be used as a reference signal for making test measurements or for synchronizing other current sinks. Current sink 200 [voltage drop monitoring component] may therefore supply a controllable periodic load current with a synchronization signal for transient testing, such as droop detection [voltage drop at the power rail].” Par 0035) [current sink circuitry uses internal delay line oscillator signal (inverter 204) as a reference for monitoring transient voltage droop detection].
Regarding claim 15, Aronheim and Karnik teach the electronic device of claim 11. Aronheim further teaches wherein the electronic device is electrically coupled to a power management integrated circuit (PMIC) via the power rail (“the power supply 170 may be implemented with the integrated circuits 110 according to a System in Package (SiP) integration level, e.g., on a same package.” Par 0049 and “as shown in FIG. 2 , the artificial load 236 may be connected to the power supply 270, for example, in parallel to the IC 210.” Par 0170 and Figure 1).
Karnik further teaches and power performance of the PMIC is determined based on the droop readout signal (“Current sink 200 may therefore supply a controllable periodic load current with a synchronization signal for transient testing, such as droop detection.” Par 0035 and “In operation, the scan data chain for programming the current level of each sink element 100 may be loaded first and then the power supply performance [PMIC performance] may be observed.” Par 0044) [the test current sink uses an oscillator /synchronization signal as a reference during transient droop detection to determine overall performance of power supply system].
Regarding claim 16, Aronheim and Karnik teach the electronic device of claim 1. Aronheim further teaches wherein the electronic device is electrically coupled to a PMIC or a semiconductor package via a power rail of the set of load modules (“the power supply 170 may be implemented with the integrated circuits 110 according to a System in Package (SiP) integration level, e.g., on a same package.” Par 0049 and “as shown in FIG. 2 , the artificial load 236 may be connected to the power supply 270, for example, in parallel to the IC 210.” Par 0170 and Figure 1).
Regarding claim 17, Aronheim and Karnik teach the electronic device of claim 1. Aronheim further teaches wherein the one or more dynamic current characteristics of the load component includes one or more of: an amplitude, a ramping rate, and a waveform shape of a current transient profile (“artificial load profile parameters [current transient profile] of the artificial load may include, for example, a gradual start duration, e.g., an “on” slew rate, an active duration, an active magnitude [amplitude], a gradual end duration, e.g., an “off” slew rate [ramping rate], and/or any other additional or alternative parameter of the artificial load 236.” Par 0198 and “determine based on the current consumption event at least one of a timing of the event-based load, a load magnitude of the event-based load, a load duration of the event-based load, a slew rate of the event-based load [ramping rate], a start time of the event-based load, or an end time of the event-based load.” Par 0350).
Regarding claim 19, Aronheim and Karnik teach the electronic device of claim 1. Karnik further teaches wherein the set of load modules includes a plurality of load modules (“the programmable current sink further comprises a plurality of sink elements.” Claim 15 and Figure 9, 15), and the plurality of load modules are controlled by the plurality of load control signals to switch simultaneously with respect to each of the plurality of clock edges (“The NAND gates, 102A-102N, each may have one input driven by a common enable control line 110” par 0029 and “The clock output 213A of sink 501A is shown feeding the synchronization clock inputs 275 of the current sinks 501 via clock line 513 to synchronize the test-current waveforms.” Par 0048 and paragraphs 30-32) [current sink elements (load modules) and transistors are driven in parallel by common control signal 110 to switch simultaneously according to clock edges provided by clock inputs 275/113].
Regarding claim 20, Aronheim and Karnik teach the electronic device of claim 1, wherein the set of load modules includes a first set of load modules coupled to a first power rail, and the electronic device further includes a second set of load modules coupled to a second power rail (“the current consumption adjuster is configured to adjust the current consumption from the power supply based on current consumption events corresponding to a plurality of integrated circuits, e.g., in parallel to the power supply.” Par 0348) [the first power rail corresponds to the power supply branch providing power to the first IC domain, the second power rail corresponds to the parallel power supply rail branch providing power to the second IC domain], and wherein the first set of load modules and the second set of load modules are configured to operate concurrently to emulate the dynamic current characteristics of the first power rail and the second power rail of the load component, respectively (“controller is configured to identify a plurality of at least partially-overlapping current consumption events comprising a first current consumption event corresponding to a first integrated circuit and a second current consumption event corresponding to a second integrated circuit, wherein the second current consumption event at least partially overlaps in time with the first current consumption event, wherein the controller is configured to control activation of the controllable load circuitry to apply the event-based load based on the plurality of at least partially-overlapping current consumption events.” Par 0349) [the controller manages load circuitry across parallel IC power supply branches, activates load in response to overlapping current consumption events to concurrently emulate dynamic current characteristics of both rails].
Claims 7 are rejected under 35 U.S.C. 103 as being unpatentable over Aronheim and Karnik in view of Hsieh et al. (US 2023/0037496 A1).
Regarding claim 7, Aronheim and Karnik teach the electronic device of claim 1. However, Aronheim and Karnik do not explicitly teach wherein each load module further includes one or more flip-flop circuits coupled to one another in parallel, and is configured to operate according to the operating clock signal during a duty cycle defined according to the respective module control signal.
In the analogous art, Hsieh teaches wherein each load module further includes one or more flip-flop circuits coupled to one another in parallel, and is configured to operate according to the operating clock signal during a duty cycle defined according to the respective module control signal (“FIG. 2 is a schematic diagram illustrating the load generation circuit 210. The load generation circuit 210 includes a flip-flop FF1, a flip-flop FF2, a flip-flop FF3” par 0019 and “The flip-flop FF1 has an input terminal D, an output terminal Q, a clock receiving terminal C and a reset terminal R. The flip-flop FF1 is turned on or off by the reset terminal R by receiving the reset signal Sr 1. When the reset signal Sr 1 has the first logic level, the flip-flop FF1 is turned on and consumes the power [active duty cycle] provided by the supply current I.” par 0021 and “the flip-flop FF1, the flip-flop FF2, the flip-flop FF3… alternately using different load configurations as the current load of the load generation circuit 210, according to the clock period of the clock signal CLK when the flip-flop FF1, the flip-flop FF2, and the flip-flop FF3 are activated.” Par 0024 and “the current load circuit 200 includes a plurality of load generation circuits, e.g., the load generation circuit 210 and a load generation circuit 211 that are arranged in parallel” par 0032 and Figure 4) [the flip flops within the load generation circuits are driven by CLK to draw current during the active duty cycle defined by the control reset signal (Sr1)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Aronheim, Karnik and Hsieh before him before the effective filing date of the claimed invention, to have modified Aronheim and Karnik to incorporate the teachings of Hsieh to include flip flops that operate according to the clock signal during an active duty cycle to effectively test the performance of power supply circuits. (Hsieh, paragraph 3)
Claims 8-10, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Aronheim and Karnik in view of Hazucha et al. (US 2006/0224337 A1).
Regarding claim 8, Aronheim and Karnik teach the electronic device of claim 1. However, Aronheim and Karnik do not explicitly teach further comprising: a first chiplet on which the control signal interface, the clock signal interface, the load controller, and the set of load modules are integrated and formed; and one or more second chiplets distinct from the first chiplet, the one or more second chiplets configured to operate in synchronization with the first chiplet to emulate the dynamic current characteristics of the load component.
In the analogous art, Hazucha teaches a first chiplet on which the control signal interface, the clock signal interface, the load controller, and the set of load modules are integrated and formed; and one or more second chiplets distinct from the first chiplet (“The outputs 407 of the multiplexers 406 are used to enable or disable current produced by programmable current sink elements 402. As explained in … FIGS. 6 and 7, each current sink 402 is capable of producing a pulse of current with an amplitude determined by the selection inputs sel[3:0].” Par 0027 and “When an input signal is applied to programmable current load 400 via dall or din, the signal propagates to current enable inputs 404 through multiplexers 406.” Par 0028 and paragraph 44, Figure 4, 9C) [first chiplet may correspond to current load circuit 400c which includes selection inputs (control signal interface), input trigger signal din, dall (clock signal interface), mux delay line (load controller) and current sink elements 402 and switches 404 (load modules); the second chiplet may correspond to current load circuit 400d],
the one or more second chiplets configured to operate in synchronization with the first chiplet to emulate the dynamic current characteristics of the load component (“As shown in FIG. 9C, the output, dout, of one programmable current load 400 c is coupled to the din input of another programmable current load 400 d.” par 0044 and “simulating the high frequency transient characteristics of a microprocessor load,” par 0048) [the load component corresponds to the IC whose transient current demand is being simulated; the secondary load circuit synchronizes with the first load circuit by receiving the trigger output signal of the first circuit into its trigger input; the output trigger d_out driver input d_in of second load in series, cascading the activation to sum the current outputs and emulate the dynamic current characteristics of the load component].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Aronheim, Karnik and Hazucha before him before the effective filing date of the claimed invention, to have modified Aronheim and Karnik to incorporate the teachings of Hazucha to emulate the dynamic current characteristics of the load component using distinct first and second chiplets to facilitate reliable power delivery systems and a cost-effective design. (Hazucha, paragraph 48)
Regarding claim 9, Aronheim, Karnik and Hazucha teach the electronic device of claim 8. Hazucha further teaches wherein each of the first and second chiplets is configured to obtain a respective chiplet control signal to control a respective chiplet delay offset with respect to a respective remainder set of chiplets (“each programmable current load 400 c, 400 d has its own dedicated set of selection inputs, thereby enabling production of current waveforms having up to twice the ramp length and twice the amplitude of a single programmable current load 400.” Par 0044 and “The selection inputs b[4:0] [chiplet control signals] are used to select the amount of delay [delay offset] experienced by the input pulse before it reaches the enable inputs of current sinks 402.” Par 0043) [each load circuit has its own selection inputs to set the propagation delay offset before activating its current sinks relative to the remaining load circuits].
Regarding claim 10, Aronheim and Karnik teach the electronic device of claim 1. However, Aronheim and Karnik do not explicitly teach further comprising a chiplet synchronization module configured to obtain a first chiplet control signal and generate a first chiplet delay offset common to the respective output signals of the set of load modules, each respective output signal further having a respective module-level delay offset controlled by the respective load control signal.
In the analogous art, Hazucha teaches a chiplet synchronization module configured to obtain a first chiplet control signal (“The selection inputs b[4:0] are used to select the amount of delay experienced by the input pulse before it reaches the enable inputs of current sinks 402.” Par 0043) [the multiplexer delay chain (chiplet synchronization module) receives the selection inputs (chiplet control signal) to determine propagation timing] and generate a first chiplet delay offset common to the respective output signals of the set of load modules (“The delay between the input signal and the current waveform seen by power supply 403 is determined by the time it takes a signal to propagate from either dall or din to the enable inputs 404 of the current sink elements 402.” Par 0028 and “each programmable current load 400 c, 400 d has its own dedicated set of selection inputs, thereby enabling production of current waveforms having up to twice the ramp length and twice the amplitude of a single programmable current load 400.” Par 0044) [total propagation delay though mux series determines common delay offset across all current sink load modules in the chiplet], each respective output signal further having a respective module-level delay offset controlled by the respective load control signal (“adding one or more variable (e.g., selectable) delay elements between multiplexers 406 and current sinks/switches 402/404. Providing a variable on time for each current sink can increase the versatility of the current load 400” Par 0041 and Figure 4, 9C) [the individual delay elements between each mux output and its corresponding current sink provides module-level delay offset].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Aronheim, Karnik and Hazucha before him before the effective filing date of the claimed invention, to have modified Aronheim and Karnik to incorporate the teachings of Hazucha to include a chip synchronization module to facilitate reliable power delivery systems and a cost-effective design. (Hazucha, paragraph 48)
Regarding claim 18, Aronheim and Karnik teach the electronic device of claim 17. However, Aronheim and Karnik do not explicitly teach wherein a first ramping rate of a first current transient profile is greater than a current ramping rate of a second current transient profile, and a set of first load modules is enabled according to the same order and different switching times to emulate both the first current transient profile and the second current transient profile, at least one of the set of first load modules having an earlier switching time for the first current transient profile than that for the second current transient profile.
In the analogous art, Hazucha teaches wherein a first ramping rate of a first current transient profile is greater than a current ramping rate of a second current transient profile (“By programming the selection inputs b[4:0], the ramp time of the current waveform can be controlled, as illustrated in FIGS. 5A-5E.” par 0028 and “in FIG. 10, waveform 902 would result from setting b[4:0] to 11111. Similarly, successively longer ramp times can be selected using the b[4:0] inputs, as illustrated by waveforms 904, 906, 908, and 910.” Par 0045) [the steeper current rise/faster waveform corresponds to the first ramping rate for the first profile; a shorter ramp time configuration has a steeper current slope, whereas configuring selection inputs for longer ramp times produces a flatter current slope (current ramping rate of a second transient profile); waveform 902 may correspond to the first current transient profile], and a set of first load modules is enabled according to the same order and different switching times to emulate both the first current transient profile and the second current transient profile (“When an input signal is applied to programmable current load 400 via dall or din, the signal propagates to current enable inputs 404 through multiplexers 406.” Par 0028 and “The selection inputs b[4:0] are used to select the amount of delay experienced by the input pulse before it reaches the enable inputs of current sinks 402.” Par 0043 and “The current amplitude setting has been kept constant by setting sel[3:0] to a constant value, and the ramp time has been varied by varying b[4:0].” Par 0045) [the input trigger pulses propagates through the mux chain to enable same set of current sink load modules in sequential order; the selection inputs alter the propagation delay in each stage that has different switching times; by changing the individual switching times, the overall ramp time of the current waveform is varied, allowing the circuit to emulate the current transient profiles], at least one of the set of first load modules having an earlier switching time for the first current transient profile than that for the second current transient profile (“The delay between the input signal and the current waveform seen by power supply 403 is determined by the time it takes a signal to propagate from either dall or din to the enable inputs 404 of the current sink elements 402.” Par 0028 and “As shown in FIG. 5A, if b[4:0]=11111, all of the multiplexers 406 in FIG. 4 couple dall directly to their outputs 407. Thus, upon receiving a trigger pulse on dall, all of the current sink elements 402 will turn on substantially simultaneously” par 0030) [bypassing the mux delay stages allows the trigger pulse to be directly delivers to current sink enable inputs, causing load modules to switch on earlier for the fast profile versus when travelling through serial mix delays in longer ramp profiles].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Aronheim, Karnik and Hazucha before him before the effective filing date of the claimed invention, to have modified Aronheim and Karnik to incorporate the teachings of Hazucha to include a first transient profile that has a faster ramping rate than a second transient profile and enable the load modules to emulate the current transient profiles to facilitate reliable power delivery systems and a cost-effective design. (Hazucha, paragraph 48)
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Aronheim and Karnik in view of Mehra et al. (US 2019/0265767 A1).
Regarding claim 12, Aronheim and Karnik teach the electronic device of claim 11. However, Aronheim and Karnik do not explicitly teach wherein the voltage drop monitoring component includes a ring oscillator driven by the power rail, the voltage drop monitoring component configured to monitor a frequency of a periodic signal outputted by the ring oscillator and determine the droop readout signal based on the frequency of the periodic signal.
In the analogous art, Mehra teaches wherein the voltage drop monitoring component includes a ring oscillator driven by the power rail (“The detector 130A is electrically connected via the voltage sense line 212 to the local power bus 204 … The detector 130A includes the ring oscillator 206” par 0019), the voltage drop monitoring component configured to monitor a frequency of a periodic signal outputted by the ring oscillator and determine the droop readout signal based on the frequency of the periodic signal (“The ring oscillator 206 generates a count 214, which is a quantitative representation of the frequency of the periodic signal generated by the ring oscillator 206.” Par 0020 and “when the input voltage (e.g. the supply voltage being sent to the processor) falls due to a droop event, the ring oscillator's periodic signal decreases in frequency and creates a corresponding change in the count indicative of the droop.” Par 0010) [droop detector 130A monitors local power bus (204) using a ring oscillator (206) whose output frequency varies with voltage, generating a count signal 214 as a readout to detect voltage droop conditions].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Aronheim, Karnik and Mehra before him before the effective filing date of the claimed invention, to have modified Aronheim and Karnik to incorporate the teachings of Mehra to include a ring oscillator and monitor a frequency of a periodic signal to allow the processor to better and more efficiently respond to droop events. (Mehra, paragraph 10)
Regarding claim 13, Aronheim and Karnik teach the electronic device of claim 11. However, Aronheim and Karnik do not explicitly teach wherein the voltage drop monitoring component is configured to generate the droop readout signal in response to a command, according to a predefined schedule, periodically, or upon detection of a signature voltage change event.
In the analogous art, Mehra teaches wherein the voltage drop monitoring component is configured to generate the droop readout signal in response to a command, according to a predefined schedule, periodically, or upon detection of a signature voltage change event (“The compare module receives the count and generates an alert if the count falls below a predetermined threshold level.” Par 0016 and “Once a droop condition on the local power bus 204 appears, the periodic signal frequency of the ring oscillator 206 decreases and causes the count 214 to decrease. The compare module 208 compares the count 214 with the threshold value 216, and once the count drops below the threshold value 216, the compare module generates the response 210 that is sent to the clock control module 120.” Par 0022) [compare module of the droop detector generates an alert when ring oscillator frequency falls below a threshold upon detecting a droop event on the power line (signature voltage change event)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Aronheim, Karnik and Mehra before him before the effective filing date of the claimed invention, to have modified Aronheim and Karnik to incorporate the teachings of Mehra to generate a response to a signature voltage change event to allow the processor to better and more efficiently respond to droop events. (Mehra, paragraph 10)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Aronheim and Karnik in view of Paillet et al. (US 2007/0013414 A1).
Regarding claim 14, Aronheim and Karnik teach the electronic device of claim 11. However, Aronheim and Karnik do not explicitly teach further comprising: a first-in-first-out memory configured to store the droop readout signal, wherein the droop readout signal includes data samples corresponding to a signature voltage change event.
In the analogous art, Paillet teaches a first-in-first-out memory configured to store the droop readout signal (“The droop detectors 10 thus each produce n outputs, one for each sampling circuit, which are fed into the optional memory buffer or FIFO 12, which stores the outputs of the droop detectors 10 for further analysis.” Par 0023 and “The FIFO 12 receives the sampling information obtained from the α and β droop detectors.” Par 0024), wherein the droop readout signal includes data samples corresponding to a signature voltage change event (“the information received from the α and β droop detectors, including both droop events and non-droop events, is fed into the FIFO 12, which stores a predetermined number of samples. Once a droop event is identified by the combinational logic circuit 18, information continues to be stored in a first-in-first-out fashion until the droop event information is stored approximately in the middle of the FIFO ” Par 0025) [FIFO receives and stores continuous sampling output (droop readout signals) containing data samples captures before, during and after a signature voltage change event].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Aronheim, Karnik and Paillet before him before the effective filing date of the claimed invention, to have modified Aronheim and Karnik to incorporate the teachings of Paillet to include a FIFO memory to store the droop readout signals to overcome the concern that monitored droop events are unpredictable by guaranteeing the power grid is sampled continuously and systematically so that at least one sample captures the droop event. (Paillet, paragraph 46)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Lee et al. (US 2023/0152841 A1) teaches a semiconductor device that has an IP block and a clock management unit. The clock management unit receives a clock request signal, indicated whether the IP block requires a clock signal. Based on the signal, the clock management unit performs clock gating for the IP block. A critical path monitor checks the clock signal to adjust the frequency and voltage of the signal.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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