DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant is advised that should claim 1 be found allowable, claim 12 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claims 1, 12, and 19 are objected to because of the following informalities: “a first terminal” and “a second terminal” are each recited for a second time. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 11, 12, 18, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by In (US 2023/0206833 A1).
Instant Claim 1: A pixel (“FIG. 2 is a schematic diagram of an equivalent circuit illustrating an embodiment of the pixel included in the display device of FIG. 1.” (In, paragraph 69))
comprising: a first transistor comprising a gate connected to a first node, (“A first thin film transistor M1 (fig 2) may include … a gate electrode connected to a first pixel node N_G,” (In, paragraph 73) The first thin film transistor M1 and first pixel node N_G of In correspond to the first transistor and first node of the claim, respectively.)
a first terminal configured to receive a first power voltage, (“A first power voltage VDD may be applied to the first power line PL1,” (In, paragraph 70)
“A first thin film transistor M1 (or driving transistor) may include a first electrode connected to a second electrode of a fifth thin film transistor M5 (or the first power line PL1 through the fifth thin film transistor M5),” (In, paragraph 73) The first electrode of first thin film transistor M1 receiving first power voltage VDD (through fifth thin film transistor M5) corresponds to the first terminal of the claim.)
a second terminal connected to a second node, (“A first thin film transistor M1 (or driving transistor) may include … a second electrode connected to a second pixel node N_S,” (In, paragraph 73) The second electrode of first thin film transistor M1 and second pixel node N_S of In correspond to the second terminal and second node of the claim, respectively.)
and a body connected to a third node; (“The back-gate electrode may be disposed while overlapping with the gate electrode with an insulating layer interposed therebetween, comprise a body of the corresponding transistor,” (In, paragraph 73) Referring to fig 2 of In, the node connected to the body of first thin film transistor M1 corresponds to the third node of the claim.)
a second transistor configured to transmit a data signal to the third node in response to a write gate signal; (“The second thin film transistor M2 (fig 2) may be turned on in response to a write gate signal applied to the write gate line GWLn,” (In, paragraph 76) The second thin film transistor M2 of In corresponds to the second transistor of the claim.)
a third transistor configured to connect the first node to the second node in response to a compensation gate signal; (“The third thin film transistor M3 (fig 2) may be turned on in response to a compensation gate signal applied to the compensation gate line GRLn,” (In, paragraph 77) The third thin film transistor M3 of In corresponds to the third transistor of the claim.)
a first capacitor connected between the third node and a first voltage line configured to transmit a first voltage; (“The hold capacitor Chold (fig 2) may be disposed (or formed) or electrically connected between the first power line PL1 and the back-gate electrode of the first thin film transistor M1.” (In, paragraph 82) The hold capacitor Chold and first power line PL1 of In correspond to the first capacitor and first voltage line of the claim, respectively.)
a second capacitor connected between the first node and a second voltage line configured to transmit a second voltage; (“The storage capacitor Cst (fig 2) may be disposed (or formed) or electrically connected between the first pixel node N_G and the second pixel node N_S.” (In, paragraph 81) The storage capacitor Cst of In corresponds to the second capacitor of the claim.
“a fourth power voltage VINT (fig 2) (or initialization voltage) may be applied to the fourth power line PL4” (In, paragraph 70) The fourth power line PL4 of In corresponds to the second voltage line of the claim.)
and a light-emitting element comprising a first terminal connected to the second node, and a second terminal configured to receive a second power voltage. (“The light emitting element LD (fig 2) may be electrically connected between the second pixel node N_S and the second power line PL2,” (In, paragraph 83) Referring to fig 2 of In, the terminal of light emitting element LD directly connected to the second pixel node N_S corresponds to the first terminal of the claim.
“a second power voltage VSS (Fig 2) may be applied to the second power line PL2,” (In, paragraph 70) Referring to fig 2 of In, the terminal of light emitting element LD directly connected to the second power line PL2 corresponds to the second terminal of the claim.)
Instant Claim 11: The pixel of claim 1, further comprising a fourth transistor configured to transmit an initialization voltage to the second node in response to an initialization gate signal. (“A fourth thin film transistor M4 (or initialization transistor) may include a first electrode electrically connected to the second pixel node N_S, a second electrode electrically connected to the fourth power line PL4, and a gate electrode electrically connected to the initialization gate line GILn. The fourth thin film transistor M4 may be turned on in response to an initialization gate signal applied to the initialization gate line GILn.” (In, paragraph 78) The fourth thin film transistor M4 of In corresponds to the fourth transistor of the claim. The voltage transmitted by the fourth thin film transistor M4 corresponds to the initialization voltage of the claim.)
Instant Claim 12: (Claim 12 is identical to claim 1, and thus, is rejected under the same rationale.)
Instant Claim 18: (Claim 18 is identical to claim 11, and thus, is rejected under the same rationale.)
Instant Claim 19: An electronic apparatus comprising: a processor configured to generate input image data; (“A display device includes a data driver, a gate driver, and pixels.” (In, paragraph 3) The display device of In corresponds to the electronic apparatus of the claim.)
comprising: a processor configured to generate input image data; (“In the case of blocks, units, and/or modules implemented by microprocessors or other similar hardware, the units, and/or modules are programmed and controlled by using software, to perform various functions discussed in the disclosure, and may be selectively driven by firmware and/or software.” (In, paragraph 41) The microprocessor of In corresponds to the processor of the claim. The microprocessor generates image data for the display device.)
and a display device configured to display an image corresponding to the input image data, (“A display device includes a data driver, a gate driver, and pixels.” (In, paragraph 3))
the display device comprising: a display panel comprising pixels; (“A display panel includes pads and pixels,” (In, abstract))
a gate driver (“The display device may further include a gate driver that provides a gate signal to the pixels based on a start signal and a clock signal.” (In, paragraph 9))
configured to provide a write gate signal (“The second thin film transistor M2 (fig 2) may be turned on in response to a write gate signal applied to the write gate line GWLn,” (In, paragraph 76))
and a compensation gate signal to each of the pixels; (“The third thin film transistor M3 (fig 2) may be turned on in response to a compensation gate signal applied to the compensation gate line GRLn,” (In, paragraph 77))
a data driver configured to provide a data signal to each of the pixels; (“The display device may further include a data driver that provides data signals to the pixels.” (In, paragraph 10))
and a power management circuit configured to provide a first power voltage, a second power voltage, a first voltage, and a second voltage to each of the pixels, (“Referring to FIGS. 1 and 2, the pixel PXLnm may be electrically connected to a first power line PL1, a second power line PL2, a third power line PL3, and a fourth power line PL4.” (In, paragraph 70) The combination of power lines of In – and the power transmitted through these power lines - corresponds to the power management circuit of the claim.
The remainder of claim 19 is substantially identical to claim 1, and thus, is rejected under similar rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9, 10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over In.
Instant Claim 9: The pixel of claim 1, wherein the first transistor is a p-type metal oxide semiconductor (PMOS) transistor, and wherein each of the second transistor and the third transistor is an n-type metal oxide semiconductor (NMOS) transistor. (“Each of the thin film transistors M1 to M5 (fig 2) may be an N-type transistor. For example, each of the thin film transistors M1 to M5 may include an oxide semiconductor.” (In, paragraph 72) Although In does not explicitly teach the use of a PMOS transistor, by official notice PMOS transistors are widely used in the field of pixel technology and would be obvious to use with In.)
Instant Claim 10: The pixel of claim 1, wherein the first transistor is a PMOS transistor, and wherein at least one of the second transistor or the third transistor is a PMOS transistor. (“Each of the thin film transistors M1 to M5 (fig 2) may be an N-type transistor. For example, each of the thin film transistors M1 to M5 may include an oxide semiconductor.” (In, paragraph 72) Although In does not explicitly teach the use of a PMOS transistor, by official notice PMOS transistors are widely used in the field of pixel technology and would be obvious to use with In.)
Instant Claim 20: The electronic apparatus of claim 19, wherein the gate driver is configured to: sequentially provide the write gate signal to pixel rows; and concurrently provide the compensation gate signal to the pixel rows. (Although In does not explicitly teach the write gate signal and the compensation gate signal being provided sequentially or concurrently, it would be obvious to try both sequential and concurrent signaling as there are only those two choices.)
Allowable Subject Matter
Claims 2-8 and 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 2, the prior art of record fails to teach or fairly suggest “in a third node initialization period of an initialization period, each of the first power voltage, the first voltage, and the second voltage has a high level, the write gate signal has an activation level, and the data signal has a sustain voltage”.
Claims 3-8 depend on claim 2, and thus, contain the same allowable subject matter as claim 2.
With respect to claim 13, the prior art of record fails to teach or fairly suggest “in an initialization period, each of the first power voltage and the first voltage has a low level, and the compensation gate signal has an activation level”.
Claims 14-17 depend on claim 13, and thus, contain the same allowable subject matter as claim 13.
Conclusion
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/YARON COHEN/Examiner, Art Unit 2626
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