DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Applicant is advised that this Double Patenting rejection will not be held in abeyance. See MPEP § 804(I)(B)(1); 37 CFR § 1.111(b).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17, 19, 20 of U.S. Patent No. 12,332,723. Although the claims at issue are not identical, they are not patentably distinct from each other because all of the features of the instant claims can be found in the conflicting claims, and thus are anticipated by those claims.
Instant Claims
Claims of U.S. Patent 12,332,723
1. An apparatus comprising:
a plurality of integrated circuit dies that includes a first integrated circuit die and a second integrated circuit die that is associated with a set of agent circuits;
wherein the first integrated circuit die is configured to:
detect a latency event to be performed with respect to a memory associated with the plurality of integrated circuit dies;
determine read and write tolerance values for the latency event;
send the read and write tolerance values to the second integrated circuit die; and
block the latency event until at least an acknowledgment is received from the second integrated circuit die that the set of agent circuits is able to tolerate latencies corresponding to the read and write tolerance values.
1. A system, comprising: a plurality of integrated circuit dies coupled together, wherein the plurality of integrated circuit dies include a first and a second integrated circuit die that include respective processor circuitry, wherein the second integrated circuit die is associated with a set of agent circuits; wherein the first integrated circuit die is configured to: detect a latency event to be performed that affects an availability of a memory associated with the plurality of integrated circuit dies; determine read and write tolerance values for the latency event; send the read and write tolerance values to the second integrated circuit die; and block the latency event until at least an acknowledgment is received from the second integrated circuit die that the set of agent circuits is able to tolerate latencies corresponding to the read and write tolerance values.
2. The apparatus of claim 1, wherein the second integrated circuit die is configured to:
send the read and write tolerance values to the set of agent circuits;
based on tolerance information received from the set of agent circuits, make a determination that the set of agent circuits is able to tolerate the latencies; and
provide the acknowledgment to the first integrated circuit die based on the determination.
2. The system of claim 1, wherein the second integrated circuit die is configured to: send the read and write tolerance values to the set of agent circuits; based on tolerance information received from the set of agent circuits, make a determination that the set of agent circuits is able to tolerate the latencies; and provide the acknowledgment to the first integrated circuit die in response to the determination.
3. The apparatus of claim 1, wherein a particular agent circuit of the set of agent circuits includes a buffer and is configured to:
receive a read tolerance value of the read and write tolerance values; and
store an amount of data in the buffer based on the read tolerance value.
3. The system of claim 1, wherein a particular agent circuit of the set of agent circuits includes a buffer and is configured to: receive a read tolerance value of the read and write tolerance values; and based on the read tolerance value, store a sufficient amount of data in the buffer to prevent an underflow of the buffer due to the latency event.
4. The apparatus of claim 1, wherein a particular agent circuit of the set of agent circuits includes a buffer and is configured to:
receive a write tolerance value of the read and write tolerance values; and
evict an amount of data from the buffer that is based on the write tolerance value.
4. The system of claim 1, wherein a particular agent circuit of the set of agent circuits includes a buffer and is configured to: receive a write tolerance value of the read and write tolerance values; and based on the write tolerance value, evict a sufficient amount of data from the buffer to prevent an overflow of the buffer due to the latency event.
5. The apparatus of claim 1, wherein a particular agent circuit of the set of agent circuits is configured to send, to the second integrated circuit die, a minimum read tolerance value that indicates a latency for reads that can be tolerated by the particular agent circuit and a minimum write tolerance value that indicates a latency for writes that can be tolerated by the particular agent circuit.
5. The system of claim 1, wherein a particular agent circuit of the set of agent circuits is configured to send, to the second integrated circuit die, a minimum read tolerance value that indicates a latency for reads that can be tolerated by the particular agent circuit and a minimum write tolerance value that indicates a latency for writes that can be tolerated by the particular agent circuit.
6. The apparatus of claim 1, wherein the second integrated circuit die is configured to:
receive minimum read and write tolerance values from ones of the set of agent circuits;
determine minimum die read and write tolerance values for the second integrated circuit die based on the minimum read and write tolerance values received from the agent circuits; and
send the minimum die read and write tolerance values to the first integrated circuit die.
6. The system of claim 1, wherein the second integrated circuit die is configured to: receive minimum read and write tolerance values from ones of the set of agent circuits; determine minimum die read and write tolerance values for the second integrated circuit die based on the minimum read and write tolerance values received from the agent circuits; and send the minimum die read and write tolerance values to the first integrated circuit die.
7. The apparatus of claim 6, wherein the first integrated circuit die is configured to:
determine minimum system read and write tolerance values based on the minimum die read and write tolerance values of the second integrated circuit die; and
send the read and write tolerance values to the second integrated circuit die in response to a determination that the minimum system read and write tolerance values does not satisfy the read and write tolerance values determined for the latency event.
7. The system of claim 6, wherein the first integrated circuit die is configured to: determine minimum system read and write tolerance values based on the minimum die read and write tolerance values of the second integrated circuit die; and send the read and write tolerance values to the second integrated circuit die in response to a determination that the minimum system read and write tolerance values does not satisfy the read and write tolerance values determined for the latency event.
8. The apparatus of claim 7, wherein the first integrated circuit die is configured to:
receive minimum die read and write tolerance values from a third integrated circuit die of the plurality of integrated circuit dies, wherein the minimum system read and write tolerance values are determined based on the minimum die read and write tolerance values of the third integrated circuit die.
8. The system of claim 7, wherein the first integrated circuit die is configured to: receive minimum die read and write tolerance values from a third integrated circuit die of the plurality of integrated circuit dies, wherein the minimum system read and write tolerance values are determined based on the minimum die read and write tolerance values of the third integrated circuit die.
9. The apparatus of claim 1, wherein the first integrated circuit die includes a first power manager circuit that is configured to synchronize a power state change of the plurality of integrated circuit dies from a first power state to a second power state, and wherein the first power manager circuit is further configured to:
determine the read and write tolerance values;
send the read and write tolerance value to a second power manager circuit included in the second integrated circuit die; and
block the latency event until at least the acknowledgment is received.
9. The system of claim 1, wherein the first integrated circuit die includes a first power manager circuit that is configured to synchronize a power state change of the plurality of integrated circuit dies from a first power state to a second power state, and wherein the first power manager circuit is further configured to: determine the read and write tolerance values; send the read and write tolerance value to a second power manager circuit included in the second integrated circuit die; and block the latency event until at least the acknowledgment is received.
10. The apparatus of claim 1, wherein the first and second integrated circuit dies are copies of each other.
20. The non-transitory computer readable medium of claim 18, wherein the first and second integrated circuit dies are copies of each other.
11. A method, comprising;
detecting, by a first integrated circuit die of a plurality of integrated circuit dies, a latency event to be performed with respect to a memory associated with the plurality of integrated circuit dies;
determining, by the first integrated circuit die, read and write tolerance values;
sending, by the first integrated circuit die, the read and write tolerance values to a second integrated circuit die of the plurality of integrated circuit dies, wherein the second integrated circuit die is associated with a set of agent circuits; and
blocking, by the first integrated circuit die, the latency event until at least an acknowledgment is received from the second integrated circuit die that the set of agent circuits is able to tolerate latencies corresponding to the read and write tolerance values.
11. A method, comprising; detecting, by a first integrated circuit die of a plurality of integrated circuit dies coupled together, a latency event to be performed that affects an availability of a memory associated with the plurality of integrated circuit dies; determining, by the first integrated circuit die, read and write tolerance values to prevent instances of underflow and overflow due to the latency event; sending, by the first integrated circuit die, the read and write tolerance values to a second integrated circuit die of the plurality of integrated circuit dies, wherein the second integrated circuit die is associated with a set of agent circuits; and blocking, by the first integrated circuit die, the latency event until at least an acknowledgment is received from the second integrated circuit die that the set of agent circuits is able to tolerate latencies corresponding to the read and write tolerance values.
12. The method of claim 11, further comprising:
receiving, by the first integrated circuit die, minimum die read and write tolerance values associated with the second integrated circuit die; and
determining, by the first integrated circuit die, minimum system read and write tolerance values based on the minimum die read and write tolerance values, wherein the sending is performed in response to a determination that the minimum system read and write tolerance values does not satisfy the read and write tolerance values determined for the latency event.
12. The method of claim 11, further comprising: receiving, by the first integrated circuit die, minimum die read and write tolerance values associated with the second integrated circuit die; and determining, by the first integrated circuit die, minimum system read and write tolerance values based on the minimum die read and write tolerance values, wherein the sending is performed in response to a determination that the minimum system read and write tolerance values does not satisfy the read and write tolerance values determined for the latency event.
13. The method of claim 11, wherein the method is performed by a power manager circuit included in the first integrated circuit die, and wherein the power manager circuit is configured to transition the first integrated circuit die between power states.
13. The method of claim 11, wherein the method is performed by a power manager circuit included in the first integrated circuit die, wherein the power manager circuit is configured to transition the first integrated circuit die between power states.
14. The method of claim 13, further comprising:
synchronizing, by the power manager circuit, a power state change of the plurality of integrated circuit dies from a first power state to a second power state, wherein the synchronizing includes the power manager circuit issuing, to a power manager circuit in included the second integrated circuit die, a request to transition the second integrated circuit die from the first power state to the second power state.
14. The method of claim 13, further comprising: synchronizing, by the power manager circuit, a power state change of the plurality of integrated circuit dies from a first power state to a second power state, wherein the synchronizing includes the power manager circuit issuing, to a power manager circuit in included the second integrated circuit die, a request to transition the second integrated circuit die from the first power state to the second power state.
15. The method of claim 11, wherein the first and second integrated circuit dies are configured as a single system in which the existence of the first and second integrated circuit dies is hidden to software routines.
15. The method of claim 11, wherein the first and second integrated circuit dies are configured as a single system in which the existence of the first and second integrated circuit dies is hidden to software routines.
16. The method of claim 11, wherein the latency event involves a change to a frequency of the memory.
16. The method of claim 11, wherein the latency event involves a change to a frequency of the memory.
17. The method of claim 11, wherein the set of agent circuits includes a peripheral circuit.
17. The method of claim 11, wherein the set of agent circuits includes a peripheral circuit.
18. A system, comprising:
a memory; and
an integrated circuit assembly that is coupled to the memory and includes a first integrated circuit die and a second integrated circuit die that is associated with a set of peripheral circuits, and wherein the first integrated circuit includes a first power manager circuit;
wherein the first power manager circuit is configured to:
detect a latency event to be performed with respect to the memory;
determine read and write tolerance values for the latency event;
send the read and write tolerance values to the second integrated circuit die; and
block the latency event until at least an acknowledgment is received from the second integrated circuit die that the set of peripheral circuits is able to tolerate latencies corresponding to the read and write tolerance values.
1. A system, comprising: a plurality of integrated circuit dies coupled together, wherein the plurality of integrated circuit dies include a first and a second integrated circuit die that include respective processor circuitry, wherein the second integrated circuit die is associated with a set of agent circuits; wherein the first integrated circuit die is configured to: detect a latency event to be performed that affects an availability of a memory associated with the plurality of integrated circuit dies; determine read and write tolerance values for the latency event; send the read and write tolerance values to the second integrated circuit die; and block the latency event until at least an acknowledgment is received from the second integrated circuit die that the set of agent circuits is able to tolerate latencies corresponding to the read and write tolerance values.
19. The system of claim 18, wherein the second integrated circuit die includes a second power manager circuit that is configured to:
send the read and write tolerance values to the set of peripheral circuits;
determine that the set of peripheral circuits is able to tolerate the latencies based on tolerance information received from the set of peripheral circuits; and
provide the acknowledgment to the first power manager circuit.
19. The non-transitory computer readable medium of claim 18, wherein the second integrated circuit die includes a second power manager circuit that is configured to: send the read and write tolerance values to the set of peripheral circuits; determine that the set of peripheral circuits is able to tolerate the latencies based on tolerance information received from the set of peripheral circuits; and provide the acknowledgment to the first power manager circuit.
20. The system of claim 18, wherein the first integrated circuit die includes one or more circuits that are absent in the second integrated circuit die.
10. The system of claim 1, wherein the first and second integrated circuit dies are a first and a second system-on-a-chip respectively that include at least a central processing unit and a graphics processing unit. (i.e., they be different types of circuits)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jones et al. (U.S. Patent Application Publication Number 2014/0098617) and Cooper et al. (U.S. Patent Application Publication Number 2015/0006923).
Regarding Claims 1 and 11, Jones discloses an apparatus (para 0029, 0049 – 0050, 0053; i.e., an integrated circuit assembly) comprising:
a plurality of integrated circuit dies (Figures 1a, 1b, and 2, para 0004, 0055, 0057-0058) that includes a first integrated circuit die (Figure 1a, item 2, paragraph 0058; i.e., a set-top box application die) and a second integrated circuit die (Figure 1a, item 4, para 0004, 0055; i.e., a media processing engine die) that is associated with a set of agent circuits (para 0073, 0200 - 0201; i.e., a set of peripheral circuits);
wherein the first integrated circuit die is configured to:
detect a latency (i.e., latency or delay) event to be performed with respect to a memory (Figure 1a, item 24, paragraphs 0072 and 0094) associated with the plurality of integrated circuit dies (para 0105, 0110);
block (i.e., queuing, arbitration or blocking) the latency event until at least an acknowledgment (i.e., a confirmation) is received (para 0023, 0069, 0208 – 0209) from the second integrated circuit die about the set of agent circuits (i.e., set of peripheral circuits) (para 0104 – 0105, 0107, 0110 – 0111, 0131 – 0132, 0192, 0208 – 0209, claim 7; i.e., by controlling sample rate control over delay).
Jones does not teach explicitly to determine read and write tolerance values for the latency event;
send the read and write tolerance values to the second integrated circuit die; and
the set of agent circuits are able to tolerate latencies corresponding to the read and write tolerance values.
In the same field of endeavor (e.g., latency determination techniques), Cooper teaches to determine read and write tolerance values (i.e., platform latency tolerance) for the latency event (i.e., first event break) (para 0020 – 0021, 0084; i.e., latency time information for each components including memory 150 includes read and write tolerance);
send the read and write tolerance values to the second integrated circuit die (Figure 1, item 120, paragraph 0020); and
the set of agent circuits are able to tolerate latencies corresponding to the read and write tolerance values (paragraphs 0020-0021, 0085–0086, 0094, 0097; i.e., latency tolerance requirements are provided that do not affect functionality and performance).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Cooper’s teachings of latency determination techniques with the teachings of Jones, for the purpose of obtaining a system include functionality to impose a forced delay on block break events to increase the time spent in a reduced power state and thereby reduce overall power consumption.
Regarding Claim 2, Cooper teaches wherein the second integrated circuit die is configured to send (i.e., via a latency tolerance messaging [LTM]) the read and write tolerance values (i.e., platform latency tolerance) to the set of agent circuits (para 0020, 0084 - 0085);
based on tolerance information received from the set of agent circuits, make a determination that the set of agent circuits is able to tolerate the latencies (i.e., latency tolerance requirements) (para 0084 – 0085, 0095, 0097); and
provide the acknowledgment to the first integrated circuit die based on the determination (para 0099).
Regarding Claim 3, Jones discloses wherein a particular agent circuit of the set of agent circuits includes a buffer and is configured to receive a read tolerance value of the read and write tolerance values (para 0020 – 0021, 0084; i.e., latency time information for each components including memory 150 includes read and write tolerance); and
store an amount of data in the buffer based on the read tolerance value (para 0162 teaches to prevent overflow, therefore buffering includes overflow too, para 0165).
Regarding Claim 4, Jones discloses wherein a particular agent circuit of the set of agent circuits includes a buffer (para 0161; i.e., a circular buffer) and is configured to receive a write tolerance value of the read and write tolerance values (para 0020 – 0021, 0084; i.e., latency time information for each components including memory 150 includes read and write tolerance); and
evict an amount of data from the buffer that is based on the write tolerance value (para 0161 – 0163, 0192; i.e., prevent time stamp overflow).
Regarding Claim 5, Jones and Cooper teach wherein a particular agent circuit of the set of agent circuits is configured to send, to the second integrated circuit die (Jones, Die 2, as shown in fig. 15), a minimum read tolerance value that indicates a latency for reads that can be tolerated by the particular agent circuit (i.e., latency tolerance requirements to read without affecting functionality and performance) and a minimum write tolerance value that indicates a latency for writes that can be tolerated by the particular agent circuit (para 0085 – 0086, 0094, 0097; i.e., latency tolerance requirements to write without affecting functionality and performance).
Regarding Claim 6, Cooper teaches wherein the second integrated circuit die is configured to receive minimum read and write tolerance values from ones of the set of agent circuits (i.e., latency tolerance requirements to read without affecting functionality and performance);
determine minimum die read and write tolerance values (i.e., platform latency tolerance) for the second integrated circuit die based on the minimum read and write tolerance values (i.e., platform latency tolerance) received from the agent circuits (para 0020 – 0021, 0084; i.e., latency time information for each components including memory 150 includes read and write tolerance); and
send the minimum die read and write tolerance values to the first integrated circuit die (para 0020; i.e., via a Latency tolerance messaging (LTM) system).
Regarding Claim 7, Cooper teaches wherein the first integrated circuit die is configured to determine minimum system read and write tolerance values based on the minimum die read and write tolerance values of the second integrated circuit die; and
send the read and write tolerance values to the second integrated circuit die in response to a determination that the minimum system read and write tolerance values does not satisfy the read and write tolerance values determined for the latency event (paragraphs 0020-0021).
Regarding Claim 8, Cooper teaches wherein the first integrated circuit die is configured to receive minimum die read and write tolerance values from a third integrated circuit die of the plurality of integrated circuit dies, wherein the minimum system read and write tolerance values are determined based on the minimum die read and write tolerance values of the third integrated circuit die (Figure 1, item 160, paragraphs 0020-0021).
Regarding Claim 9, Cooper teaches wherein the first integrated circuit die includes a first power manager circuit (i.e., 1160 power management logic) that is configured to synchronize a power state change of the plurality of integrated circuit dies from a first power state to a second power state (abstract, para 0011), and wherein the first power manager circuit is further configured to determine the read and write tolerance values (para 0020 – 0022, 0029, 0083; i.e., platform latency tolerance);
send the read and write tolerance value to a second power manager circuit included in the second integrated circuit die (para 0020; i.e., via a Latency tolerance messaging (LTM) system); and
block the latency event (i.e., block break event by forced delay) until at least the acknowledgment is received (abstract, para 0012, 0022 - 0023, 0044; i.e., timer expired).
Regarding Claim 10, Jones discloses wherein the first and second integrated circuit dies are copies of each other (paragraph 0052).
Regarding Claim 12, Cooper teaches receiving, by the first integrated circuit die, minimum die read and write tolerance values associated with the second integrated circuit die; and
determining, by the first integrated circuit die, minimum system read and write tolerance values based on the minimum die read and write tolerance values, wherein the sending is performed in response to a determination that the minimum system read and write tolerance values does not satisfy the read and write tolerance values determined for the latency event (paragraphs 0020-0021).
Regarding Claim 13, Jones discloses wherein the method is performed by a power manager circuit included in the first integrated circuit die, and wherein the power manager circuit is configured to transition the first integrated circuit die between power states (para 0023, 0069, 0071, 0195; i.e., lower power mode).
Regarding Claim 14, Jones discloses synchronizing, by the power manager circuit, a power state change of the plurality of integrated circuit dies from a first power state to a second power state, wherein the synchronizing includes the power manager circuit issuing, to a power manager circuit in included the second integrated circuit die, a request (i.e., power state change request) to transition the second integrated circuit die from the first power state to the second power state (para 0023, 0069, 0071, 0195; i.e., lower power mode).
Regarding Claim 15, Jones discloses wherein the first and second integrated circuit dies (i.e., Die 1 and Die 2) are configured as a single system in which the existence of the first and second integrated circuit dies is hidden to software routines (para 0004, 0010, 0130, 0140).
Regarding Claim 16, Jones discloses wherein the latency event involves a change to a frequency of the memory (para 0195, 0179; i.e., clock rate).
Regarding Claim 17, Jones discloses wherein the set of agent circuits includes a peripheral circuit (para 0055, 0200 – 0200, fig. 15).
Regarding Claim 18, Jones discloses a system comprising:
a memory (Figure 1a, item 24); and
an integrated circuit assembly (Figure 1a, item 12) that is coupled to the memory and includes a first integrated circuit die (Figure 1a, item 2, paragraph 0058; i.e., a set-top box application die) and a second integrated circuit die (Figure 1a, item 4, para 0004, 0055; i.e., a media processing engine die) that is associated with a set of peripheral circuits (para 0073, 0200 - 0201; i.e., a set of peripheral circuits);
wherein the first power manager circuit is configured to:
detect a latency event (i.e., latency or delay) to be performed with respect to the memory (Figure 1a, item 24, paragraphs 0072 and 0094);
block (i.e., queuing, arbitration or blocking) the latency event until at least an acknowledgment (i.e., a confirmation) is received (para 0023, 0069, 0208 – 0209) from the second integrated circuit die about the set of peripheral circuits (para 0104 – 0105, 0107, 0110 – 0111, 0131 – 0132, 0192, 0208 – 0209, claim 7; i.e., by controlling sample rate control over delay).
Jones does not expressly disclose wherein the first integrated circuit includes a first power manager circuit;
to determine read and write tolerance values for the latency event;
send the read and write tolerance values to the second integrated circuit die; and
the set of agent circuits are able to tolerate latencies corresponding to the read and write tolerance values.
In the same field of endeavor (e.g., latency determination techniques), Cooper teaches wherein the first integrated circuit includes a first power manager circuit (Figure 6, item 1160, paragraph 0068);
to determine read and write tolerance values (i.e., platform latency tolerance) for the latency event (i.e., first event break) (para 0020 – 0021, 0084; i.e., latency time information for each components including memory 150 includes read and write tolerance);
send the read and write tolerance values to the second integrated circuit die (Figure 1, item 120, paragraph 0020); and
the set of agent circuits are able to tolerate latencies corresponding to the read and write tolerance values (paragraphs 0020-0021, 0085–0086, 0094, 0097; i.e., latency tolerance requirements are provided that do not affect functionality and performance).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 18.
Regarding Claim 19, Cooper teaches wherein the second integrated circuit die includes a second power manager circuit that is configured to send the read and write tolerance values to the set of peripheral circuits (para 0020; i.e., via a Latency tolerance messaging (LTM) system);
determine that the set of peripheral circuits is able to tolerate the latencies based on tolerance information received from the set of peripheral circuits (para 0020 – 0022, 0029, 0083; i.e., platform latency tolerance); and
provide the acknowledgment to the first power manager circuit (abstract, para 0012, 0022 - 0023, 0044; i.e., timer expired).
Regarding Claim 20, Jones discloses wherein the first integrated circuit die includes one or more circuits that are absent in the second integrated circuit die (paragraph 0058; i.e., the two dies 2 and 4 have different functionalities and therefore indicate that one may have different circuits than the other).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a system for determining read and write latency tolerance values and blocking an event until it is determined that a target device can accept those values.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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