DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2022/0189410 A1, hereinafter referred as “Kim”) in view of Jung et al. (US 2020/0203382 A1, hereinafter referred as “Jung”).
Regarding claim 1, Kim discloses a display apparatus (abstract and title discloses organic light emitting display device) comprising:
a substrate (101) comprising a display area (AA1, AA2) ([0004 discloses a pixel driving circuit and an organic light emitting element are formed over a substrate) and a peripheral area (IA) outside the display area (AA1, AA2) (Fig. 3 and [0049 discloses the substrate 101… may be present in the non-display area IA);
a scan driving circuit including a logic circuit unit and a buffer circuit unit (Fig. 7 and [0070 discloses the second scan driver SP respectively may include a logic circuit for generating a control signal, and a buffer circuit for transmitting the generated control signal); and
a pixel circuit arranged in the display area (AA1, AA2) ([0070 discloses the sub-pixels provided in the display areas AA1 and AA2),
wherein the logic circuit unit includes a first circuit arranged in the peripheral area (IA) and a second logic circuit arranged in the peripheral area (IA) (Figs. 6-7 illustrate logic circuits of the second scan driver SP located in the non-display area IA);
wherein the buffer circuit unit includes a first buffer circuit and a second buffer circuit (Figs. 6-7 and [0075 discloses buffer circuit SP[n] over the sub-pixel in the second display area AA2 and additional buffer circuits corresponding to rows under the sub-pixel in the second display area AA2), the first buffer circuit… in the display area (AA1, AA2) and being electrically connected to the first logic circuit (Fig. 7 and [0070 discloses the second scan driver SP respectively may include a logic circuit and its associated buffer circuit) and configured to output a first scan signal ([0056 discloses the scan driver SP[n] can supply a scan signal SCAN to corresponding gate lines in a line-sequential manner), and the second buffer circuit… in the display area (AA1, AA2) and being electrically connected to the second logic circuit (Fig. 7 and [0070 discloses the second scan driver SP respectively may include a subsequent logic circuit and its associated subsequent buffer circuit) and configured to output a second scan signal ([0056 discloses the scan driver SP[n] can supply a scan signal SCAN to corresponding gate lines in a line-sequential manner).
Kim doesn’t disclose a first buffer circuit arranged on the pixel circuit and second buffer circuit arranged on the pixel circuit, and the display apparatus further comprising: a light-emitting diode arranged on the first buffer circuit in the display area and electrically connected to the pixel circuit.
However, in the same field of endeavor, Jung discloses the pixel circuit arranged on a first buffer circuit (Figs. 6-7, 9 and [0181 discloses the elements SWT and DRT of the pixel circuit arranged on elements of the buffer circuit Tup) and the pixel circuit arranged on a second buffer circuit (Figs. 6-7, 9 and [0181 discloses the elements SWT and DRT of the pixel circuit arranged on elements of the buffer circuit Tup), and the display apparatus (Title discloses display panel and display device) further comprising: a light-emitting diode arranged on the first buffer circuit in the display area (Figs. 6, 9 and [0211 discloses OLED arranged on the Tup element of the buffer circuit in the display area A/A) and electrically connected to the pixel circuit (Fig. 7 and [0147-[0149 discloses driving transistor DRT supplies a driving current to the organic light-emitting diode OLED to drive the organic light-emitting diode OLED).
While Jung discloses the pixel circuits arranged on the first and second buffer circuits as described above, Jung doesn’t explicitly disclose first and second buffer circuits arranged on the pixel circuits.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to disclose first and second buffer circuits arranged on the pixel circuits, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Please note that in the instant application, Fig. 3 and [0092 of the specification, applicant has not disclosed any criticality for the claimed limitations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim for the purpose of enabling top emission of the emissive layer on top and circuitry connected to the emissive layer hidden behind the OLED layer.
Regarding claim 3, Kim discloses the display apparatus of claim 1, wherein the pixel circuit comprises a plurality of transistors (Fig. 2 and [0035 discloses the pixel circuit may include … a plurality of thin film transistors (DT, M1, M2, and/or M3)), the first buffer circuit is electrically connected to a gate electrode of one of the plurality of transistors through a first scan line (Fig. 5c and [0069-[0070 discloses a second scan driver SP that transmits a control signal to the low-temperature polycrystalline silicon thin film transistor (LTPS TFT) within the pixel circuit), and the second buffer circuit is electrically connected to a gate electrode of another one of the plurality of transistors through a second scan line (Fig. 7 and [0070 discloses the second scan driver SP respectively may include a subsequent logic circuit and its associated subsequent buffer circuit; and Fig. 5c and [0069-[0070 discloses a second scan driver SP that transmits a control signal to the low-temperature polycrystalline silicon thin film transistor (LTPS TFT) within the pixel circuit).
4. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jung and in further view of Fan et al. (US 2024/0395213 A1, hereinafter referred as “Fan”).
Regarding claim 5, Kim discloses the display apparatus of claim 1, wherein the pixel circuit comprises:
a first transistor (DT) comprising a first gate electrode (Fig. 2 and [0038 discloses driving TFT D comprising a gate electrode);
a second transistor (M1) arranged between a data line (Vdata/Vref) and the first gate electrode (Fig. 2 illustrates TFT M1 arranged between the data line Vdata and gate electrode of driving transistor DT);
a fourth transistor (M3) arranged between an initialization voltage line (Vini) and the light-emitting diode (EL) (Fig. 2 and [0035 discloses TFT M3 arranged between the initialization line Vini and an organic light emitting element EL, such as an organic light emitting diode);
a fifth transistor (M2) arranged between a driving voltage line (VDD) and the first transistor (DT) (Fig. 2 illustrates TFT M2 arranged between the pixel driving voltage VDD and driving transistor DT).
Kim as modified doesn’t disclose a third transistor arranged between a reference voltage line and the first gate electrode; and a sixth transistor arranged between the light-emitting diode and the first transistor.
However, in the same field of endeavor, Fan discloses a third transistor (T1) arranged between a reference voltage line (Vinit1) and the first gate electrode (gate of T3) (Fig. 17 illustrates first transistor T1 arranged between first rest power line Vinit1 and the gate of third transistor T3); and a sixth transistor (T6) arranged between the light-emitting diode (D) and the first transistor (T3) (Fig. 17 illustrates sixth transistor T6 arranged between the light emitting element D and the third transistor T3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Kim so that the gate of the driving transistor T3 is reset by an initialization voltage written by the first reset power line Vinit1, so as to prepare for the writing of the data voltage Vdata for a next frame ([0210).
5. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jung and in further view of Kwon et al. (US 2024/0185786 A1, hereinafter referred as “Kwon”).
Regarding claim 10, Kim as modified doesn’t disclose the display apparatus of claim 1, wherein: each of the first logic circuit, the second logic circuit, the pixel circuit, the first buffer circuit, and the second buffer circuit comprises an oxide-based semiconductor layer.
However, in the same field of endeavor, Kwon discloses wherein: each of the first logic circuit, the second logic circuit, the pixel circuit, the first buffer circuit, and the second buffer circuit comprises an oxide-based semiconductor layer ([0042 discloses a pixel circuit and a gate driving circuit may include a plurality of transistors. Transistors may be implemented as oxide thin film transistors (oxide TFTs) including an oxide semiconductor).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Kim for the purpose of having more uniform mobility and threshold voltage over large areas than LTPS.
6. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jung and in further view of Kwon et al. (US 2024/0185786 A1, hereinafter referred as “Kwon”).
Regarding claim 20, Kim discloses an electronic device ([0003 discloses an image display device) comprising:
a display apparatus (abstract and title discloses organic light emitting display device); and
a power supply circuit configured to supply power to the display apparatus ([0037 discloses the pixel circuit may further include a first power line PL1 for supplying a pixel driving voltage VDD to the sub-pixel, a second power line PL2 for supplying an initialization voltage VINI to the sub-pixel, and a low power supply terminal VSS for supplying a low power supply voltage VSS to the sub-pixel. These power lines are connected to a power circuit),
a display apparatus (abstract and title discloses organic light emitting display device) comprising:
a substrate (101) comprising a display area (AA1, AA2) ([0004 discloses a pixel driving circuit and an organic light emitting element are formed over a substrate) and a peripheral area (IA) outside the display area (AA1, AA2) (Fig. 3 and [0049 discloses the substrate 101… may be present in the non-display area IA);
a scan driving circuit including a logic circuit unit and a buffer circuit unit (Fig. 7 and [0070 discloses the second scan driver SP respectively may include a logic circuit for generating a control signal, and a buffer circuit for transmitting the generated control signal); and
a pixel circuit arranged in the display area (AA1, AA2) ([0070 discloses the sub-pixels provided in the display areas AA1 and AA2),
wherein the logic circuit unit includes a first circuit arranged in the peripheral area (IA) and a second logic circuit arranged in the peripheral area (IA) (Figs. 6-7 illustrate logic circuits of the second scan driver SP located in the non-display area IA);
wherein the buffer circuit unit includes a first buffer circuit and a second buffer circuit (Figs. 6-7 and [0075 discloses buffer circuit SP[n] over the sub-pixel in the second display area AA2 and additional buffer circuits corresponding to rows under the sub-pixel in the second display area AA2), the first buffer circuit… in the display area (AA1, AA2) and being electrically connected to the first logic circuit (Fig. 7 and [0070 discloses the second scan driver SP respectively may include a logic circuit and its associated buffer circuit) and configured to output a first scan signal ([0056 discloses the scan driver SP[n] can supply a scan signal SCAN to corresponding gate lines in a line-sequential manner), and the second buffer circuit… in the display area (AA1, AA2) and being electrically connected to the second logic circuit (Fig. 7 and [0070 discloses the second scan driver SP respectively may include a subsequent logic circuit and its associated subsequent buffer circuit) and configured to output a second scan signal ([0056 discloses the scan driver SP[n] can supply a scan signal SCAN to corresponding gate lines in a line-sequential manner).
Kim doesn’t disclose a first buffer circuit arranged on the pixel circuit and second buffer circuit arranged on the pixel circuit, and the display apparatus further comprising: a light-emitting diode arranged on the first buffer circuit in the display area and electrically connected to the pixel circuit.
However, in the same field of endeavor, Jung discloses the pixel circuit arranged on a first buffer circuit (Figs. 6-7, 9 and [0181 discloses the elements SWT and DRT of the pixel circuit arranged on elements of the buffer circuit Tup) and the pixel circuit arranged on a second buffer circuit (Figs. 6-7, 9 and [0181 discloses the elements SWT and DRT of the pixel circuit arranged on elements of the buffer circuit Tup), and the display apparatus (Title discloses display panel and display device) further comprising: a light-emitting diode arranged on the first buffer circuit in the display area (Figs. 6, 9 and [0211 discloses OLED arranged on the Tup element of the buffer circuit in the display area A/A) and electrically connected to the pixel circuit (Fig. 7 and [0147-[0149 discloses driving transistor DRT supplies a driving current to the organic light-emitting diode OLED to drive the organic light-emitting diode OLED).
While Jung discloses the pixel circuits arranged on the first and second buffer circuits as described above, Jung doesn’t explicitly disclose first and second buffer circuits arranged on the pixel circuits.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to disclose first and second buffer circuits arranged on the pixel circuits, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Please note that in the instant application, Fig. 3 and [0092 of the specification, applicant has not disclosed any criticality for the claimed limitations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim for the purpose of enabling top emission of the emissive layer on top and circuitry connected to the emissive layer hidden behind the OLED layer.
Allowable Subject Matter
7. Claims 2, 4, and 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-19 are allowed due to allowable limitations “a first layer stack arranged on the substrate; a second layer stack arranged on the first layer stack; and a light-emitting diode layer arranged on the second layer stack, wherein the first layer stack comprises a first logic circuit arranged in the peripheral area and a pixel circuit arranged in the display area, the second layer stack comprises a second logic circuit arranged in the peripheral area” of independent claim 11.
The closest prior relevant to this limitation is US 2020/0203382 A1, which in the abstract discloses display panel can include a first plate; a second plate disposed on the first plate; a first layer stack disposed between the first plate and the second plate; a first transistor disposed within the first layer stack; a second layer stack disposed on the second plate; and a second transistor disposed within the second layer stack, in which the first transistor is disposed in a location overlapping with an active area corresponding to an image display area. Figs. 3-4, 9-12 and [0110 discloses the plurality of first transistors TR1 disposed in the first layer stack LST1 can be transistors constituting the plurality of gate driving circuits GIP. Figs. 3-4, 9-12 and [0121 discloses in addition to the plurality of second transistors TR2 constituting the plurality of subpixels SP, a plurality of capacitors and a plurality of light emitting elements corresponding to components of the plurality of subpixels SP, and various signal lines for driving the plurality of subpixels SP can be formed in the second layer stack LST2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYANK J SHAH whose telephone number is (571)270-3732. The examiner can normally be reached on 10:00 - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ghebretinsae, Temesghen can be reached on (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRIYANK J SHAH/Primary Examiner, Art Unit 2626