DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final communication in response to communication filed 5/21/25.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 7,8, 10, 16, 17, 18, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticpated by Kawasaki et al. 20010043099.
With respect to claim 1, figures 17-22 of Kawasaki et al. disclose a system comprising:
a logic device [fig. 17 240; figure 21] configured to perform a logic operation [241, 243, 244, 252] to a signal [SS2] generated by a oscillator [fig. 17 230 plus 242 fig. 21 ; fig. 20] circuit, wherein the logic operation generates a pulse width modulation (PWM) signal [SS3] corresponding to the signal.
With respect to claim 3, figures 17-22 of Kawasaki et al. disclose the system of claim 1, wherein the logic device is configured to perform the logic operation to two signals [SS2 and output 242] generated by the oscillator circuit, and the logic device comprises:
a first logic circuit [243] and a second logic circuit [241] configured to receive the two signals; and a third logic circuit [252] configured to output the PWM signal.
With respect to claim 7, figures 17-22 of Kawasaki et al. disclose the system of claim 1, wherein the logic operation comprises at least one of a NOT gate, a NAND gate, or a NOR gate.
With respect to claim 8, figures 17-22 of Kawasaki et al. disclose the system of claim 1, further comprising a signal generator configured to delay an input signal [SR] to generate the signals, and the signal generator comprises the oscillator circuit.
With respect to claim 10, figures 17-22 of Kawasaki et al. disclose a device comprising:
a plurality of logic circuits [241,243,244,252] configured to generate an output signal [output 252] based on signals [SS2 and output 242] generated by a oscillator circuit [230 plus 242; fig. 17,20,21] and to the plurality of logic circuits, wherein the plurality of logic circuits comprise:
first [243] and second [241] logic circuits configured to receive the signals.
With respect to claim 16, figures 17-22 of Kawasaki et al. disclose the device of claim 10, wherein the signal generator comprises the oscillator circuit. [230 fig. 20]
With respect to claim 17, figures 17-22 of Kawasaki et al. disclose a method, comprising:
generating an output signal [SS3 or output 252] by performing a logic operation [241,243,244,252] to a signal [SS2 and/or output 242] generated by a oscillator circuit [230 and 242], wherein the output signal is generated by:
receiving, by a first logic circuit [243], the signal; and
generating, by a third logic circuit [241 or 252], the output signal.
With respect to claim 18, figures 17-22 of Kawasaki et al. disclose the method of claim 17, wherein the output signal is a pulse width modulation (PWM) signal [output 251] with variable duty cycle modulation, the PWM signal is generated by:
receiving, by the first logic circuit [243] and a second logic circuit [241], two signals generated by the oscillator circuit;
generating, by the first logic circuit and the second logic circuit, clocking voltages configured
to drive a fourth logic circuit [244];
performing, by the fourth logic circuit, a first logic operation to generate a first voltage
output [output 244]; and
generating, by the third logic circuit [252], the PWM signal by performing a second logic operation on the first voltage output.
With respect to claim 20, figures 17-22 of Kawasaki et al. disclose the method of claim 18, wherein the PWM signal is further generated by performing, by a fifth logic circuit [252] coupled between the third logic circuit and the fourth logic circuit, a third logic operation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4,5,6, 9, 11-15, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki et al. in view of Udrea et al. [11081578].
With respect to claim 2, figures 17-22 of Kawasaki et al. disclose the system of claim 1, but does not disclose wherein the logic device comprises a plurality of enhancement mode high electron mobility transistors (E-HEMTs) and a plurality of depletion mode high electron mobility transistors (D-HEMTs).
However, Udrea et al. teach that the technology has matured allowing for high speed (col 1, ln 24). Fig. 11 show that logic circuits may be implemented as E-HEMTs and D-HEMTs as recited in claim 2.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement the logic circuits of Kawasaki et al. as E-HEMTs and D-HEMTs as taught by Udrea et al. for the benefit of high-speed operation. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions and the combination would have yielded predictable results to one of ordinary skill in the art before the effective filing date of the invention claim 2 is obvious.
Udrea et al. Fig. 11 depicts a NAND gate. However, when taken in context of the disclosure as a whole, Fig. 11 is seen to represent a general example of logic structure where the pull-up components are D-HEMTs and the pull-down components are E-HEMTs (col 15, Ins 3-5). That is, one of ordinary skill would intuitively recognize that the pull-up D-HEMTs and pull-down E-HEMTs could readily be reconfigured into equally well-know logic gates such as inverters and NOR gates. That is, as per Examiner's combination, each pull-up transistor depicted by Kawasaki would be replaced by a pull-up D-HEMT as taught by Udrea et al. Each pull-down transistor depicted by Kawasaki would be replaced by a pull-down E-HEMT as taught by Udrea et al.
With respect to claim 4, the above combination discloses the system of claim 3, wherein:
the first logic circuit [241] is configured to receive a first signal [SS2] of the two signals, the first logic
circuit comprising a first E-HEMT coupled in series to a first D-HEMT;
the second logic circuit [243] is configured to receive a second signal [output 242] of the two signals, the second logic circuit comprising a second E-HEMT coupled in series to a second D-HEMT;
the logic device further comprises a fourth logic circuit [243] coupled to the first logic circuit and the second logic circuit, the fourth logic circuit comprising a third E-HEMT and a fourth E-HEMT coupled together in series with a third D-HEMT; and
the third logic circuit is coupled to the fourth logic circuit, the third logic circuit comprising a
fifth E-HEMT and a fourth D-HEMT.
With respect to claim 5, the above combination discloses the system of claim 4, wherein the logic device further comprises a fifth logic circuit [251] coupled between the third logic circuit and the fourth logic circuit, the fifth logic circuit comprising a sixth E- HEMT and a fifth D-HEMT.
With respect to claim 6, the above combination discloses the system of claim 2, wherein the plurality of E-HEMTs and the plurality of D-HEMTs are n- type transistors. [Fig. 11]
With respect to claim 9, the above combination discloses the system of claim 1, wherein the logic device comprises Gallium Nitride (GaN) components. [Udrea et al. fig. 3]
With respect to claim 11, the above combination discloses the device of claim 10, wherein the plurality of logic circuit comprises a plurality of high electron mobility transistors (HEMTs), the output signal is a pulse width modulation (PWM) signal, and the plurality of logic circuits further comprises a third logic circuit [251] configured to output the PWM signal.
With respect to claim 12, the above combination discloses the device of claim 11, wherein the signals to the plurality of logic circuits comprise at least two signals generated by a signal generator [230] and the PWM signal has a duty cycle signal that is based on duty cycles of the at least two signals. [duty depends on the combination of signals]
With respect to claim 13, the above combination discloses the device of claim 11, wherein:
the first logic circuit [241] is configured to receive a first signal [SS2] of the signals, the first logic circuit comprising a first E-HEMT (enhancement-HEMT) of the plurality of E-HEMTs coupled in series to a first D-HEMT (depletion-HEMT) of the plurality of D-HEMTs;
the second logic circuit [243] is configured to receive a second signal [output 242] of the signals the second logic circuit comprising a second E-HEMT of the plurality of E-HEMTs coupled in series to a second D-HEMT of the plurality of D-HEMTs;
the plurality of logic circuits further comprise a fourth logic circuit [244 or 252 or 251] coupled to the first logic circuit and the second logic circuit, the fourth logic circuit comprising a third E-HEMT and a fourth E-HEMT of the plurality of E-HEMTs coupled together in series with a third D-HEMT of the plurality of D-HEMTs; and
the third logic circuit is coupled to the fourth logic circuit, the third logic circuit comprising a
fifth E-HEMT of the plurality of E-HEMTs and a fourth D-HEMT of the plurality of D-HEMTs.
With respect to claim 14, the above combination discloses the device of claim 13, wherein the plurality of logic circuits further comprises a fifth logic circuit [244 or 251 or 252] coupled between the third logic circuit and the fourth logic circuit, the fifth logic circuit
comprising a sixth E-HEMT of the plurality of E-HEMTs and a fifth D-HEMT of the plurality of D- HEMTs.
With respect to claim 15, the above combination discloses the device of claim 11, wherein the plurality of E-HEMTs and the plurality of D-HEMTs are n- type transistors. [Udrea et al. fig. 3]
With respect to claim 19, the above combination discloses the method of claim 18, wherein:
the first logic circuit [241] comprises a first E-HEMT coupled in series to a first D-HEMT;
the second logic circuit[243] comprises a second E-HEMT coupled in series to a second D-HEMT;
the fourth logic circuit [244] is coupled to the first logic circuit and the second logic circuit and
comprises a third E-HEMT and a fourth E-HEMT coupled together in series with a third D-HEMT; and
the third logic circuit is coupled to the fourth logic circuit and comprises a fifth E-HEMT and
a fourth D-HEMT.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12334925 in view of U.S. Pantent No.. 11764760.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Taelor Kim can be reached on 571-270-7166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN JAGER/
Primary Examiner, Art Unit 2842
9/30/26
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