DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin et al. (US 9,489,894) (herein Yin).
Regarding claim 1, Yin teaches a pixel (a pixel circuit, abstract and figure 3);
a first transistor (DTFT) including a first electrode, a second electrode, and a gate electrode electrically connected to a first voltage line (ELVDD) which receives a first voltage; a light emitting diode (OLED) including a first electrode electrically connected to the second electrode of the first transistor (DTFT) and a second electrode connected to a second voltage line (ELVSS) which receives a second voltage; a second transistor (a transistor T3) including a first electrode connected to a data line (VData) , a second electrode electrically connected to the first electrode of the first transistor (DTFT), and a gate electrode which receives a first scan signal (Vgata(n));
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a fifth transistor (transistor T2) including a first electrode electrically connected to the first electrode of the first transistor (DTFT), a second electrode electrically connected to a first node (a node), and a gate electrode which receives a third scan signal (Vgate (n-1)));
a first capacitor (Cs) connected between the second electrode of the fifth transistor (T2) and the gate electrode of the first transistor (DTFT);
wherein the first electrode of the first transistor (DTFT), the second electrode of the second transistor (T3) and the first electrode of the fifth transistor (T2) are electrically connected to each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-13 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2016/0351124 herein Kim ‘124) in view of Heganovic et al. (US 11,315,489) ( herein Heganovic).
Regarding claim 11, Kim ‘124 teaches a display device (see abstract, figures 2-3, and ¶51-¶53);
a pixel (PXL) connected to a plurality of scan lines (scan lines (n) and (n-1) and a data line (a data line m, see figure 3);
a scan driving circuit (13) which outputs a plurality of scan signals ( scan (n) of T1, scan (n) of T3 and scan (n-1) of T5, see ¶66-¶70) for driving the pixel to the plurality of scan lines;
a data driving circuit (12) which output a data signal to the data line during a driving frame (see ¶73 and figure 4);
a driving controller (11) which controls the scan driving circuit and the data driving circuit,
wherein the plurality of scan signals comprises first to third scan signals (the scan (n) of T1, scan (n) of T3 and scan (n-1) of T5, see ¶66-¶70) ,
wherein the pixel (PXL, see Figure 3, ¶62) comprising:
a first transistor (a drive transistor DT, ¶63) including a first electrode, a second electrode, and a gate electrode electrically connected to a first voltage line (Vini) which receives a first voltage;
a light emitting diode (OLED) including a first electrode electrically connected to the second electrode of the first transistor (DT) and a second electrode connected to a second voltage line (ELVSS) which receives a second voltage;
a second transistor (a transistor T1) including a first electrode connected to a data line (Data(m)) , a second electrode electrically connected to the first electrode of the first transistor (DT), and a gate electrode which receives a first scan signal (SCAN(n));
a fifth transistor (transistor T5) including a first electrode electrically connected to the first electrode of the first transistor (DT), a second electrode electrically connected to a first node (a node A), and a gate electrode which receives a third scan signal (SCAN(n-1)); and
a first capacitor (Cstg) connected between the second electrode of the fifth transistor (T5) and the gate electrode of the first transistor (DT).
Kim '124 fails to teach a driving frame and output a bias signal to the data line during a bias frame, the pixel emits light in response to the data signal received through the data line during the driving frame, and is initialized in response to the bias signal received through the data line during the bias frame;
wherein, during the bias frame, the second transistor is turned on to transmit the bias signal from the data line to the first electrode of the first transistor.
Heganovic teaches FIG. 2A illustrates a timing diagram associated with the operation of the pixel driving circuit of FIG. 1 during a refresh frame (col. 5, lines 4-7), As illustrated in FIG. 3, the solid curve shows what the threshold voltage VTH of the drive transistor TD behaves with the on bias stress phase inserted between the frames. (col. 9, lines 54-62), At the beginning of the anode reset and on bias stress phase (e.g., at t=t6), the EMI(n) signal level is changed from a low voltage value to a high voltage value, causing the transistors T3 and T5 to be turned off, and the transistor T6 to be turned on. When the transistor T6 is on, the anode of the light-emitting device 104 is reset to VINIT. The pSCAN(n) signal level is changed from a high voltage value to a low voltage value which turns the transistor T4 on. A high enough data voltage is applied to the source of the drive transistor through the transistor T4 to bias stress the drive transistor TD. (Col. 9, lines 10-19).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the driving operation as Heganovic teaches, to modify the display device of Kim '124. The motivation for doing so would deliver the better results in the pixels in a display exhibiting substantially uniform brightness for a given VDATA value and reduce flicker. Heganovic col. 9, lines 59-62.
Regarding claim 12, Heganovic teaches the display device of claim 11, wherein the driving controller determines a driving frequency and controls the data driving circuit and the scan driving circuit to operate as the driving frame and the bias frame based on the driving frequency. (See Heganovic col. 10, lines 1-27).
Regarding claim 13, Heganovic teaches the display device of claim 12, wherein the scan driving circuit activates each of the plurality of scan signals in a predetermined order during the driving frame. (See Heganovic col. 6, line 62 to col. 7, line 33).
Regarding claim 19, Kim '124 teaches an electronic device (see Abstract, figures 2-3, and ¶51-¶53);
a display panel (10) including a pixel (PXL) connected to a plurality of scan lines (scan lines (n) and (n-1) and a data line (a data line m, see figure 3);
a controller (11) which controls the scan driving circuit and the data driving circuit,
a scan driving circuit (13) which outputs a plurality of scan signals ( scan (n) of T1, scan (n) of T3 and scan (n-1) of T5, see ¶66-¶70) for driving the pixel to the plurality of scan lines;
a data driving circuit (12) which output a data signal to the data line during a driving frame (see ¶ 73 and figure 4);
wherein the plurality of scan signals comprises first to third scan signals (the scan (n) of T1, scan (n) of T3 and scan (n-1) of T5, see ¶66-¶70),
wherein the pixel (PXL, see Figure 3, ¶62) comprising:
a first transistor (a drive transistor DT, ¶63) including a first electrode, a second electrode, and a gate electrode electrically connected to a first voltage line (Vini) which receives a first voltage;
a light emitting diode (OLED) including a first electrode electrically connected to the second electrode of the first transistor (DT) and a second electrode connected to a second voltage line (ELVSS) which receives a second voltage;
a second transistor (a transistor T1) including a first electrode connected to a data line (Data(m)) , a second electrode electrically connected to the first electrode of the first transistor (DT), and a gate electrode which receives a first scan signal (SCAN(n));
a fifth transistor (transistor T5) including a first electrode electrically connected to the first electrode of the first transistor (DT), a second electrode electrically connected to a first node (a node A), and a gate electrode which receives a third scan signal (SCAN(n-1)); and
a first capacitor (Cstg) connected between the second electrode of the fifth transistor (T5) and the gate electrode of the first transistor (DT).
Kim '124 fails to teach a driving frame and output a bias signal to the data line during a bias frame, the pixel emits light in response to the data signal received through the data line during the driving frame, and is initialized in response to the bias signal received through the data line during the bias frame;
wherein, during the bias frame, the second transistor is turned on to transmit the bias signal from the data line to the first electrode of the first transistor.
Heganovic teaches FIG. 2A illustrates a timing diagram associated with the operation of the pixel driving circuit of FIG. 1 during a refresh frame (col. 5, lines 4-7), As illustrated in FIG. 3, the solid curve shows what the threshold voltage VTH of the drive transistor TD behaves with the on bias stress phase inserted between the frames. (col. 9, lines 54-62), At the beginning of the anode reset and on bias stress phase (e.g., at t=t6), the EMI(n) signal level is changed from a low voltage value to a high voltage value, causing the transistors T3 and T5 to be turned off, and the transistor T6 to be turned on. When the transistor T6 is on, the anode of the light-emitting device 104 is reset to VINIT. The pSCAN(n) signal level is changed from a high voltage value to a low voltage value which turns the transistor T4 on. A high enough data voltage is applied to the source of the drive transistor through the transistor T4 to bias stress the drive transistor TD. (Col. 9, lines 10-19).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the driving operation as Heganovic teaches, to modify the display device of Kim '124. The motivation for doing so would deliver the better results in the pixels in a display exhibiting substantially uniform brightness for a given VDATA value and reduce flicker. Heganovic col. 9, lines 59-62.
Regarding claim 20, Heganovic teaches the display device of claim 19, wherein the controller determines a driving frequency and controls the data driving circuit and the scan driving circuit to operate as the driving frame and the bias frame based on the driving frequency. (See Heganovic col. 10, lines 1-27).
Claim(s) 14 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘124 and Heganovic as applied to claim 11 above, and further in view of Kim et al. (US 2021/0142733 herein Kim ‘733).
Regarding claim 14, Kim ‘124 and Heganovic fail to teach the scan driving circuit maintains the second and third scan signals at an inactive level during the bias frame and activates the first scan signal.
Regarding claim 18, Kim ‘124 and Heganovic fail to teach the driving controller determines a driving frequency as one selected from a first frequency and a second frequency lower than the first frequency, wherein when the driving controller determines the driving frequency as the first frequency, one frame comprises only the driving frame, wherein when the driving controller determines the driving frequency as the second frequency, one frame comprises the driving frame and the bias frame.
Regarding claim 14, Kim '733 teaches the scan driving circuit maintains the second and third scan signals at an inactive level during the bias frame and activates the first scan signal. (See Kim '733 ¶60).
Regarding claim 18, Kim '733 teaches the driving controller determines a driving frequency as one selected from a first frequency and a second frequency lower than the first frequency, wherein when the driving controller determines the driving frequency as the first frequency, one frame comprises only the driving frame, wherein when the driving controller determines the driving frequency as the second frequency, one frame comprises the driving frame and the bias frame. (See Kim '733 ¶73).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the driving operation, as Kim '733 teaches, to modify the display device of Kim '124 and Heganovic. The motivation for doing so would preventing a gradual increase of luminance at a low driving frequency, while saving power consumption. Kim '733 ¶15-¶16, and ¶75.
Allowable Subject Matter
Claims 2-10 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of prior art of record teaches claim 2 having the pixel of claim 1, further comprising:
a second capacitor electrically connected between the first voltage line and the first node;
a third transistor including a first electrode electrically connected to the second electrode of the first transistor, a second electrode electrically connected to the gate electrode of the first transistor, and a gate electrode which receives a second scan signal;
a fourth transistor including a first electrode electrically connected to the second electrode of the third transistor, a second electrode electrically connected to a third voltage line which receives a third voltage, and a gate electrode which receives a fourth scan signal;
a sixth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first electrode of the light emitting diode, and a gate electrode which receives a first emission control signal;
a seventh transistor including a first electrode connected to the second electrode of the sixth transistor, a second electrode electrically connected to a fourth voltage line which receives a fourth voltage, and a gate electrode which receives a fifth scan signal; and
an eighth transistor including a first electrode connected to the first voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode which receives a second emission control signal.
None of prior art of record teaches claim 15 having the display device of claim 11, comprising:
an emission driving circuit which outputs a first emission control signal and a second emission control signal,
wherein the plurality of scan signals further comprises a fourth scan signal and a fifth scan signal, wherein the pixel further comprises:
a second capacitor electrically connected between the first voltage line and the first node;
a third transistor including a first electrode electrically connected to the second electrode of the first transistor, a second electrode electrically connected to the gate electrode of the first transistor, and a gate electrode which receives the second scan signal;
a fourth transistor including a first electrode electrically connected to the second electrode of the third transistor, a second electrode electrically connected to a third voltage line which receives a third voltage, and a gate electrode which receives the fourth scan signal;
a sixth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first electrode of the light emitting diode, and a gate electrode which receives the first emission control signal;
a seventh transistor including a first electrode connected to the second electrode of the sixth transistor, a second electrode electrically connected to a fourth voltage line which receives a fourth voltage, and a gate electrode which receives the fifth scan signal; and
an eighth transistor including a first electrode connected to the first voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode which receives a second emission control signal.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Nguyen whose telephone is (571)272-7697. The examiner can normally be reached M-T 8am-5pm Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin K Patel can be reached on 571-272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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KEVIN M NGUYEN
Examiner, Art Unit 2628
/Kevin M Nguyen/Primary Examiner, Art Unit 2628 Telephone: (571) 272-7697
Email: kevin.nguyen2@uspto.gov
Prosecution Insights