DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/18/2026 has been entered.
Claims 1, 11, and 19-20 are amended.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 20 is objected to because of the following informalities: “the electronic of claim 19” is missing --device--. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2018/0293939).
Regarding claim 1, Kim teaches a pixel (a pixel circuit PXL, abstract and figure 2); a first transistor (M1) including a first electrode, a second electrode, and a gate electrode electrically connected to a first voltage line (ELVDD) which receives a first voltage;
a light emitting diode (OLED) including a first electrode electrically connected to the second electrode of the first transistor (M1) and a second electrode connected to a second voltage line (ELVSS) which receives a second voltage;
a second transistor (a transistor M2) including a first electrode connected to a data line (data line Dm) , a second electrode electrically connected to the first electrode of the first transistor (M1), and a gate electrode which receives a first scan signal (S1i);
a fifth transistor (transistor M5) including a first electrode electrically connected to the first electrode of the first transistor (M1), a second electrode electrically connected to a first node (a node N1), and a gate electrode which receives a third scan signal (Ei);
a first capacitor (Cst) connected between the second electrode of the fifth transistor (M5) and the gate electrode of the first transistor (M1);
wherein the first electrode of the first transistor (M1), the second electrode of the second transistor (M2) and the first electrode of the fifth transistor (M5) are electrically connected to each other, defined by a same active pattern (See ¶ 100 for the first to fifth transistors M1 to M5 are formed a same P-type poly-silicon semiconductor transistors.)
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US 2019/0130832).
Regarding claim 1, Chang teaches a pixel (a pixel circuit SP, abstract and figure 6); a first transistor (DT) including a first electrode, a second electrode, and a gate electrode electrically connected to a first voltage line (VVL2) which receives a first voltage;
a light emitting diode (EL) including a first electrode electrically connected to the second electrode of the first transistor (DT) and a second electrode connected to a second voltage line (VSSL) which receives a second voltage;
a second transistor (a transistor T1) including a first electrode connected to a data line (data line DLk) , a second electrode electrically connected to the first electrode of the first transistor (DT), and a gate electrode which receives a first scan signal (scanl (j));
a fifth transistor (transistor T3) including a first electrode electrically connected to the first electrode of the first transistor (DT), a second electrode electrically connected to a first node (a node DTS), and a gate electrode which receives a third scan signal (eml(j));
a first capacitor (Cst) connected between the second electrode of the fifth transistor (T3) and the gate electrode of the first transistor (DT);
wherein the first electrode of the first transistor (DT), the second electrode of the second transistor (T1) and the first electrode of the fifth transistor (T3) are electrically connected to each other, defined by a same active pattern (See ¶ 100 for a pixel circuit including a plurality of transistors DT and T1 to T5 are described as p-type transistors.)
Allowable Subject Matter
Claims 11-20 are allowed.
None of prior art of record teaches “wherein, during the bias frame, the second transistor is turned on to transmit the bias signal from the data line to the first electrode of the first transistor, and wherein, during the driving frame, the data signal is transmitted to the first node through the second transistor and the fifth transistor.”
Claims 2-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
None of prior art of record teaches claim 2 having the pixel of claim 1, further comprising:
a second capacitor electrically connected between the first voltage line and the first node;
a third transistor including a first electrode electrically connected to the second electrode of the first transistor, a second electrode electrically connected to the gate electrode of the first transistor, and a gate electrode which receives a second scan signal;
a fourth transistor including a first electrode electrically connected to the second electrode of the third transistor, a second electrode electrically connected to a third voltage line which receives a third voltage, and a gate electrode which receives a fourth scan signal;
a sixth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode connected to the first electrode of the light emitting diode, and a gate electrode which receives a first emission control signal;
a seventh transistor including a first electrode connected to the second electrode of the sixth transistor, a second electrode electrically connected to a fourth voltage line which receives a fourth voltage, and a gate electrode which receives a fifth scan signal; and
an eighth transistor including a first electrode connected to the first voltage line, a second electrode connected to the first electrode of the first transistor, and a gate electrode which receives a second emission control signal.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Nguyen whose telephone is (571)272-7697. The examiner can normally be reached M-T 8am-5pm Eastern Time.
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KEVIN M NGUYEN
Examiner, Art Unit 2628
/Kevin M Nguyen/Primary Examiner, Art Unit 2628 Telephone: (571) 272-7697
Email: kevin.nguyen2@uspto.gov
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