DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 05/22/2025. Claims 1-20 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 4, 6, 8, 10, 11, 13, 15, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sharon et al., US 2021/0349778 A1 (“Sharon”) and further in view of US 2023/0325105 A1 (“the ’105 publication”).
Claim 1: Sharon teaches a system comprising: a memory device; and a processing device, operatively coupled to the memory device (e.g., Sharon teaches memory system 100 including memory controller 102 and integrated memory assembly 104, with control circuitry including the control die, state machine, folding circuit, processor, and/or microcontroller for controlling operations on the nonvolatile memory cells. See ¶¶[0046]-[0047], [0190]-[0191]), to perform operations comprising:
performing a data integrity check on a first set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value (e.g., Sharon teaches that the first set of data is read from a first set of nonvolatile memory cells in which it is stored as single-bit-per-memory-cell data. See ¶[0196]. Sharon further teaches determining a measure of error (MOE) for the set of data. The measure may be: a syndrome weight / number of unsatisfied parity-check equations; or a bit error rate (BER). See ¶[0204]. Sharon also explains that the initial syndrome weight correlates with BER and that the control die can estimate BER and make memory-management decisions based on it. See ¶[0085]);
responsive to determining that the data integrity metric value satisfies a threshold criterion (e.g., Sharon expressly compares the MOE to first and second thresholds TH1 and TH2 and selects a course of action based on that comparison. See ¶¶[0204]-[0206]).
Not explicitly taught by Sharon is determining whether a threshold number of second sets of memory cells, configured to store the first number of bits per memory cell, are available for a memory management operation. Sharon teaches that multiple single-bit source sets are used in the folding operation. For example, FIGS. 24-25 and ¶¶[0191]-[0199] describe first, second, and third single-bit-per-cell source sets that are subsequently folded into a multiple-bit-per-cell target. FIG. 25 expressly shows the first, second, and third source sets being programmed to a target set as multiple-bit-per-cell data. Sharon therefore establishes that a plurality of source sets is needed for the fold.
However, The ’105 publication explains that:
an SLC block stores one bit per memory cell;
TLC stores three bits per cell;
QLC stores four bits per cell;
after three SLC blocks have been written, they can be folded into a TLC block;
after four SLC blocks have been written, they can be folded into a QLC block.
See ¶[0032]. More importantly, ¶[0037] expressly teaches the required availability determination. Referring to FIG. 7, the controller:
determines whether the number of available SLC blocks is below a threshold;
performs an urgent folding operation when required;
determines the number of available blocks for folding; and
“If four blocks are available,” performs a full folding operation.
If four blocks are not available, the controller proceeds to alternative folding branches. See ’105 publication ¶[0037], Fig. 7.
Sharon also fails to teach that responsive to determining that the threshold number of second sets of memory cells are available, causing the memory device to perform the memory management operation by copying data from the first set of memory cells and from the threshold number of second sets of memory cells to a third set of memory cells configured to store a second number of bits per memory cell. Sharon teaches adaptive folding of first, second, and third sets of single-bit-per-cell data into a target set storing multiple bits per cell. See ¶¶[0194]-[0199]. Besides, Sharon’s summary of the embodiment likewise states that a first and second set of single-bit-per-cell data are programmed into a third set of nonvolatile cells as multiple-bit-per-cell data. See ¶[0218]. Furthermore, the ’105 publication strengthens this disclosure by expressly teaching that four SLC blocks are folded into a QLC block and that this full-folding operation is selected if four blocks are available. See ¶¶[0032]-[0033], [0037].
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have had reason to incorporate the source-block availability determination of the ‘105 publication into Sharon’s adaptive folding process for the following reasons:
Sharon already requires a plurality of low-bit-density source sets to perform a fold into a higher-bit-density target. The ’105 publication teaches that before performing such a full fold, the controller determines whether the required complement of SLC source blocks is available. Incorporating that known availability check into Sharon would predictably ensure that the source sets required by the selected folding operation are present before initiating the operation, thereby avoiding an incomplete fold and providing appropriate alternative processing when an insufficient number of source blocks is available. This would have amounted to use of a known memory-management technique according to its established function to obtain the predictable result of performing a full folding operation only when the required number of source blocks is available.
Claim 3: Sharon and the ‘105 publication teach the system of claim 1, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell. For instance, Sharon expressly teaches: SLC/single-bit-per-cell source data; and multiple-bit-per-cell destination data. Sharon, in ¶[0164], identifies single-bit-per-cell cells as SLC, and ¶[0165] identifies multiple-bit-per-cell cells as MLC, including an example storing three bits per cell. The ’105 publication ¶[0032] likewise expressly teaches one-bit SLC source blocks and three-bit TLC or four-bit QLC destination blocks.
Claim 4: Sharon and the ‘105 publication teach the system of claim 1, wherein the first set of memory cells are configured as single- level cell (SLC) memory. For instance, Sharon expressly states that memory cells storing single-bit-per-memory-cell data are referred to as single-level cells (“SLC”). See ¶[0164].
Claim 6: Sharon and the ‘105 publication teach the system of claim 1, wherein the data integrity metric value reflects at least one of a bit error count (BEC) value or a raw bit error rate (RBER) value. For instance, Sharon ¶[0204] expressly teaches BER as the measure of error. Sharon ¶[0085] further teaches estimating BER from an initial syndrome weight prior to full decoding, i.e., the error condition of the data as read from the source memory before correction.
Claims 8, 10, 11, 13, 17 and 19 recite method/computer readable medium limitations that substantially correspond to the system, limitations of claims 1, 3, 4 and 6, respectively. Accordingly, claims 8, 10, 11 and 13 are rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding system claims.
Claim(s) 2, 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sharon and the ‘105 publication as applied to claim 1 above, and further in view of Camp et al., US 2016/0110248 A1 (“Camp”).
Claim 2: Sharon and the ‘105 publication teach the system of claim 1, but fail to teach that the operations further comprise: responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, performing a further data integrity check on a third set of memory cells. However, Camp teaches a background health checker performing a read sweep, detecting bit errors, comparing the error information with thresholds, and then proceeding to additional page groups/blocks. Camp ¶[0047] compares the number of detected bit errors against calibration and relocation thresholds. More particularly, ¶[0055] teaches that when the bit errors for the currently tested page group do not exceed the relocation threshold, the controller determines whether additional page groups remain and, if so, selects the next page group and returns to the read-sweep operation. Thus, Camp teaches that a threshold result for one memory set causes an integrity/read-error check to proceed to another memory set. Therefore, it would have been obvious to apply Camp’s known sequential health-checking procedure to Sharon’s plurality of source sets so that, where the current source set does not meet the threshold condition that triggers the selected management action, the controller proceeds to check another source set. This allows the controller to identify additional suitable source data for the memory-management operation without unnecessarily terminating the management process.
Claims 9, and 16 recite method/computer readable medium limitations that substantially correspond to the system, limitations of claim 2 above. Accordingly, claims 9 and 16 are rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding system claims.
Claim(s) 5, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sharon and the ‘105 publication as applied to claim 1 above, and further in view of Takafuji et al., US 2014/0160842 A1 (“Takafuji”).
Claim 5: Sharon and the ‘105 publication teach the system of claim 1, but fail to teach that the second set of memory cells are configured as higher- level cell (HLC) memory. However, Takafuji, in ¶[0054], teaches memory systems designed and manufactured as MLC memory systems in which some or all of the physical MLC cells are nevertheless operated in SLC mode, and explains that MLC and SLC blocks can be physically identical and simply operated differently. ¶¶[0056]-[0057] further teaches operating MLC cells in SLC mode by assigning only two MLC states for SLC operation. Therefore, it would have been obvious to implement Sharon’s single-bit source sets using physically higher-level/MLC-capable memory operated temporarily in SLC mode because Takafuji teaches that such an arrangement provides faster programming/read performance and improved retention/disturb characteristics while permitting use of the same physically multi-level memory.
Claim 12 is rejected similarly to claim 5 above.
As per claim 18, Sharon expressly states that memory cells storing single-bit-per-memory-cell data are referred to as single-level cells (“SLC”). See ¶[0164]. And Takafuji, in ¶[0054], teaches memory systems designed and manufactured as MLC memory systems in which some or all of the physical MLC cells are nevertheless operated in SLC mode, and explains that MLC and SLC blocks can be physically identical and simply operated differently. ¶¶[0056]-[0057] further teaches operating MLC cells in SLC mode by assigning only two MLC states for SLC operation. Therefore, it would have been obvious to implement Sharon’s single-bit source sets using physically higher-level/MLC-capable memory operated temporarily in SLC mode because Takafuji teaches that such an arrangement provides faster programming/read performance and improved retention/disturb characteristics while permitting use of the same physically multi-level memory.
Claim(s) 7, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sharon and the ‘105 publication as applied to claim 1 above, and further in view of Agarwal et al., US 2016/0092129 A1 (“Agarwal”).
Claim 7: Sharon and the ‘105 publication teach the system of claim 1, but fail to teach that the operations further comprise: responsive to determining that the threshold number of second sets of memory cells are not available, causing the memory device to copy data from the first set of memory cells and from the threshold number of second sets of memory cells to a fourth set of memory cells configured to store the first number of bits per memory cell. However, Agarwal ¶[0037] teaches a folding operation in which valid data suitable for folding is moved from SLC to an MLC destination, while other valid data is copied “to another SLC block for compaction.” Agarwal further teaches that multiple SLC blocks are processed to collect data for the folding operation, while data not directed to the MLC folding path is directed to an SLC compaction block. See ¶¶[0044]-[0047]. Agarwal ¶[0048] expressly describes the compaction process as:
“a copy from the selected SLC block to a new SLC compaction block.”
Thus:
the ’105 publication teaches determining that the source-block complement required for the normal/full fold is unavailable; and
Agarwal teaches the known alternative of relocating/compacting source data into another SLC destination instead of folding it into the higher-density destination.
A person of ordinary skill would have had reason to employ Agarwal’s SLC-compaction alternative when the full complement of source sets required for the higher-density fold is unavailable, because doing so preserves/consolidates the source data in low-density storage until the conditions required for a later full folding operation are met, while also freeing source storage resources.
Claim 14 and 20 are rejected similarly to claim 7 above.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111
8/21/2026
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