DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 6 and 14 of U.S. Patent No. 12,329,005. Although the claims at issue are not identical, they are not patentably distinct from each other because all claimed limitations of claims 1-3 and 11 of the instant application are encompassed by claims 1-3, 6 and 14 of the patent as follow:
Instant application (claim 1)
U.S. 12,329,005 (claims 1, 6)
An electronic device comprising:
An electronic device comprising:
a display panel comprising: signal lines; a first pixel; a second pixel; a third pixel; a fourth pixel; a fifth pixel; and a sixth pixel,
a display panel comprising: signal lines; a first pixel; a second pixel; a third pixel; and a fourth pixel; a fifth pixel; and a sixth pixel (claim 6)
wherein each of the first to sixth pixels comprises a light-emitting element, a first
transistor electrically connected to the light-emitting element, and a second transistor electrically connected to a source or a drain of the first transistor,
wherein each of the first-to-fourth pixels comprises: a light-emitting element; a first transistor electrically connected to the light-emitting element; a second transistor electrically connected to a source or a drain of the first transistor;
wherein a hole penetrates the display panel, the first pixel and the second pixel are disposed with the hole interposed therebetween and arranged in a same pixel row, the third pixel and the fourth pixel are disposed with the hole interposed therebetween and arranged in a same pixel row, and wherein the first-first line and the first-second line are disposed with the hole interposed therebetween and the second-first line and the second-second line are disposed with the hole interposed therebetween;
a hole penetrates the display panel; the first pixel, the second pixel, the third pixel, and the fourth pixel are disposed outside the hole; the first pixel and the second pixel are disposed with the hole interposed therebetween; and a connection line disposed outside the hole and electrically connected to the first-first line and the second-second line, wherein the first pixel and the third pixel arranged in different pixel rows;
wherein the signal lines comprise: a first-first line electrically connected to the second transistor of the first pixel; a first-second line electrically connected to the second transistor of the second pixel; a second-first line electrically connected to the second transistor of the third pixel; and a second-second line electrically connected to the second transistor of the fourth pixel.
a first-first line electrically connected to the second transistor of the first pixel; a first-second line electrically connected to the third transistor of the first pixel and the third transistor of the second pixel; a second-first line electrically connected to the second transistor of the third pixel; a second-second line electrically connected the third transistor of the fourth pixel.
Regarding claim 2, see claim 2 of the patent.
Regarding claim 3, see claim 3 of the patent.
Regarding claim 11, see claim 14 of the patent.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-6 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2016/0363909).
Regarding claim 1, Kang discloses an electronic device (1000, fig. 6, para. 0117) comprising:
a display panel (100, fig. 1, para. 0061) comprising:
signal lines (LI1, LI2, Sn, Sn-1, Sn-2, para. 0092);
a first pixel (such as a first left pixel PX connected to the first line LI1 neighbor the through-hole TH, fig. 1, para. 0012);
a second pixel (such as a first right pixel PX connected to the first line LI1 neighbor the through-hole TH);
a third pixel (such as a second left pixel PX connected to the first line LI1 neighbor the through-hole TH);
a fourth pixel (such as a second right pixel PX connected to the first line LI1 neighbor the through-hole TH);
a fifth pixel (such as a upper pixel PX connected to the second line LI2 neighbor the through-hole TH, fig. 1, para. 0098); and
a sixth pixel (such as a lower pixel PX connected to the second line LI2 neighbor the through-hole TH),
wherein each of the first to sixth pixels (PX, fig. 3, para. 0073) comprises a light-emitting element (OLED), a first transistor (T1) electrically connected to the light-emitting element, and a second transistor (T2) electrically connected to a source or a drain of the first transistor,
wherein a hole (TH, para. 0064) penetrates the display panel (100), the first pixel and the second pixel are disposed with the hole interposed therebetween and arranged in a same pixel row, the third pixel and the fourth pixel are disposed with the hole interposed therebetween and arranged in a same pixel row (para. 0012), and
wherein the signal lines comprise:
a first-first line (Sn, left side of the through-hole TH) electrically connected to the second transistor (T2) of the first pixel;
a first-second line (Sn, right side of the through-hole TH) electrically connected to the second transistor (T2) of the second pixel;
a second-first line (Sn+1, left side of the through-hole TH) electrically connected to the second transistor (T2) of the third pixel; and
a second-second line (Sn+1, right side of the through-hole TH) electrically connected to the second transistor (T2) of the fourth pixel,
wherein the first-first line and the first-second line are disposed with the hole interposed therebetween and the second-first line and the second-second line are disposed with the hole interposed therebetween (paras. 0092-0093).
Regarding claim 3, Kang discloses an optical film on the display panel (para. 0061-0062).
Regarding claim 4, Kang discloses the fifth pixel (such as a upper pixel PX connected to the second line LI2 neighbor the through-hole TH, fig. 1, para. 0098) and the sixth pixel (such as a lower pixel PX connected to the second line LI2 neighbor the through-hole TH) are disposed with the hole (TH) interposed therebetween and arranged in a same pixel column;
the signal lines further comprise a first-first data line (such as upper straight line of LI2, fig. 1) electrically connected to the fifth pixel, a first-second data line (such as lower straight line of LI2, fig. 1) electrically connected to the sixth pixel and a column connection line (such as curved line around the though-hole TH) electrically connected to the first-first data line and the first-second data line;
the first-first data line (upper straight line of LI2) of and the first-second data line (lower straight line of LI2) are disposed with the hole (TH) interposed therebetween; and
the column connection line (curved line around the though-hole TH) is disposed outside the hole.
Regarding claim 5, Kang discloses the first-first line (Sn, left side of the through-hole TH) and the first-second line (Sn, right side of the through-hole TH) are disposed with the column connection line (curved line around the though-hole TH) interposed therebetween (fig. 1).
Regarding claim 6, Kang discloses the column connection line (curved line around the though-hole TH) is disposed between the hole (TH) and an end of the first-first line (Sn, left side of the through-hole TH) or between the hole (TH) and an end of the first-second line (Sn, right side of the through-hole TH).
Regarding claim 9, Kang discloses the fifth pixel (upper pixel PX connected to the second line LI2 neighbor the through-hole TH, fig. 1, para. 0098) and the sixth pixel (lower pixel PX connected to the second line LI2 neighbor the through-hole TH) are disposed with the hole (TH) interposed therebetween and arranged in a same pixel column;
the signal lines further comprise a data line (LI2) electrically connected to the fifth pixel and the sixth pixel; and
the first-first line (Sn, left side of the through-hole TH) and the first-second line (Sn, right side of the through-hole TH) are disposed with the data line interposed therebetween (fig. 1).
Regarding claim 10, Kang discloses each of the first to sixth pixels (PX, fig. 3) further comprises a third transistor (T3) electrically connected to a gate of the first transistor (T1),
the signal lines further comprises a second-third line (such as line connects G3 and Sn, fig. 3) electrically connected to the third transistor of the third pixel and first-first line.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 7-8 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Ka et al. (US 2017/0294502).
Regarding claim 2, Kang does not specifically disclose an electro-optical module configured to transmit or receive an optical signal through the hole.
In a similar filed of display device, Ka discloses an electro-optical module (“camera module”, fig. 1, para. 0056) configured to transmit or receive an optical signal through the hole (FA).
Therefore, it would have been obvious to one of ordinary skill in the art before effective filling date of the claimed invention to incorporate the electro-optical module as taught by Ka in the system of Kang in order to increase functionality for a small-sized electronic device.
Regarding claim 7, the combination of Kang and Ka discloses the first-first line (SL1) and the column connection line (DT1) are disposed on a same layer (para. 0069, fig. 3 of ka).
Regarding claim 8, the combination of Kang and Ka discloses the column connection line (DT3) and the first-first line (SL1) are disposed on different layers; and
the column connection line is connected to the first-first data line through at least one contact hole (fig. 3 of Ka).
Regarding claim 11, the combination of Kang and Ka discloses a semiconductor pattern (120, fig. 3, paras. 0089-0092 of Ka);
a gate (135) overlapping the semiconductor pattern;
the source (155) of the first transistor extended from the semiconductor pattern; and
the drain (150) of the first transistor extended from the semiconductor pattern.
Regarding claim 12, the combination of Kang and Ka discloses the first-first line and the second-first line are disposed in a same layer as the gate (such as the gate 135 and SL1 disposed on the same first gate insulation layer 130, fig. 3 of Ka, para. 0094).
Regarding claim 13, the combination of Kang and Ka discloses the display panel further comprises a first scan driving circuit (such as left gate driving part) electrically connected to the first-first line and the second-first line and a second scan driving circuit (such as right gate driving part) electrically connected to the first-second line and the second-second line (paras. 0071-0072 of Ka).
Regarding claim 14, the combination of Kang and Ka discloses the first scan driving circuit and the second scan driving circuit are disposed with the hole interposed therebetween (gate driving parts disposed at both sides of the peripheral area PA, para. 0071 of Ka)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Choi et al. (US 2017/0162637) disclose a display area DA is a region in which the pixel array is located, and an image is provided by using light emitted by a plurality
of pixels PX in the display area DA. The substrate includes a through hole (through portion) TH passing through the substrate. The through hole TH is surrounded by a plurality of pixels (paras. 0076-0077).
Kaise et al. (US 2019/0259349 A1) disclose the gate driver GD1 and the gate driver GD2 are provided in a non-display area NA which surrounds the display area DA. The display area DA includes a side area SA1 that is located by one of sides of the cutout NZ which sides face each other in a direction in which the scanning signal lines extend (a right-and-left direction of (a) of FIG. 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER T NGUYEN whose telephone number is (571)272-7696. The examiner can normally be reached Mon-Fri 7:00-5:00.
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/JENNIFER T NGUYEN/ Primary Examiner, Art Unit 2629