Prosecution Insights
Last updated: October 25, 2026
Application No. 19/216,685

CONTROL CIRCUIT AND CONTROL METHOD THEREOF

Non-Final OA §112
Filed
May 22, 2025
Priority
May 30, 2024 — CN 202410686038.2
Examiner
ZAMAN, FAISAL M
Art Unit
2175
Tech Center
2100 — Computer Architecture & Software
Assignee
Coretronic Corporation
OA Round
1 (Non-Final)
67%
Grant Probability
Favorable
1-2
OA Rounds
1y 5m
Est. Remaining
80%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
634 granted / 943 resolved
+12.2% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
29 currently pending
Career history
982
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
65.5%
+25.5% vs TC avg
§102
15.4%
-24.6% vs TC avg
§112
11.5%
-28.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 943 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding Claim 1, in the last two lines of the claim, it is stated "after being activated, the second circuit receives the first signal from the first circuit and enters a firmware mode". However, earlier in the claim (lines 11-12), it is stated that "the first circuit provides a first signal to a preset pin of the second circuit after completing the initial setting". In lines 13-17, it is stated "after the first circuit provides the first signal to the second circuit ... the switch unit converts the first voltage from the power converter into a third voltage to be provided to the second circuit, so that the second circuit is activated". Therefore, in one portion of the claim, the second circuit receives the "first signal" before it is activated, but in another portion of the claim, the second circuit receives the "first signal" after it is activated. Accordingly, it is unclear as to when the second circuit actually receives the "first signal". The examiner will presume for examination purposes that the second circuit receives the first signal before it is activated but only acts upon it/reads it once the third voltage is provided to the second circuit. Appropriate correction/clarification is required. Regarding Claim 8, in the last three lines of the claim, it is stated "after being activated, the second circuit receives the first signal from the first circuit and enters a firmware mode". However, earlier in the claim (lines 10-11), it is stated that "providing a first signal to a preset pin of the second circuit after the first circuit completes the initial setting". In lines 12-16, it is stated "controlling the switch unit to turn on the power supply path between the power converter and the second circuit via the first circuit after the first circuit provides the first signal to the second circuit; and making the switch unit convert the first voltage from the power converter into a third voltage to be provided to the second circuit to activate the second circuit". Therefore, in one portion of the claim, the second circuit receives the "first signal" before it is activated, but in another portion of the claim, the second circuit receives the "first signal" after it is activated. Accordingly, it is unclear as to when the second circuit actually receives the "first signal". The examiner will presume for examination purposes that the second circuit receives the first signal before it is activated but only acts upon it/reads it once the third voltage is provided to the second circuit. Appropriate correction/clarification is required. All claims that are not specifically addressed are rejected due to a dependency. Allowable Subject Matter Claims 1-14 would be allowable if the § 112 rejection discussed above was addressed. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 1, the prior art of record does not teach “wherein the first circuit is configured to receive a firmware update command and control the power converter to provide a first voltage to the switch unit according to the firmware update command, and the first circuit performs an initial setting; the first circuit provides a first signal to a preset pin of the second circuit after completing the initial setting; and after the first circuit provides the first signal to the second circuit, the first circuit controls the switch unit to turn on the power supply path between the power converter and the second circuit, so that the switch unit converts the first voltage from the power converter into a third voltage to be provided to the second circuit, so that the second circuit is activated, and after being activated, the second circuit receives the first signal from the first circuit and enters a firmware update mode”, in conjunction with the other limitations in the claim. Regarding Claim 8, the prior art of record does not teach “receiving a firmware update command via the first circuit and controlling the power converter to provide a first voltage to the switch unit according to the firmware update command, and performing an initial setting via the first circuit; providing a first signal to a preset pin of the second circuit after the first circuit completes the initial setting; controlling the switch unit to turn on the power supply path between the power converter and the second circuit via the first circuit after the first circuit provides the first signal to the second circuit; and making the switch unit convert the first voltage from the power converter into a third voltage to be provided to the second circuit to activate the second circuit, and after being activated, the second circuit receives the first signal from the first circuit and enters a firmware update mode”, in conjunction with the other limitations in the claim. The closest prior art references of record are Yang (U.S. Patent Application Publication Number 2023/0231475) and Krzyzanowski et al. (U.S. Patent Application Publication Number 2011/0283274). Yang discloses a control circuit, wherein the control circuit comprises a power converter, a switch unit, a first circuit, and a second circuit, wherein, the first circuit is coupled to the power converter, the second circuit, and the switch unit; the switch unit is coupled between the power converter and the second circuit and configured to turn on or turn off a power supply path between the power converter and the second circuit (see Yang, Figure 1). However, Yang’s "first circuit" 12 does not "control the power converter (16)" as required by the claims. Rather, it controls the switch 10 to provide voltage to "second circuit" 2. First circuit 12 does not provide a first signal to the preset pin of the second circuit 2. Further, switch unit 10 does not convert voltage and second circuit 2 does not enter firmware update mode (only the power supply 1 updates its firmware). Krzyzanowski discloses that first processor 102 is configured to populate shared memory 106 with the appropriate boot code (i.e., firmware) for second processor 104. First processor 102 is further configured to trigger second processor 104 to initiate a boot. First processor 102 may trigger second processor 104 to initiate the boot by sending one or more messages via shared memory 106 or by sending one or more messages over a network or some other communication path between first processor 102 and second processor 104. However, Krzyzanowski does not disclose controlling a power converter to provide a first voltage to the switch unit according to the firmware update command, the first circuit controlling the switch unit to turn on the power supply path between the power converter and the second circuit, so that the switch unit converts the first voltage from the power converter into a third voltage to be provided to the second circuit, so that the second circuit is activated, and after being activated, the second circuit receives the first signal from the first circuit and enters a firmware update mode as required by the claims. Accordingly, the claims are allowable. All claims that are not specifically addressed are allowable due to a dependency. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a circuit for updating circuit firmware. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
Read full office action

Prosecution Timeline

May 22, 2025
Application Filed
Oct 08, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
67%
Grant Probability
80%
With Interview (+13.3%)
2y 10m (~1y 5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 943 resolved cases by this examiner. Grant probability derived from career allowance rate.

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