CTNF 19/217,677 CTNF 80228 Detail Action Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 2. The instant application having application No. 19/217,677 has a total of 20 claims pending in the application; there are 2 independent claim and 18 dependent claims, all of which are ready for examination by the examiner. ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT Information Disclosure Statement 3. As required by M.P.E.P. 2001.06(b) and 37 C.F.R. 1.98(d) , since the instant application has been identified as a continuation application of an earlier filed application and is relied upon for an earlier filing date under 35 U.S.C. 120 , the examiner has reviewed the prior art cited in the earlier related application as required by M.P.E.P. 707.05 and 904 and as stated in M.P.E.P. 2001.06(b), no separate citation of the same prior art need be made by the applicants in the instant application. INFORMATION CONCERNING IDS: 4. The information disclosure statement (IDS) submitted on 05/23/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner INFORMATION CONCERNING FOREIGN PRIORITY: 5. Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on 08/06/2021. INFORMATION CONCERNING CLAIMS: Double Patenting Rejection 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA 6. Claim s 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-15 and 20 of U.S. Patent No. 12,333,141 B2 (hereinafter “ the patent ”) . Although the claims at issue are not identical, they are not patentably distinct from each other because the minor differences in use and order of word and/or limitation(s) in the claims, do not make the two set of claims patentably distinct from each other patentably distinct from each other. For example, the independent claim 21 of the instant application recites: determine an interval between transmitting a first instruction to the non- volatile memory and transmitting a second instruction to non-volatile memory ”. While the independent claim of the patent recites: “the second instruction is transmitted to the non-volatile memory after a first period following transmission of the first instruction elapses”. However, as has been described in the specs. of both instant application and the patent, the time period or interval is determined according to setting and expiration of timer(s) . 7. Claims of the instant application (e.g., Application 19/217,677) are compared to claims of US Patent 12,333,141 B2 in table below: US Patent 12,333,141 B2 US Application 19/217,677 1. A memory system comprising: a non-volatile memory including at least one memory chip; a controller electrically coupled to the non-volatile memory, and configured to: transmit a first instruction to the non-volatile memory; transmit a second instruction to the non-volatile memory after transmitting the first instruction; determine whether the non-volatile memory includes an interface chip; and in response to determining that the non-volatile memory includes the interface chip, the second instruction is transmitted to the non-volatile memory after a first period following transmission of the first instruction elapses, in response to determining that the non-volatile memory does not include the interface chip, the second instruction is transmitted to the non-volatile memory after a second period following transmission of the first instruction elapses , and the first period is different from the second period. 21. A memory system comprising: a non-volatile memory including at least one memory chip; a controller electrically coupled to the non-volatile memory, and configured to: determine whether the non-volatile memory includes an interface chip; and determine an interval between transmitting a first instruction to the non-volatile memory and transmitting a second instruction to non-volatile memory. 1. A memory system comprising: …. the second instruction is transmitted to the non-volatile memory after a first period following transmission of the first instruction elapses, in response to determining that the non-volatile memory does not include the interface chip, the second instruction is transmitted to the non-volatile memory after a second period following transmission of the first instruction elapses , and the first period is different from the second period. 22. The memory system according to claim 21, wherein the controller is configured to: wait for the determined interval ; and transmit the second instruction after the determined interval elapses . 1. A memory system comprising: …. determine whether the non-volatile memory includes an interface chip; and in response to determining that the non-volatile memory includes the interface chip, the second instruction is transmitted to the non-volatile memory after a first period following transmission of the first instruction elapses, in response to determining that the non-volatile memory does not include the interface chip, the second instruction is transmitted to the non-volatile memory after a second period following transmission of the first instruction elapses, and the first period is different from the second period . 23. The memory system according to claim 22, wherein the controller is configured to: in response to determining that the non-volatile memory includes the interface chip, determine a first interval as the interval, and transmit the second instruction to the non-volatile memory after the first interval elapses; and in response to determining that the non-volatile memory does not include the interface chip, determine a second interval as the interval, and transmit the second instruction to the non-volatile memory after the second interval elapses; wherein the first interval is different from the second interval . 2. The memory system according to claim 1, wherein the first instruction and the second instruction form a series of sequences. 24. The memory system according to claim 21, wherein the first instruction and the second instruction form a series of sequences. 3. The memory system according to claim 1, wherein the controller is further configured to store data indicating whether the non-volatile memory includes the interface chip. 25. The memory system according to claim 21, wherein the controller is further configured to store data indicating whether the non-volatile memory includes the interface chip. 4. The memory system according to claim 3, wherein the controller is further configured to, before transmitting the first and second instructions to the non-volatile memory, transmit a third instruction to the non-volatile memory, and store data indicating whether the non-volatile memory includes the interface chip based on a response for the third instruction from the non-volatile memory. 26. The memory system according to claim 25, wherein, before transmitting the first and second instructions to the non-volatile memory, the controller is further configured to: transmit a third instruction to the non-volatile memory; and store data indicating whether the non-volatile memory includes the interface chip based on a response for the third instruction from the non-volatile memory. 5. The memory system according to claim 3, wherein the data indicating whether the non-volatile memory includes the interface chip is generated at the time of manufacture of the memory system. 27. The memory system according to claim 25, wherein the data indicating whether the non-volatile memory includes the interface chip is generated at the time of manufacture of the memory system. 6. The memory system according to claim 5, wherein the controller is further configured to determine whether to use the first period or the second period as a period between transmitting the first instruction and transmitting the second instruction based on a correspondence table in which the data indicating whether the non-volatile memory includes the interface chip and a physical address of the non-volatile memory are associated. 28. The memory system according to claim 27, wherein the controller is further configured to determine whether to use the first interval or the second interval as the interval between transmitting the first instruction and transmitting the second instruction based on a correspondence table in which the data indicating whether the non-volatile memory includes the interface chip and a physical address of the non-volatile memory are associated. 7. The memory system according to claim 1, wherein the controller and the non-volatile memory are electrically coupled by a first signal line, the first instruction is one of assertion and negation of a first signal transmitted from the controller to the non-volatile memory via the first signal line, and the second instruction is another one of assertion and negation of the first signal. 29. The memory system according to claim 21, wherein the controller and the non-volatile memory are electrically coupled by a first signal line, the first instruction is one of assertion and negation of a first signal transmitted from the controller to the non-volatile memory via the first signal line, and the second instruction is another one of assertion and negation of the first signal. 8. The memory system according to claim 1, wherein the controller and the non-volatile memory are electrically coupled by a first signal line and a second signal line, the first instruction is assertion of a first signal transmitted from the controller to the non-volatile memory via the first signal line, and the second instruction is assertion of a second signal transmitted from the controller to the non-volatile memory via the second signal line. 30. The memory system according to claim 21, wherein the controller and the non-volatile memory are electrically coupled by a first signal line and a second signal line, the first instruction is assertion of a first signal transmitted from the controller to the non-volatile memory via the first signal line, and the second instruction is assertion of a second signal transmitted from the controller to the non-volatile memory via the second signal line. 9. The memory system according to claim 1, wherein the second period is shorter than the first period. 31. The memory system according to claim 23, wherein the second interval is shorter than the first interval. 10. The memory system according to claim 1, wherein the controller is further configured to: transmit, to the non-volatile memory, an instruction indicating a timing of taking in a command for requesting output of data from the non-volatile memory, as the first instruction, and transmit, to the non-volatile memory, an instruction indicating a timing of output of the data from the non-volatile memory, as the second instruction. 32. The memory system according to claim 21, wherein the controller is further configured to: transmit, to the non-volatile memory, an instruction indicating a timing of taking in a command for requesting output of data from the non-volatile memory, as the first instruction, and transmit, to the non-volatile memory, an instruction indicating a timing of output of the data from the non-volatile memory, as the second instruction. 11. The memory system according to claim 1, wherein the controller includes at least one of a system-on-a-chip (SoC), a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). 33. The memory system according to claim 21, wherein the controller includes at least one of a system-on-a-chip (SoC), a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). 12. The memory system according to claim 1, wherein the non-volatile memory includes at least one of a NAND flash memory, a magnetoresistive random access memory (MRAM), a phase change random access memory (PCRAM), or a resistive random access memory (ReRAM). 34. The memory system according to claim 21, wherein the non-volatile memory includes at least one of a NAND flash memory, a magnetoresistive random access memory (MRAM), a phase change random access memory (PCRAM), or a resistive random access memory (ReRAM). 13. A method of controlling a plurality of non-volatile memories each having at least one memory chip, the plurality of the non-volatile memories including at least a first non-volatile memory and a second non-volatile memory, the method comprising: transmitting a first instruction to the first non-volatile memory and the second non-volatile memory; and determining that the first non-volatile memory includes an interface chip ; in response to determining that the first non-volatile memory includes the interface chip, transmitting a second instruction to the first non-volatile memory after a first period following the first instruction elapses , determining that the second non-volatile memory does not include the interface chip; and in response to determining that the second non-volatile memory does not include the interface chip, transmitting the second instruction to the second non-volatile memory after a second period following the first instruction elapses, the second period being different from the first period. 35. A method of controlling a plurality of non-volatile memories each having at least one memory chip, the plurality of the non-volatile memories including at least a first non-volatile memory and a second non-volatile memory, the method comprising: determining that a first non-volatile memory and a second non-volatile memory includes an interface chip ; and determining an interval between transmitting a first instruction to non-volatile memory and transmitting a second instruction to non-volatile memory. 13. A method…comprising: … in response to determining that the first non-volatile memory includes the interface chip, transmitting a second instruction to the first non-volatile memory after a first period following the first instruction elapses, … …. 36. The method according to claim 35, further comprising: waiting for the determined interval; and transmitting the second instruction to the first non-volatile memory and the second non-volatile memory after the determined interval elapses . 13. A method…comprising: … determining that the first non-volatile memory includes an interface chip; in response to determining that the first non-volatile memory includes the interface chip, transmitting a second instruction to the first non-volatile memory after a first period following the first instruction elapses , determining that the second non-volatile memory does not include the interface chip; and in response to determining that the second non-volatile memory does not include the interface chip, transmitting the second instruction to the second non-volatile memory after a second period following the first instruction elapses, the second period being different from the first period . 37. The method according to claim 36, further comprising: determining that the first non-volatile memory includes the interface chip; in response to determining that the first non-volatile memory includes the interface chip, determining a first interval as the interval; transmitting the second instruction to the first non-volatile memory after the first interval elapses , determining that the second non-volatile memory does not include the interface chip; in response to determining that the second non-volatile memory does not include the interface chip, determining a second interval as the interval; and transmitting the second instruction to the second non-volatile memory after the second interval elapses, and wherein the second interval is different from the first interval . 14. The method according to claim 13, wherein the first instruction and the second instruction form a series of sequences. 38. The method according to claim 35, wherein the first instruction and the second instruction form a series of sequences. 15. The method according to claim 13, further comprising: storing data indicating whether the plurality of the non-volatile memories each includes the interface chip. 39. The method according to claim 35, further comprising: storing data indicating whether the plurality of the non-volatile memories each includes the interface chip. 20. The method according to claim 13, wherein the second period is shorte r than the first period . 40. The method according to claim 35, wherein the second interval is shorter than the first interval . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 21 and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. “Park” (US 2021/0208815 A1) in view of JUNG et al. “Jung” (US 2016/0321002 A1) . 8. Regarding claim 21, Park teaches or suggests: “A memory system (e.g., Fig. 1) comprising: a non-volatile memory including at least one memory chip;” (e.g., Fig. 1, ¶ 0024, non-volatile memory device 100). “a controller electrically coupled to the non-volatile memory (e.g., Fig. 1, ¶ 0024) , and configured to: “and determine an interval between transmitting a first instruction to the non-volatile memory and transmitting a second instruction to non-volatile memory.” (e.g., Abstract; Fig. 13, ¶ 0140, controller 200 issues the read command CMD_R in response to the read request (S10); ¶ 0141, wait for t1 time (S20)); ¶ 0142, the controller 200 issues the second readout command CMD_O2 that allows the nonvolatile memory device 100 to output both the status information signal Status and the read data (S30)). The t1(time) is the determined waiting time (e.g., interval) between issuing (e.g., transmitting) a first instruction and a second instruction to the non-volatile memory. However, Park does not appear to expressly teach while: Jung discloses: “determine whether the non-volatile memory includes an interface chip;” (e.g., Figs. 1 and 14, ¶ 0112, interface chip configuration information (FBI-1 SET) indicating that the first interface chip FBI_1 exists as well as the second interface chip FBI-2; Figs. 6 and 14 and the corresponding text descriptions) configuration information indicates the interface chip exists. Disclosures by Park and Jung are analogous because they are in the same field of endeavor and/or solving a similar or common problem. It would have been obvious to a person of having ordinary skill in art before the effective filing date of claim invention to modify the storage device and operating method taught By Park to include the configuration information indicating whether interface chip(s) exists disclosed by Jung. The motivation for including the configuration information indicating whether interface chip(s) exists as taught paragraph [0048] of Jung is to enable stable execution of initialization operation of the storage device. Therefore, it would have been obvious to combine teaching of Jung with Park to obtain the invention as specified in the claim. 9. Regarding claim 35, Park teaches or suggests: “A method of controlling a plurality of non-volatile memories each having at least one memory chip, the plurality of the non-volatile memories including at least a first non-volatile memory and a second non-volatile memory ;” (e.g., Fig. 15, ¶ 0155, memory devices 1230, 1240, and 1250 are connected to the SSD controller 1210) , the method comprising: and determining an interval between transmitting a first instruction to non-volatile memory and transmitting a second instruction to non-volatile memory.” (e.g., Abstract; Fig. 13, ¶ 0140, controller 200 issues the read command CMD_R in response to the read request (S10); ¶ 0141, wait for t1 time (S20)); ¶ 0142, the controller 200 issues the second readout command CMD_O2 that allows the nonvolatile memory device 100 to output both the status information signal Status and the read data (S30)). The t1(time) is the determined waiting time (e.g., interval) between issuing (e.g., transmitting) a first instruction and a second instruction to the non-volatile memory. However, Park does not appear to expressly teach while: Jung discloses: “determining that a first non-volatile memory and a second non-volatile memory includes an interface chip;” (e.g., Figs. 1 and 14, ¶ 0112, interface chip configuration information (FBI-1 SET) indicating that the first interface chip FBI_1 exists as well as the second interface chip FBI-2; Figs. 6 and 14 and the corresponding text descriptions) configuration information indicates the interface chips exist. The motivation for combining is based on the same rational presented above with respect to the independent claim 21. 10. Regarding claims 22 and 36, taking claim 22 as exemplary, Park further teaches: “wherein the controller is configured to: wait for the determined interval; and transmit the second instruction after the determined interval elapses.” (e.g., Fig. 13, ¶ 0141, the controller 200 waits for a first time interval t1, S20 in Fig. 13). 11. Regarding claims 24 and 38, taking claim 24 as exemplary, Park further teaches: “wherein the first instruction and the second instruction form a series of sequences.” (e.g., ¶ 0097, FIG. 7 is a timing diagram that illustrates a time sequence of signals and commands). 12. Regarding claim 25 and 39, taking claim 24 as exemplary, Jung further teaches: “wherein the controller is further configured to store data indicating whether the non-volatile memory includes the interface chip.” (e.g., Figs. 1 and 14, ¶ 0112, interface chip configuration information (FBI-1 SET) indicating that the first interface chip FBI_1 exists as well as the second interface chip FBI-2; Figs. 6 and 14 and the corresponding text descriptions) configuration information indicates the interface chip exists. 13. Regarding claim 26, Park further teaches: “wherein the controller is further configured to, … transmitting the first and second instructions to the non-volatile memory, transmit a third instruction to the non-volatile memory,” (e.g., Figs. 7-9 and 13, ¶¶ 0140-0144 of Park). Jung teaches: “ and store data indicating whether the non-volatile memory includes the interface chip based on a response for the third instruction from the non-volatile memory.” (e.g., ¶ 0100, the configuration information related to one or more nonvolatile memory devices 120 and/or associated internal channel(s), as well as certain configuration information associated with the interface chip 110; ¶ 0112, configuration information (FBI-1 SET) indicating that the first interface chip FBI_1 exists” . 14. Regarding claim 29, Park further teaches: “wherein the controller and the non-volatile memory are electrically coupled by a first signal line (e.g., Fig. 1, ¶ 0032, According to an embodiment, the control logic 110 receives the read enable signal REB from the controller 200) , the first instruction is one of assertion and negation of a first signal transmitted from the controller to the non-volatile memory via the first signal line, and the second instruction is another one of assertion and negation of the first signal.” (e.g., Fig. 7, ¶ 0099, at a time point t2 that is a transition time point, such as a rising edge or a falling edge, of the write enable signal WEB, the read command CMD_R is issued and transferred to the nonvolatile memory device 100; (e.g., Fig. 8, ¶ 0112, The controller 200 transitions a level of the write enable signal WEB to issue the second readout command CMD_O2). The first read command CMD_R is the first command issued, by the controller, to the non-volatile memory. The second read command CMD_O2 issued to read-out the data. the timing diagram of Figs. 7 and 8 show signal (e.g., WEB and REB) associated with read commands. 15. Regarding claim 30, Park further teaches: “wherein the controller and the non-volatile memory are electrically coupled by a first signal line and a second signal line, the first instruction is assertion of a first signal transmitted from the controller to the non-volatile memory via the first signal line (e.g., Fig. 7, ¶ 0099, at a time point t2 that is a transition time point, such as a rising edge or a falling edge, of the write enable signal WEB, the read command CMD_R is issued and transferred to the nonvolatile memory device 100; (e.g., Fig. 8, ¶ 0112, The controller 200 transitions a level of the write enable signal WEB to issue the second readout command CMD_O2) , and the second instruction is assertion of a second signal transmitted from the controller to the non-volatile memory via the second signal line.” (e.g., Fig. 8, ¶ 0112, The controller 200 transitions a level of the write enable signal WEB to issue the second readout command CMD_O2). The timing diagram of Fig. 8 shows relevant signals associated with the second read command CMD_O2. 16. Regarding claim 32, Park further teaches: “wherein the controller is further configured to: transmit, to the non-volatile memory, an instruction indicating a timing of taking in a command for requesting output of data from the non-volatile memory, as the first instruction, and transmit, to the non-volatile memory, an instruction indicating a timing of output of the data from the non-volatile memory, as the second instruction.” (e.g., Fig. 8, ¶ 0116, the third time interval Tc is obtained; Fig. 13 and its corresponding text description) . 07-22-aia AIA Claim s 33-34 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Jung as applied to claim 1 above, and further in view of IGAHARA et al. “Igahara” (US 2020/0387425 A1) . 17. Regarding claim 33, Park in view of Jung teach all limitations recited in claim 21 but does not expressly teach while: Igahara discloses: “wherein the controller includes at least one of a system-on-a-chip (SoC), a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).” (e.g., Fig. 1, ¶ 0032, the memory controller … configured as … a System on a Chip (SoC), a Field-Programmable Gate Array (FPGA), or an Application Specific Integrated Circuit (ASIC)). Disclosures by Park, Jung, and Igahara are analogous because they are in the same field of endeavor and/or solving a similar or common problem. It would have been obvious to a person of having ordinary skill in art before the effective filing date of claim invention to modify the storage device and operating method taught By Park to include the configuration information indicating whether interface chip(s) exists disclosed by Jung; furthermore, to include integrated circuits or chips disclosed by Igahara. The motivation for including the configuration information indicating whether interface chip(s) exists as taught paragraph [0048] of Jung is to enable stable execution of initialization operation of the storage device; furthermore, the motivation for using an integrated circuit furthermore, the motivation for the controller to include integrated circuits or chips as taught by paragraphs [0167]- [0168] of Igahara is to reduce the cost of memory chip or reduce power consumption. Therefore, it would have been obvious to combine teachings of Igahara and Jung with Park to obtain the invention as specified in the claim. 18. Regarding claim 34, Igahara further teaches or suggests: “wherein the non-volatile memory includes at least one of a NAND flash memory, a magnetoresistive random access memory (MRAM), a phase change random access memory (PCRAM), or a resistive random access memory (ReRAM).” (e.g., ¶ 0033, a NAND-type flash memory). Conclusion The prior art made of record and not relied upon are as follows: 1. KIM et al. (US 20210349660 A1) teaches “… a storage device includes; a non-volatile memory (NVM) package including an interface chip, first NVM devices connected to the interface chip through a first internal channel…” (par. 0007) 2. Yang et al. (US 20200167298 A1) teaches “…a controller 1000 may transmit, to the first stage, data input/output signals DQ[k: 0 ] including an address indicating the interface chip 2110 _ 1 of a semiconductor chip of the first stage that is to be selected…” (par. 0073) 3. CHU et al. (US 2018/0336960 A1) teaches “…The controller is configured to detect a program operation for a flash memory device; determine that a time period that satisfies a program threshold time has elapsed; send, after the time period that satisfies the program threshold time has elapsed, a first check status command; receive a first signal indicating a first status…” (par. 0005). Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. For questions regarding access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HASHEM FARROKH/ Primary Examiner, Art Unit 2138 Application/Control Number: 19/217,677 Page 2 Art Unit: 2138 Application/Control Number: 19/217,677 Page 3 Art Unit: 2138 Application/Control Number: 19/217,677 Page 4 Art Unit: 2138 Application/Control Number: 19/217,677 Page 5 Art Unit: 2138 Application/Control Number: 19/217,677 Page 6 Art Unit: 2138 Application/Control Number: 19/217,677 Page 7 Art Unit: 2138 Application/Control Number: 19/217,677 Page 8 Art Unit: 2138 Application/Control Number: 19/217,677 Page 9 Art Unit: 2138 Application/Control Number: 19/217,677 Page 10 Art Unit: 2138 Application/Control Number: 19/217,677 Page 11 Art Unit: 2138 Application/Control Number: 19/217,677 Page 12 Art Unit: 2138 Application/Control Number: 19/217,677 Page 13 Art Unit: 2138 Application/Control Number: 19/217,677 Page 14 Art Unit: 2138 Application/Control Number: 19/217,677 Page 15 Art Unit: 2138 Application/Control Number: 19/217,677 Page 16 Art Unit: 2138 Application/Control Number: 19/217,677 Page 17 Art Unit: 2138 Application/Control Number: 19/217,677 Page 18 Art Unit: 2138 Application/Control Number: 19/217,677 Page 19 Art Unit: 2138 Application/Control Number: 19/217,677 Page 20 Art Unit: 2138 Application/Control Number: 19/217,677 Page 21 Art Unit: 2138 Application/Control Number: 19/217,677 Page 22 Art Unit: 2138 Application/Control Number: 19/217,677 Page 23 Art Unit: 2138 Application/Control Number: 19/217,677 Page 24 Art Unit: 2138 Application/Control Number: 19/217,677 Page 25 Art Unit: 2138 Application/Control Number: 19/217,677 Page 26 Art Unit: 2138 Application/Control Number: 19/217,677 Page 27 Art Unit: 2138 Application/Control Number: 19/217,677 Page 28 Art Unit: 2138 Application/Control Number: 19/217,677 Page 29 Art Unit: 2138 Application/Control Number: 19/217,677 Page 30 Art Unit: 2138 Application/Control Number: 19/217,677 Page 31 Art Unit: 2138 Application/Control Number: 19/217,677 Page 32 Art Unit: 2138 Application/Control Number: 19/217,677 Page 33 Art Unit: 2138 Application/Control Number: 19/217,677 Page 34 Art Unit: 2138 Application/Control Number: 19/217,677 Page 35 Art Unit: 2138 Application/Control Number: 19/217,677 Page 36 Art Unit: 2138 Application/Control Number: 19/217,677 Page 37 Art Unit: 2138 Application/Control Number: 19/217,677 Page 38 Art Unit: 2138 Application/Control Number: 19/217,677 Page 39 Art Unit: 2138 Application/Control Number: 19/217,677 Page 40 Art Unit: 2138 Application/Control Number: 19/217,677 Page 41 Art Unit: 2138 Application/Control Number: 19/217,677 Page 42 Art Unit: 2138 Application/Control Number: 19/217,677 Page 43 Art Unit: 2138 Application/Control Number: 19/217,677 Page 44 Art Unit: 2138 Application/Control Number: 19/217,677 Page 45 Art Unit: 2138 Application/Control Number: 19/217,677 Page 46 Art Unit: 2138 Application/Control Number: 19/217,677 Page 47 Art Unit: 2138 Application/Control Number: 19/217,677 Page 48 Art Unit: 2138 Application/Control Number: 19/217,677 Page 49 Art Unit: 2138 Application/Control Number: 19/217,677 Page 50 Art Unit: 2138
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