DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/17/2025 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 5-14 and 23-24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3-16 of U.S. Patent No. 12,322,718 in view of Lee (US 2020/0135594).
Regarding claim 5 of the pending application, US Patent teaches a method of manufacturing a bonded structure (see claim 3’s preamble), the method comprising:
providing an interposer element having an upper surface at a first side and a lower surface at a second side, wherein the upper surface comprises a first conductive pad, a second conductive pad, and a non-conductive region, and wherein the lower surface is supported by a carrier (see col. 17, lines 3-8);
directly bonding a first die comprising integrated circuitry to the interposer element, the first die having a first bonding surface, the first bonding surface comprising a first conductive bond pad and a first non-conductive material, the first conductive bond pad directly bonded to the first conductive pad without an intervening adhesive, and the first non-conductive material directly bonded to a first portion of the non-conductive region (see col. 17, lines 9-17);
directly bonding a second die comprising integrated circuitry to the interposer element, the second die spaced apart from the first die laterally along the upper surface of the interposer element by a gap, the second die electrically connected with the first die through at least the interposer element (see col. 17, lines 18-23);
disposing an insulating material over the upper surface of the interposer element to fill the gap (see col. 17, lines 24-25);
planarizing the insulating material and the first and second dies (see col. 17, lines 26-27);
attaching a support structure over the planarized insulating material and the first and second dies (see col. 17, lines 28-29);
removing the carrier (see col. 17, line 30); and
attaching the second side of the interposer element to a substrate (see col. 17, lines 31-32).
US Patent does not mention the substrate comprising a semiconductor die (see col. 17, lines 31-32).
Lee teaches the same field of an endeavor wherein the substrate (10) comprising a semiconductor die (see fig. 7; see par. 71).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the substrate comprising a semiconductor die as taught by Lee in the teaching of US Patent because if chip 10 is on lower surface of the interposer, the test pad is typically positioned on the lower surface of the interposer. This arrangement allows the test probe to access the bonding interface without needing to penetrate the upper surfaces of silicon. It helps to prevent the test probe from accidentally damaging the delicate circuitry during probing.
Claim 6 of the pending application discloses all the limitations of claim 4 of US Patent.
Claim 7 of the pending application discloses all the limitations of claim 5 of US Patent.
Claim 8 of the pending application discloses all the limitations of claim 6 of US Patent.
Claim 9 of the pending application discloses all the limitations of claim 7 of US Patent.
Claim 10 of the pending application discloses all the limitations of claim 8 of US Patent.
Claim 11 of the pending application discloses all the limitations of claim 9 of US Patent.
Claim 12 of the pending application discloses all the limitations of claim 10 of US Patent.
Claim 13 of the pending application discloses all the limitations of claim 11 of US Patent.
Claim 14 of the pending application discloses all the limitations of claim 12 of US Patent.
Regarding claim 23 of the pending application, US Patent teaches a method of manufacturing a bonded structure (see claim 13’s preamble), the method comprising:
providing a reconstituted wafer comprising (see col. 18, line 5):
a carrier and a routing structure on the carrier, the routing structure comprising a nonconductive material, a plurality of conductive lines in the Filing Date: May 23, 2025 nonconductive material, and a plurality of conductive vias extending at least partially through the nonconductive material (see col. 18, lines 6-10);
a first die hybrid bonded to the routing structure, the first die comprising integrated circuitry (see col. 18, lines 11-12);
a second die hybrid bonded to the routing structure, the second die comprising integrated circuitry, the second die electrically connected with the first die through at least the routing structure (see col. 18, lines 13-16); and
an insulating material over the routing structure and in which the first and second dies are at least partially embedded (see col. 18, lines 17-19);
planarizing the insulating material and the first and second dies (see lines 20-21);
attaching a support structure over the planarized insulating material and the first and second dies (see col. 18, lines 22-23);removing the carrier; and
attaching the routing structure to a substrate (see col. 18, line 25).
Lee teaches the same field of an endeavor wherein the substrate (10) comprising a semiconductor die (see fig. 7; see par. 71).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the substrate comprising a semiconductor die as taught by Lee in the teaching of US Patent because if chip 10 is on lower surface of the interposer, the test pad is typically positioned on the lower surface of the interposer. This arrangement allows the test probe to access the bonding interface without needing to penetrate the upper surfaces of silicon. It helps to prevent the test probe from accidentally damaging the delicate circuitry during probing.
Claim 24 of the pending application discloses all the limitations of claim 16 of US Patent.
Claims 15 and 17-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3-10 of U.S. Patent No. 12,322,718. Although the claims at issue are not identical, they are not patentably distinct from each other for the following reasons:
Regarding claim 15 of the pending application, US Patent teaches a method of manufacturing a bonded structure (see claim 3’s preamble), the method comprising:
providing an interposer element having an upper surface at a first side and a lower surface at a second side, wherein the upper surface comprises a first conductive pad, a second conductive pad, and a non-conductive region, and wherein the lower surface is supported by a carrier (see col. 17, lines 3-8);
directly bonding a first die comprising integrated circuitry to the interposer element, the first die having a first bonding surface, the first bonding surface comprising a first conductive bond pad and a first non-conductive material, the first conductive bond pad directly bonded to the first conductive pad without an intervening adhesive, and the first non-conductive material directly bonded to a first portion of the non-conductive region (see col. 17, lines 9-17);
directly bonding a second die comprising integrated circuitry to the interposer element, the second die spaced apart from the first die laterally along the upper surface of the interposer element by a gap (see col. 17, lines 18-20);
providing a conformal dielectric coating over top surfaces of the first and second dies and over the upper surface of the interposer element (refer to the conformal first layer of the insulating layer in claim 5);
disposing an encapsulant over the conformal dielectric coating to fill the gap (See col. 17, lines 24-25);
removing portions of at least the conformal dielectric coating and the encapsulant to planarize the conformal dielectric material, the encapsulant, and the first and second dies (see col. 17, lines 26-27);
attaching a support structure over the planarized conformal dielectric material, the encapsulant, and the first and second dies (see col. 17, lines 28-29);
removing the carrier (see col. 17, line 30); and
attaching the second side of the interposer element to a substrate (see col. 17, lines 31-32).
Claim 17 of the pending application discloses all the limitations of claim 4 of US Patent.
Claim 18 of the pending application discloses all the limitations of claim 7 of US Patent.
Claim 19 of the pending application discloses all the limitations of claim 8 of US Patent.
Claim 20 of the pending application discloses all the limitations of claim 9 of US Patent.
Claim 21 of the pending application discloses all the limitations of claim 10 of US Patent.
Claim 22 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 5 of U.S. Patent No. 12,322,718 in view of Lee (US 2020/0135594).
Regarding claim 22 of the pending application, US Patent’s claim 3 teaches all the limitations for the same reasons as set forth above (See claim 15’s rejection) except for the substrate comprises a semiconductor die.
Lee teaches the same field of an endeavor wherein the substrate (10) comprising a semiconductor die (see fig. 7; see par. 71).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include the substrate comprising a semiconductor die as taught by Lee in the teaching of US Patent because if chip 10 is on lower surface of the interposer, the test pad is typically positioned on the lower surface of the interposer. This arrangement allows the test probe to access the bonding interface without needing to penetrate the upper surfaces of silicon. It helps to prevent the test probe from accidentally damaging the delicate circuitry during probing.
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 3 and 5 of U.S. Patent No. 12,322,718 in view of Gu (US 20150235991).
Regarding claim 16 of the pending application, US patent teaches all the limitations of the claimed invention for the same reasons as set forth above except for performing only one planarization step to the first and second dies, the only one planarization step causing top surfaces of the first and second dies to be flush with insulating material, wherein performing the only one planarization step comprises removing the portions of at least the conformal dielectric coating and the encapsulant.
Gu teaches the same field of an endeavor wherein performing only one planarization step to the first and second dies, the only one planarization step causing top surfaces of the first and second dies to be flush with insulating material, wherein performing the only one planarization step comprises removing the portions of at least the conformal dielectric coating and the encapsulant (See par. 43 and fig. 2H).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include performing only one planarization step to the first and second dies, the only one planarization step causing top surfaces of the first and second dies to be flush with insulating material, wherein performing the only one planarization step comprises removing the portions of at least the conformal dielectric coating and the encapsulant as taught by Gu in the teaching of US Patent by grinding away the encapsulant to fully exposed the backside of the die to form a RDL directly onto this ground surface for a fan-out wafer-level package (see par. 33).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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