Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 27 May 2025 for application number 19/218,935. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 20 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 30 December 2021 (KR10-2021-0192183).
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 27 May 2025 were filed on the mailing date of the application. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 9 – 15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 recites in the second limitation, “wherein a first transaction region among the plurality of transaction regions comprises…” There is a lack of antecedent basis in the claim. A plurality of transaction regions has not previously been established in claims 1 or 9. Claims 10 – 15 depend from claim 9, and are rejected based upon their dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Norrie et al. [hereafter as Norrie], US Pub. No. 2022/0156071 A1 in view of Doshi et al. [hereafter as Doshi], US Pub. No. 2019/0004851 A1.
As per claim 1, Norrie discloses a neural processing device [“Regarding its physical structure, the resources of shared memory 104 may be physically distributed on a special-purpose or neural net processor chip corresponding to hardware circuit 101.”] [para. 0050] [“The hardware circuit can be a special-purpose processor, such as a neural network processor,”] [para. 0031] comprising:
a plurality of neural cores including a first neural core and a second neural core [“an integrated circuit for a hardware machine-learning accelerator that includes a plurality of cores and a shared memory that communicates with each of the plurality of cores”] [claim 2] [para. 0037] [“The hardware circuit can be a special-purpose processor, such as a neural network processor,”] [para. 0031];
a shared memory shared by the plurality of neural cores [“an integrated circuit for a hardware machine-learning accelerator that includes a plurality of cores and a shared memory that communicates with each of the plurality of cores”] [claim 2] [para. 0037] [“The hardware circuit can be a special-purpose processor, such as a neural network processor,”] [para. 0031]; and
a first memory [“The system 100, including the circuit 101, includes a system memory 102 and a shared memory 104. The system memory 102 can represent a high-bandwidth memory (“HBM 102”) or an input/output (I/O) device that exchanges data communications with a processor core 105-1, 105-2, of the hardware circuit 101.”] [para. 0037],
wherein each of the plurality of neural cores is configured to transmit a first memory access request to the first [“The system memory 102 can represent a high-bandwidth memory (“HBM 102”) or an input/output (I/O) device that exchanges data communications with a processor core 105-1, 105-2, of the hardware circuit 101.”] [para. 0037], and
wherein is configured to:
receive a plurality of first memory access requests from the plurality of neural cores [“the control unit 201 tracks the operations based on the accumulate flag 330, 335 that accompanies a write request from a processor core.”] [para. 0096]; and
track a read operation or a write operation corresponding to the plurality of first memory access requests [“With respect to tracking outstanding operations, the control unit 201 is configured to execute an operations tracker 440 to keep track of outstanding requests and current (or queued) operations for accumulating different vectors of values in the shared memory system. For example, the control unit 201 uses the operations tracker 440 to track each write operation”] [para. 0096].
However, Norrie does not explicitly disclose a first programmable hardware transactional memory (PHTM),
request to the first PHTM, and
the first PHTM.
Doshi teaches a first programmable hardware transactional memory (PHTM) [“Thus, for example, any of the example components of the transaction execution manager 201 for transaction execution atomicity in NVM under hardware transactional memory and/or, more generally, the transaction execution manager 201 for transaction execution atomicity in NVM under hardware transactional memory could be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)) and/or field programmable logic device(s) (FPLD(s)).”] [para. 0081],
the first PHTM [“Thus, for example, any of the example components of the transaction execution manager 201 for transaction execution atomicity in NVM under hardware transactional memory and/or, more generally, the transaction execution manager 201 for transaction execution atomicity in NVM under hardware transactional memory could be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)) and/or field programmable logic device(s) (FPLD(s)).”] [para. 0081], and
the first PHTM [“Thus, for example, any of the example components of the transaction execution manager 201 for transaction execution atomicity in NVM under hardware transactional memory and/or, more generally, the transaction execution manager 201 for transaction execution atomicity in NVM under hardware transactional memory could be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)) and/or field programmable logic device(s) (FPLD(s)).”] [para. 0081].
As per claim 3, Norrie in view of Doshi discloses the neural processing device of claim 1, Norrie discloses wherein the plurality of first memory access requests comprises:
a read request, being a request to read data from the shared memory [“the control unit 201 generates control signals for managing operations to retrieve (or read) multiple batches of inputs and sets of weights from memory locations of shared memory 104,”] [para. 0078]; or
a plurality of write requests, being requests to write data onto the shared memory [“For example, the control unit 201 uses the operations tracker 440 to track each write operation that requests to write a vector of values to a memory location of shared memory”] [para. 0096].
As per claim 4, Norrie in view of Doshi discloses the neural processing device of claim 1, Norrie discloses wherein the plurality of neural cores are further configured to perform the read operation or the write operation [“For example, the control unit 201 uses the operations tracker 440 to track each write operation that requests to write a vector of values to a memory location of shared memory”] [para. 0096] without a transmission and reception operation of a synchronization signal among the plurality of neural cores [“The atomic reductions are processed as accumulate or vector reduction steps where vectors of values are accumulated directly into a memory location of the shared memory without the need to synchronize activity between the cores”] [para. 0033].
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 20 have received a first action on the merits and are subject of a first action non-final. Claims 9 – 15 are rejected under a 112 rejection. Claim 1, 3, and 4 are rejected under a 103 rejection.
Allowable Subject Matter
Claims 2, 5, 9, and 16 are objected to as being dependent upon a rejected based claim, but are considered as containing allowable subject matter. These claims would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims in independent form. Claims 6 – 8, 10 – 15, and 17 – 20 depend from claims 5, 9, and 16 and are objected to as considered containing allowable subject matter based upon their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 2 the prior art of record, neither anticipates, nor renders obvious where the first PHTM receives a preset criteria that to perform committing or buffering of the first memory access requests based on the preset criteria, where the preset criteria includes a group number that is associated with the first memory access requests, a memory access type of the first memory access requests, a service order for the first memory access requests, a write number associated with the first memory access requests, or a read number associated with the first memory access requests.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 5 the prior art of record, neither anticipates, nor renders obvious where the first PHTM has multiple transaction regions that are configured to track read or write operations. Claims 6 – 8 depend from claim 5 and would be allowable based upon their dependency.
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 9 the prior art of record, neither anticipates, nor renders obvious a first and second group of neural cores, where a first transaction region out of many transaction regions is comprised of a first group area configured to receive first memory access requests from the first group of neural cores and a second group area that also receives from the first memory access requests, memory access requests of the second group of neural cores. Claims 10 – 15 depend from claim 9 and would be allowable based upon their dependency
The following is a statement of reasons for the indication of allowable subject matter: for dependent claim 16 the prior art of record, neither anticipates, nor renders obvious a first group of neural cores that include the first neural core and the second neural core, and a second group of neural cores that includes a third neural core and a fourth neural core, where the neural processing device includes a second and third PHTM that respectively receives second memory access requests from the first group of neural cores, and third memory access requests from the second group of neural cores. Claims 17 – 20 depend from claim 16 and would be allowable based upon their dependency
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Suzuki et al., US Pub. No. 2013/0097389 A1 – teaches “A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores not having made an exclusive access request to the shared memory, multiple cores capable of accessing the shared memory; detect a core having completed the exclusive access among the first group of cores; and send to a core among the first group of cores and standing by for the exclusive access, a notification of release from a standby state, when detecting a core having completed the exclusive access.” [Abstract]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD WADDY JR whose telephone number is (571)272-5156. The examiner can normally be reached M-Th 8am-5pm.
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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