DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 05/27/2025. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Continuity Priority information
The present Application 19219935 filed 05/27/2025 Claims Priority from Provisional Application 63652295, filed 05/28/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/25/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 15, 2, 3, 7, 16, 17, the limitations “designating a first block stripe of the plurality of block stripes as a single-level cell (SLC) block stripe that are associated with the error condition; and designating a second block stripe of the plurality of block stripes as a quad-level cell (QLC) block stripe that are associated with the error condition” are indefinite. It is unclear how one is able to distinguish between a (SLC) block stripe and a quad-level cell (QLC) block stripe based on an error condition occurred in a memory device. Normally, one identifies the memory type prior to error detection. There is no sufficient information in the specification for identifying the memory type, SLC or QLC, based on the error condition.
Claim 8 recites similar limitations “designating a first block stripe of the plurality of block stripes as a block stripe with memory having a first number of bits per cell” and “designating a second block stripe of the plurality of block stripes as a block stripe with memory having a second number of bits per cell”, which render the claims indefinite for the same reasons as the claims above.
Any Claims not specifically mentioned above are rejected due to their dependency on a rejected claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ioannou et al. (US 20190171381) Pub. Date: 2019-06-06.
Regarding independent Claims 1, 8 and 15, Ioannou discloses a system and method for reducing unnecessary calibration for a unit of memory for which an error count margin has been exceeded, comprising:
a processing device, coupled with the memory device, configured to perform operations; [0017] FIG. 1A, illustrates a data processing environment 100 including a data storage system 120 having a non-volatile memory array, and a processor system 102 having one or more processors 104 that process instructions and data. A processor system 102 may additionally include local storage 106 (e.g., dynamic random access memory (DRAM) or disks) that may store program code, operands and/or execution results of the processing performed by processor(s) 104.
identifying, for a plurality of block stripes, respective quantities of blocks that are associated with an error condition, wherein each block stripe of the plurality of block stripes spans the plurality of dies of the memory device;
[0032] Once all pages in a block stripe have been written, flash controller 140 places the block stripe into one of occupied block queues 302, which flash management code running on the GPP 132 utilizes to facilitate garbage collection. [0034] As further shown in FIG. 3, background health checker 330, which operates independently of the read and write operations of hosts such as processor systems 102, continuously determines one or more block health metrics 332 for blocks belonging to block stripes recorded in occupied block queues 302. Key block health metrics 332 preferably monitored and recorded by background health checker 330 relate to the bit error rate (BER) “error condition” metrics observed for valid blocks and physical pages, and may include, for example, the worst page BER “error condition” of each block, the mean page BER of each block, the rates of change of the worst page BER and mean page BER of each block, etc.
designating a first block stripe of the plurality of block stripes as a single-level cell (SLC) block stripe that are associated with the error condition; and designating a second block stripe of the plurality of block stripes as a quad-level cell (QLC) block stripe that are associated with the error condition.
[0002] Memories storing one, two, three and four bits per cell are respectively referred to in the art as Single Level Cell (SLC), Multi-Level Cell (MLC), Three Level Cell (TLC), and Quad Level Cell (QLC) memories. In a typical implementation, a NAND flash memory array includes multiple physical die, which can each include multiple planes. [0003] In multi-level (i.e., MLC, TLC and QLC) NAND flash memory, information is stored by programming the memory cells to various quantized threshold voltage levels according to the device's programming algorithm, which maps the binary bit values to discrete threshold voltage levels. [0024] As shown in FIG. 1B, the flash memory storage devices 152 take the form of a board-mounted flash memory modules, for example, Multi-Level Cell (MLC), Three Level Cell (TLC), or Quad Level Cell (QLC) 3D NAND flash memory modules. The effective storage capacity provided by flash memory storage devices 152 can be increased through the implementation of data compression, for example, by flash controllers 140 and/or high level controllers, such as GPPs 132, RAID controllers 124 or SMCs 123.
Regarding Claims 2, 3, 7, 9, 16, 17, Ioannou discloses as the SLC block stripe comprises designating a first quantity of block stripes and as the QLC block stripe comprises designating a second quantity of block stripes; [0030] A build block stripes function 320 performed by flash management code running on the GPP 132 constructs new block stripes for storing data and associated parity information from the erased blocks enqueued in RTU queues 306. The new block stripes are then queued to the flash controller 140 for data placement. Block stripes are preferably formed of blocks residing in different channels, meaning that build block stripes function 320 can conveniently construct a block stripe by drawing each block of the new block stripe from a different RTU queue 306.
Regarding Claims 4, 5, 12, 18, 19, Ioannou discloses the respective quantities of blocks that are associated with the error condition; Background health checker 330, which operates independently of the read and write operations of hosts such as processor systems 102, continuously determines one or more block health metrics 332 for blocks belonging to block stripes recorded in occupied block queues 302. Based on the one or more of the block health metrics 332, background health checker 330 places block stripes on relocation queue 304 for handling by relocation function 314. Key block health metrics 332 preferably monitored and recorded by background health checker 330 relate to the bit error rate (BER) metrics observed for valid blocks and physical pages, and may include, for example, the worst page BER of each block, the mean page BER of each block, the rates of change of the worst page BER and mean page BER of each block.
Regarding Claims 6, 13, 20, Ioannou discloses plurality of block stripes that are associated with the error condition to a highest quantity of blocks that are associated with the error condition. [0033] The flash management functions performed by GPP 132 or flash controller 140 additionally include a relocation function 314 that relocates the data held in block stripes enqueued in relocation queue 304. To relocate such data, relocation function 314 updates LPT table 300 to remove the current association between the logical and physical addresses of the data. In addition, relocation function 314 issues relocation write requests to data placement function 310 to request that the valid data of the old block stripe be written to a new block stripe in NAND flash memory system 150.
Regarding Claims 10, 11, 14, Ioannou discloses wherein designating the first block stripe comprises designating a first quantity of block stripes, and wherein designating the second block stripe comprises designating a second quantity of block stripes of the plurality of block stripes as block stripes with memory having the second number of bits per cell. [0037] The process of FIG. 4 begins at block 400 and then proceeds to block 402, which depicts background health checker 330 selecting a first or next block stripe for processing from occupied block queue 302. In general, any block stripe may be chosen, and the selection may be based on one or more criteria, such as elapsed time since last background health check, an elapsed time since last programming, elapsed time since last read access, ordering in a management queue, etc. At block 404, background health checker 330 additionally selects a desired set of the blocks for processing in the selected block stripe.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: September 29, 2026
Non-Final Rejection 20260929
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
