Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: DISPLAY PANEL WITH PLURALITY OF DISPLAY AREAS WITH FIRST PIXEL UNITS IN A FIRST ACTIVE AREA AND CONNECTED TO FIRST PIXEL CIRCUITS IN A SECOND ACTIVE AREA
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first pixel unit" in line 4 of the claim (but has introduced “a plurality of first pixel units”). There is insufficient antecedent basis for this limitation in the claim, since it is not clear which of the plurality is being referred to by "the first pixel unit".
By virtue of their dependency, claims 2-20 are also rejected.
Claim 1 recites the limitation "the sub-pixel" in line 5 of the claim (but has introduced “a plurality of sub-pixels”). There is insufficient antecedent basis for this limitation in the claim, since it is not clear which of the plurality is being referred to by “the sub-pixel”.
Claim 1 recites the limitation "the first pixel circuit" in line 7 of the claim (but has introduced “a plurality of first pixel circuits”). There is insufficient antecedent basis for this limitation in the claim, since it is not clear which of the plurality is being referred to by "the first pixel circuit".
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-16 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ge et al., US 2023/0410736 A1 (hereinafter “Ge”).
Ge discloses 1, Ge discloses a display panel (FIGS. 1 and 6, display panel 100 at [0023]-[0026] and [0089]-[0092]) which has a first active area (FIGS. 1 and 6, first display area AA1 at [0021]-[0026] and [0091]-[0094]) and a second active area (FIGS. 1 and 6, second display area AA2 at [0021]-[0026] and [0091]-[0094]), wherein a light transmittance of the first active area is greater than a light transmittance of the second active area (FIGS. 1 and 6 and [0021]-[0022] and [0091]), the display panel comprising:
a plurality of first pixel units (110s) located in the first active area (FIGS. 2-5 and sub pixel units 110 at [0026]-[0028] and [0075]-[0085]), the first pixel unit (110) comprising a plurality of sub-pixels (FIGS. 2-5 and sub pixel units 110 made up of subpixels 111 at [0026]-[0028] and [0075]-[0085]), wherein the sub-pixel (111) comprises a first electrode (FIGS. 2-5 and first electrode at [0028]-[0030] and [0072]-[0075] and [0086]-[0088]) and a second electrode opposite the first electrode (FIGS. 2-5 and second electrode at [0028]-[0030] and [0072]-[0075] and [0086]-[0088], second electrode and first electrode have a light emitting structure between rending them opposite of each other in relation to the light emitting structure [0028]); and
a plurality of first pixel circuits(120) located in the second active area (FIGS. 2-5 and pixel driving units 120 at [0026] and [0031]-[0033] and [0036]-[0038] and [0041]-[0042] arranged in AA2), the first pixel circuit (121) being connected to the first electrode of the corresponding sub-pixel (111) in the first pixel unit (110) through a wire (FIGS. 2-5 wire as shown between driving unit 120 made of multiple pixel driving units 121 connecting to first sub-pixels 111 of the pixel unit 110, connection between pixel driving circuit and first electrode at [0029]), wherein the plurality of first pixel circuits are arranged in an array (FIGS. 2-5 pixel driving units 121 are arranged in various arrays of 1x4 and 2x2 and at [0080]), and the first pixel circuits (121) corresponding to the plurality of sub-pixels (111) in a same first pixel unit are arranged in at least two rows (FIG. 4, 121 arranged in two rows) and in a number of columns less than a total number of sub-pixels in the first pixel unit (FIG. 4, 121 arranged in two columns, which is less than the total number of sub pixels 111 which is 4).
Regarding claim 2, Ge discloses the display panel according to claim 1 (see above), wherein the first pixel unit comprises m sub-pixels of the same color (FIGS. 2-5 and [0027]-[0029] sub-pixels 111 of the same color make up the sub-pixel unit 121), and the m sub-pixels of the same color in the same first pixel unit are driven by n first pixel circuits (FIGS. 2-5 numerous pixel driving circuits 121 of the driving unit 120 driving the corresponding same color sub-pixels at [0029]), wherein n and m are both positive integers greater than or equal to 1 (FIGS. 2-5 and both are greater than 1 pixel driving and sub-pixel), and n≤m (FIGS. 2-5 number of sub-pixels 111 equal to, or less than, or more than driving circuits 121 at [0040]).
Regarding claim 3, Ge discloses the display panel according to claim 2 (see above), wherein for n=m=1 (FIGS. 2-5 and both can be 1 pixel driving and sub-pixel), each first pixel circuit is connected to one corresponding sub-pixel through the wire; for n=1 and m>1 (FIGS. 2-5 and [0040]), the first electrodes of the m sub-pixels of the same color in the same first pixel unit are electrically connected to each other (FIGS. 2-5 all sub-pixels 111 of the same color connected at [0031] and [0034]-[0038]), and are electrically connected to the corresponding first pixel circuit through a same wire (FIGS. 2-5 and [0040] and [0031] and [0034]-[0038] same color subpixels 111 would be connected to the same first pixel circuit 121, e.g., FIG. 3 arrangement same wire to connect all); and for n>1 and m>1, n first pixel circuits corresponding to the m sub-pixels of the same color in the same first pixel unit are electrically connected to each other (FIGS. 2-5 and [0029] and [0031]-[0037] same color and connected to each other), and the first electrodes of the m sub-pixels of the same color are electrically connected to each other (FIGS. 2-5 and [0029] and [0031]-[0037] same color subpixels 111 are electrically connected to each other), and are electrically connected to any first pixel circuit among the n corresponding first pixel circuits through a same wire (FIGS. 2-5 and [0029] and [0031]-[0037] same color subpixels 111 are electrically connected to each and to the pixel circuits through one wire, e.g., FIG. 2).
Regarding claim 4, Ge discloses the display panel according to claim 3 (see above), wherein for n>1 and m>1 (FIGS. 2-5 and both are greater than 1 pixel driving circuit and sub-pixel), the m sub-pixels of the same color in the same first pixel unit are connected to the closest first pixel circuit among the n corresponding first pixel circuits through the wire (FIGS. 2-3 the 121 row arranged in a row closest to 111 row and [0029]).
Regarding claim 5, Ge discloses the display panel according to claim 1 (see above), wherein at least part of the plurality of sub-pixels in the first pixel unit have different colors, and there is at least one sub-pixel of each color (FIGS. 2-5 color can be different at [0037]-[0038] and [0075]); and the first pixel circuits corresponding to the sub-pixels of the same color in the same first pixel unit are arranged in a same row (FIGS. 2-5 and [0029] and [0031]-[0037] same color and connected row of pixel circuits at FIG. 2, for example, and [0055]); or the first pixel circuits corresponding to the sub-pixels of the same color in the same first pixel unit are arranged in a same column (FIGS. 2-5 and [0029] and [0031]-[0037] same color and connected to pixel circuits at FIG. 2, for example, and [0055] and [0059]-[0062] for same column); or the first pixel circuits corresponding to the sub-pixels of the same color in the same first pixel unit are arranged in at least one of different rows and different columns (FIGS. 2-5 and [0029] and [0031]-[0037] same color and connected to pixel circuits at FIG. 2, for example, and [0055] and [0064] for different row).
Regarding claim 6, Ge discloses the display panel according to claim 1 (see above), wherein the plurality of sub-pixels of the first pixel unit comprises a plurality of first sub-pixels, a plurality of second sub-pixels, and a plurality of third sub-pixels, the first sub-pixels, the second sub-pixels, and the third sub-pixels having different colors (FIGS. 2-5 and [0037]-[0038] and [0075] describing different color sub-pixels 111 and hatch patterns being different to indicate the color differences), and the same first pixel unit comprises two first sub-pixels and two third sub-pixels, as well as four second sub-pixels (FIGS. 1-5 and when viewing entirety of section illustrated of first display area AA1, pixels of three different colors arranged with two of the first color, two of the third and 4 of the second at least FIGS. 2-5 and [0037]-[0038] and [0075]-[0079); the first sub-pixels, the second sub-pixels, and the third sub-pixels are arranged in an array in the first pixel unit (arrays as arranged at FIGS. 2-5 in generally), a first sub-pixel of the first sub-pixels, a second sub-pixel of the second sub-pixels, a third sub-pixel of the third sub-pixels, and a second sub-pixel of the second sub-pixels being sequentially arranged in a first row of the first pixel unit, and a third sub-pixel of the third sub-pixels, a second sub-pixel of the second sub-pixels, a first sub-pixel of the first sub-pixels, and a second sub-pixel of the second sub-pixels being sequentially arranged in a second row of the first pixel unit (FIGS. 2-5 generally, rows created in a vertical or horizontal or diagonal direction and at [0029]-[0038] and [0055] and [0062]-[0064]); and the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel (FIGS. 2-5 and [0075] and [0027] and [0037]-[0038] describing color in any combination needed)
Regarding claim 9, Ge discloses the display panel according to claim 1 (see above), wherein the first pixel circuits corresponding to the plurality of sub-pixels in a same first pixel unit are arranged in at least two adjacent rows (FIG. 4, 121 arranged in two adjacent rows for pixels 111 of two row).
Regarding claim 10, Ge discloses the display panel according to claim 1 (see above), wherein the first active area comprises at least one row of first pixel units (FIG. 3, 110 in a first top row made up of 111), and the first pixel circuits (121) corresponding to the sub-pixels (111) in the same row of first pixel units occupy the same row (FIG. 3, top row of 111 corresponding with same row of 121).
Regarding claim 11, Ge discloses the display panel according to claim 10 (see above), wherein the first pixel circuits corresponding to the sub-pixels in the same row of first pixel units are distributed on two sides of the row of first pixel units (FIG. 3, top row of 120 is two sides of the same row distribution).
Regarding claim 12, Ge discloses the display panel according to claim 1 (see above), wherein the wire is a transparent metal wire ([0066]-[0076]); and a material of the wire comprises at least one of indium tin oxide and indium zinc oxide ([0068]).
Regarding claim 13, Ge discloses the display panel according to claim 1 (see above), further comprising a plurality of scan lines (FIGS. 2-5 and scan signal lines 130 and [0050]-[0051], wherein the first pixel circuits for driving the sub-pixels in the same row of first pixel units are connected to a same scan line (FIGS. 2-5 and [0062]-[0065], FIG. 4 generally illustrating).
Regarding claim 14, Ge discloses the display panel according to claim 13 (see above), wherein the scan line connected to the first pixel circuits is located outside the first active area (FIGS. 2-4 illustrating connection of 130 outside of the first active area as depicted by section 110 and [0050]-[0052]); or the scan line connected to the first pixel circuits passes through the first active area, and at least part of the scan line located in the first active area is a transparent metal wire (see above, condition satisfied, FIGS. 2-5 where the connection when connecting in first active area is transparent at [0066]-[0069] and [0073]-[0075]).
Regarding claim 15, Ge discloses the display panel according to claim 1 (see above), further comprising a plurality of second pixel units and a plurality of second pixel circuits (FIGS. 1-2 and [0043]), wherein the second pixel units and the second pixel circuits are both located in the second active area (FIGS. 1-2 and [0043]), the second pixel unit comprising a plurality of sub-pixels, and the second pixel circuits being configured to drive the corresponding sub-pixels in the second pixel unit (commonly known in view of FIGS. 1-2, 6-7 and [0043] in view of commonly known OLED manufacturing practices at [0019] and [0072]).
Regarding claim 16, Ge discloses the display panel according to claim 15 (see above), wherein the display panel meets at least one of the following: at least a portion of the first pixel circuits being located between adjacent second pixel circuits (see below, condition satisfied); and at least a portion of the first pixel circuits and at least a portion of the second pixel circuits being arranged in different areas in the second active area (FIGS. 1-2, 6-7 and [0043] in view of known commonly known practices in manufacturing of OLED pixel circuit known in the art that pixel circuits of a display panel are located in a matrix, circuits of which are on the panel second area and [0019] and [0072]).
Regarding claim 20, Ge discloses a display apparatus (FIGS. 1, 6-7 and 100 and [0022]-[0026] and [0029]), comprising a display panel (FIGS. 6-7 and display panel 10 and [0089]-[0090] and [0092]) according to claim 1 (see above).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ge et al., US 2023/0410736 A1 (hereinafter “Ge”).
Regarding claim 7, Ge discloses the display panel according to claim 6 (see above), wherein the first pixel circuit comprises a plurality of first sub-pixel circuits, a plurality of second sub-pixel circuits, and a plurality of third sub-pixel circuits, the two first sub-pixels in the same first pixel unit being driven by two first sub-pixel circuits (Ge at FIGS. 2-5 with the pixel circuits 121 could also be seen as sub-pixel circuits of a larger pixel circuit 120 and being used to drive each grouping of subpixels 111 110 as discussed at [0027]-[0033] and [0037]-[0039]),
the two third sub-pixels in the same first pixel unit being driven by two third sub-pixel circuits (Ge at FIGS. 2-5 with the pixel circuits 121 could also be seen as sub-pixel circuits of a larger pixel circuit 120 and being used to drive each grouping of subpixels 111 110 as discussed at [0027]-[0033] and [0037]-[0039]), and the four second sub-pixels in the same first pixel unit being driven by four second sub-pixel circuits (Ge at FIGS. 2-5 with the pixel circuits 121 could also be seen as sub-pixel circuits of a larger pixel circuit 120 and being used to drive each grouping of subpixels 111 110 as discussed at [0027]-[0033] and [0037]-[0039]); and
in the first pixel circuits corresponding to the same first pixel unit: two first sub-pixel circuits are arranged in a column (Ge at columns of FIGS. 3-4 and [0055]-[0062]), two third sub-pixel circuits are arranged in a column (Ge at columns of FIGS. 3-4 and [0055]-[0062]), four second sub-pixel circuits are arranged in two columns (Ge at columns of FIGS. 3-4 and [0055]-[0062]), and the two first sub-pixel circuits, the four second sub-pixel circuits, and the two third sub-pixel circuits are arranged in at least two rows (FIGS. 2-5 with rows as illustrated and in view of [0055]-[0062] any combination of rows and columns is known in the art); and the column of the two first sub-pixel circuits, the two columns of the four second sub-pixel circuits, and the column of the two third sub-pixel circuits are sequentially arranged on one side of the corresponding first pixel unit (FIGS. 2-5 with rows as illustrated and in view of [0055]-[0062] any combination of rows and columns is known in the art, and clearly on one side of the pixel unit in general).
Although Ge does not expressly disclose the exact layout, Ge clearly contemplates and suggests any number of arrangements of sub-pixel circuits and pixels in accordance with the particular needs, specific design and use cases/purposes known in the art ([0018] and colors at [0027]-[0030] and connections [0033]-[0037] and [0040], [0055] and [0063]-[0064]). Before the effective filing date, it would be obvious to one of ordinary skill in the art to produce the claimed arrangement given the commonly understood desirable outcomes (e.g., simplified routing, manufacturing tolerances, layout efficiencies) and the claimed arrangement would amount to nothing more than minor differences that would be the result of obvious design choice and/or routine optimization performed by one of ordinary skill.
Regarding claim 8, Ge discloses the display panel according to claim 6 (see above),
wherein the first pixel circuit comprises a plurality of first sub-pixel circuits, a plurality of second sub-pixel circuits, and a plurality of third sub-pixel circuits, the two first sub-pixels in the same first pixel unit being driven by two first sub-pixel circuits (Ge at FIGS. 2-5 with the pixel circuits 121 could also be seen as sub-pixel circuits of a larger pixel circuit 120 and being used to drive each grouping of subpixels 111 110 as discussed at [0027]-[0033] and [0037]-[0039]), the two third sub-pixels in the same first pixel unit being driven by two third sub-pixel circuits (Ge at FIGS. 2-5 with the pixel circuits 121 could also be seen as sub-pixel circuits of a larger pixel circuit 120 and being used to drive each grouping of subpixels 111 110 as discussed at [0027]-[0033] and [0037]-[0039]), and the four second sub-pixels in the same first pixel unit being driven by four second sub-pixel circuits (Ge at FIGS. 2-5 with the pixel circuits 121 could also be seen as sub-pixel circuits of a larger pixel circuit 120 and being used to drive each grouping of subpixels 111 110 as discussed at [0027]-[0033] and [0037]-[0039]); and
in the first pixel circuits corresponding to the same first pixel unit: one of the two first sub-pixel circuits and one of the two third sub-pixel circuits are arranged in a column (Ge at columns of FIGS. 3-4 and [0055]-[0062]), another one of the two first sub-pixel circuits and another one of the two third sub-pixel circuits are arranged in a column (Ge at columns of FIGS. 3-4 and [0055]-[0062]), four second sub-pixel circuits are arranged in two columns (Ge at columns of FIGS. 3-4 and [0055]-[0062]), and the two first sub-pixel circuits, the four second sub-pixel circuits, and the two third sub-pixel circuits are arranged in at least two rows (FIGS. 2-5 with rows as illustrated and in view of [0055]-[0062] any combination of rows and columns is known in the art); and the column of the one of the two first sub-pixel circuits and the one of the two third sub-pixel circuits, the column of the another one of the two first sub-pixel circuits and the another one of the two third sub-pixel circuits, and the two columns of the four second sub-pixel circuits are sequentially arranged on one side of the corresponding first pixel unit (FIGS. 2-5 with rows as illustrated and in view of [0055]-[0062] any combination of rows and columns is known in the art, and clearly on one side of the pixel unit in general)..
Although Ge does not expressly disclose the exact layout, Ge clearly contemplates and suggests any number of arrangements of sub-pixel circuits and pixels in accordance with the particular needs, specific design and use cases/purposes known in the art ([0018] and colors at [0027]-[0030] and connections [0033]-[0037] and [0040], [0055] and [0063]-[0064]). Before the effective filing date, it would be obvious to one of ordinary skill in the art to produce the claimed arrangement given the commonly understood desirable outcomes (e.g., simplified routing, manufacturing tolerances, layout efficiencies) and the claimed arrangement would amount to nothing more than minor differences that would be the result of obvious design choice and/or routine optimization performed by one of ordinary skill.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ge in view of Yang et al., US 2022/0069047 A1 (hereinafter “Yang”).
Regarding claim 17, Ge discloses the display panel according to claim 16 (see above).
However, Ge does not explicitly disclose wherein each first pixel circuit is located between adjacent second pixel circuits; and the display panel further comprises a plurality of dummy pixel circuits located between adjacent second pixel circuits, and at least part of the dummy pixel circuits are reused as the first pixel circuits.
In the same field of endeavor, Yang discloses wherein each first pixel circuit is located between adjacent second pixel circuits (FIGS. 16-19 pixels circuits C1 to drive pixels L1 in DA1 are located in SD1/DA2 and adjacent to pixel circuits C2 in SD1/DA2 and [0127]-[0134]); and the display panel further comprises a plurality of dummy pixel circuits located between adjacent second pixel circuits, and at least part of the dummy pixel circuits are reused as the first pixel circuits (FIGS. 18-19 and [0134]-[0135] and DC circuits are dummy circuits used for driving the first pixels along with C1).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display device and pixel arrangement of Ge to incorporate the dummy circuits and placement of other pixel circuits as disclosed by Yang because the references are within the same field of endeavor, namely, display panels with multiple display areas with modified pixelation and driving based on display area. The motivation to combine these references would have been to improve manufacturing of the device by shifting uneven exposure during the etching process to the dummy circuits (see Yang at least at [0128]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Regarding claim 18, Ge in view of Yang discloses the display panel according to claim 16 (see above).
However, Ge does not explicitly disclose wherein the first active area, comprises a first active sub-area and a second active sub-area, and the second active area comprises a third active sub-area and a fourth active sub-area, the third active sub-area being adjacent to the first active sub-area, and the fourth active sub-area being adjacent to the second active sub-area; the first pixel circuit corresponding to the sub-pixel in the first active sub-area is located in the third active sub-area, and the first pixel circuit corresponding to the sub-pixel in the second active sub-area is located in the fourth active sub-area; and the first pixel circuit and the second pixel circuit are arranged in different areas in the third active sub-area, and the first pixel circuit in the fourth active sub-area is located between adjacent second pixel circuits.
In the same field of endeavor, Yang discloses wherein the first active area (Yang at FIG. 3 with DA1), comprises a first active sub-area (Yang at FIG. 3, DA1 and LA) and a second active sub-area (Yang at FIG. 3 and DA1 and WA), and the second active area (Yang at FIG. 3 and DA3 and DA2) comprises a third active sub-area (Yang at FIG. 3 and SD1/SD3) and a fourth active sub-area (Yang at FIGS. 3 and 5 and SD1 and SD3 and SD4), the third active sub-area being adjacent to the first active sub-area (Yang at FIGS. 3 and 5 and with SD1/SD3 adjacent to LA/WA), and the fourth active sub-area being adjacent to the second active sub-area (Yang at FIGS. 3 and 5 and with SD1/SD3 adjacent to LA/WA); the first pixel circuit corresponding to the sub-pixel in the first active sub-area is located in the third active sub-area (Yang FIGS. 2-10 with placement of pixels circuits of the first active area LA or WA and connection thereof in various areas including DA3), and the first pixel circuit corresponding to the sub-pixel in the second active sub-area is located in the fourth active sub-area (Yang FIGS. 2-10 with placement of pixel circuits of the first active area LA or WA and connection thereof in various areas including DA3); and the first pixel circuit and the second pixel circuit are arranged in different areas in the third active sub-area (Yang at FIGS. 2-10 illustrating CU3 arranged in different areas of DA3), and the first pixel circuit in the fourth active sub-area is located between adjacent second pixel circuits (Yang at FIGS. 2-10 and 16-19 illustrating arranged in different areas of SD1 SD3 and SD4 therein).
Before the effective filing date, it would have been obvious to a person of ordinary skill in the art to modify the display device and pixel arrangement of Ge to incorporate the dummy circuits and placement of other pixel circuits as disclosed by Yang because the references are within the same field of endeavor, namely, display panels with multiple display areas with modified pixelation and driving based on display area. The motivation to combine these references would have been to improve manufacturing of the device by shifting uneven exposure during the etching process to the dummy circuits (see Yang at least at [0128]). Therefore, a person of ordinary skill in the art would have been motivated to combine the prior art to achieve the claimed invention and there would have been a reasonable expectation of success.
Regarding claim 19, Ge in view of Yang discloses the display panel according to claim 18 (see above), wherein the first active sub-area comprises a fifth active sub-area and a sixth active sub-area (Yang at FIGS. 2-10 noting further and arbitrary division and demarcation is possible of the exemplary areas of Yang, for example WA may be divided into a left and right half or top half and bottom half, as is known by one of ordinary skill), and the third active sub-area comprises a seventh active sub-area and an eighth active sub-area (Yang at FIGS. 2-10 noting further and arbitrary division and demarcation is possible of the exemplary areas of Yang, for example SD1 and SD2 may be further divided into top half and bottom half, left half and right have as needed), the seventh active sub-area being adjacent to the fifth active sub-area, and the eighth active sub-area being adjacent to the sixth active sub-area (Yang at FIGS. 2-10 and adjacent portions would be clear and obvious based on the arbitrary divisions of the areas above as known by one of ordinary skill); the seventh active sub-area comprises a first area and a second area, the first pixel circuit corresponding to the sub-pixel in the fifth active sub-area being located in the first area (Yang at FIGS. 2-10 and adjacent portions would be clear and obvious based on the arbitrary divisions of the areas above as known by one of ordinary skill, placement of pixel circuits with relation to the area would be based on these delineations, noting possibly non-linear divisions), and the second pixel circuit corresponding to the sub-pixel in the seventh active sub-area being located in the second area(Yang at FIGS. 2-10 and adjacent portions would be clear and obvious based on the arbitrary divisions of the areas above as known by one of ordinary skill, placement of pixel circuits with relation to the area would be based on these delineations, noting possibly non-linear divisions); the eighth active sub-area comprises a third area and a fourth area, the first pixel circuit corresponding to the sub-pixel in the sixth active sub-area being located in the third area, and the second pixel circuit corresponding to the sub-pixel in the eighth active sub-area being located in the fourth area (Yang at FIGS. 2-10 and adjacent portions would be clear and obvious based on the arbitrary divisions of the areas above as known by one of ordinary skill, placement of pixel circuits with relation to the area would be based on these delineations, noting possibly non-linear divisions); the display panel further comprises dummy pixel circuits (Yang at FIGS. 16-19 and [0124]-[0137]), wherein at least a portion of the dummy pixel circuits in the third active sub-area are reused as at least one of the first pixel circuit and the second pixel circuit (Yang at FIGS. 16-19 and [0122]-[0137]); at least a portion of the dummy pixel circuits in the fourth active sub-area are reused as the first pixel circuit (Yang at FIGS. 16-19 and [0124]-[0137]); and the first active sub-area and the second active sub-area are arranged in a first direction, the fourth active sub-area is located on one side of the second active sub-area that is far away from the first active sub-area (Yang FIGS. 2-10 and 16-19 adjacent and disparate portions would be clear and obvious based on the arbitrary divisions of the areas above as known by one of ordinary skill, placement of pixel circuits with relation to the area would be based on these delineations, noting possibly non-linear divisions), the fifth active sub-area and the sixth active sub-area are arranged in a second direction, the seventh active sub-area and the eighth active sub-area are respectively located on either sides of the first active sub-area, the first area and the second area are arranged in the first direction, and the third area and the fourth area are arranged in the first direction, the first direction being perpendicular to the second direction (Yang FIGS. 2-10 and 16-21 adjacent portions would be clear and obvious based on the arbitrary divisions of the areas above as known by one of ordinary skill, placement of pixel circuits with relation to the area would be based on these delineations, noting possibly non-linear divisions).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al., US 2021/0327958 A1;
Wu et al., US 12,272,776 B2;
Tian, US 12,004,409 B2;
Lu et al., US 11,984,079 B2;
Wang et al., US 11,727,861 B2;
Xu et al., US 2021/0313405 A1;
Du et al., US 2022/0293715 A1;
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARVESH J NADKARNI whose telephone number is (571)270-7562. The examiner can normally be reached 8AM-5PM M-F.
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