DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendments filed on have been entered. Claims 1, 3, 44, 45, and 47 have been amended.
Response to Arguments
With respect to claim 1, applicant argues that Lee fails to disclose or suggest "wherein the stage circuit does not include a transistor having a first electrode connected to the third node and a gate electrode configured to receive the second clock signal," as recited in amended claim 1. Examiner respectfully disagrees. The SPEC does not specifically state “wherein the stage circuit does not include a transistor having a first electrode connected to the third node and a gate electrode configured to receive the second clock signal”. Therefore, it is a new matter. Please see the details below. With respect to independent claims 44 and 45, applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Nowhere in the specifications is it discloses “wherein the stage circuit does not include a transistor having a first electrode connected to the third node and a gate electrode configured to receive the second clock signal”. Although such a transistor is not shown or mentioned in the drawings or specification but that does not preclude one from being included in the disclosed embodiment as discussed in MPEP 2173.05(i), which is quoted below.
“Any negative limitation or exclusionary proviso must have basis in the original disclosure. If alternative elements are positively recited in the specification, they may be explicitly excluded in the claims. See In re Johnson, 558 F.2d 1008, 1019, 194 USPQ 187, 196 (CCPA 1977) (“[the] specification, having described the whole, necessarily described the part remaining.”). See also Ex parte Grasselli, 231 USPQ 393 (Bd. App. 1983), aff' d mem., 738 F.2d 453 (Fed. Cir. 1984). The mere absence of a positive recitation is not basis for an exclusion. Any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement.” MPEP 2173.05(i).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (US 2019/0378458).
As to claim 1, Lee teaches a scan driver for a display device, the scan driver comprising: a stage circuit (stage PST1, fig. 6) which controls a voltage of an output terminal (an output terminal 209, fig. 6) based on voltages of a first node (node N1, fig. 6) and a second node (node N2, fig. 6), where the stage circuit comprises: a first transistor (PT1, fig. 6) connected between a first input terminal (a third input terminal 205, fig. 6) and a third node (node N3, fig. 6), a gate electrode of the first transistor being connected to a second input terminal to which a first clock signal is supplied (first input terminal 201, CLK1, fig. 6); a second transistor (PT4, fig. 6) connected between a first power input terminal (VGH, fig. 6) and the output terminal (an output terminal 209, fig. 6), a gate electrode of the second transistor being connected to the first node (node N1, fig. 6); a third transistor (PT5, fig. 6) connected between a third input terminal to which a second clock signal is supplied (second input terminal 203, CLK2,Claim Rejections - 35 USC § 112
fig. 6) and the output terminal (an output terminal 209, fig. 6), a gate electrode of the third transistor being connected to the second node (node N2, fig. 6); a fourth transistor (PT6, fig. 6) connected between the first node (N1, fig. 6) and the second input terminal (first input terminal 201, fig. 6), a gate electrode of the fourth transistor being connected to the third node (node N3, fig. 6); and a fifth transistor (PT7, fig. 6) connected between the first node (N1, fig. 6) and a second power input terminal (VGL, fig. 6), a gate electrode of the fifth transistor being connected to the second input terminal (first input terminal 201, fig. 6), wherein the third node (N3, fig. 6) is electrically connected to the second node (N2, fig. 6) during at least a portion of a period in which the first transistor is turned on (PT1, fig. 6),
wherein the stage circuit does not include a transistor having a first electrode connected to the third node and a gate electrode configured to receive the second clock signal.
As to claim 2, Lee teaches the scan driver, further comprising: a first capacitor (C1, fig. 6) connected between the output terminal (an output terminal 209, fig. 6) and the second node (node N2, fig. 6); and a second capacitor (C2, fig. 6) connected between the first power input terminal (VGH, fig. 6) and the first node (N1, fig. 6).
As to claim 3, Lee teaches the scan driver, wherein the first input terminal (a third input terminal 205, fig. 6) receives a start signal or a carry signal from a previous stage circuit ([0093] the first stage PST1 receives the scan start signal PSSP, fig. 6), the third input terminal (second input terminal 203, fig. 6) receives the second clock signal (CLK2, fig. 6) having a same period but a different phase than the first clock signal (Fig. 7 illustrates that CLK1 and CLK2 have the same period but different phase), the first power input terminal receives a voltage of a first power source (VGH, fig. 6), and the second power input terminal receives a voltage of a second power source (VGL, fig. 6) having a lower voltage than that of the first power source ([0098] the first voltage VGH is set to a high level, for example, a high-level voltage, [0106] the second voltage VGL is set to a low level, for example, a low-level voltage).
As to claim 4, Lee teaches the scan driver, further comprising a sixth transistor (PT8, fig. 6) connected between the second node (node N2, fig. 6) and the third node (N3, fig. 6), a gate electrode of the sixth transistor being connected to the second power input terminal (VGL, fig. 6).
13-43 (canceled)
5-12 and 48-51 (withdrawn)
Claim(s) 44-47 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al (US 2022/0101774).
As to claim 44, Lim teaches a display device comprising: pixels (a plurality of pixels PX, fig. 1) connected to scan lines ( scan lines SL1 to SLm, fig. 1) and data lines (data lines DL1 to DLn, fig. 1); and a scan driver (scan driver 13, fig. 1) comprising a plurality of stage circuits (stage circuits, figs. 3-4) to supply scan signals to the scan lines ([0049] The scan driver 13 … generate scan signals to be provided to scan lines SL1, SL2, SL3), wherein one of the plurality of stage circuits comprises: a first transistor (T1b, fig. 13) connected between a first input terminal (IC1, fig. 13) and a second node (N3b, fig. 13), a gate electrode of the first transistor being connected to a second input terminal (IK1, fig. 13); a second transistor (T5b, fig. 13) connected between a first power input terminal (IV2, fig. 13) and an output terminal (a first output terminal OT1, fig. 13), a gate electrode of the second transistor being connected to a first node (N2b, fig. 13); a third transistor (T6b, fig. 13) connected between a third input terminal (IK3, fig. 13) and the output terminal (a first output terminal OT1, fig. 13), a gate electrode of the third transistor being connected to the second node (N3b, fig. 13); a fourth transistor (T3b, fig. 13) connected between the first node (N2b, fig. 13) and the second input terminal (IK1, fig. 13), a gate electrode of the fourth transistor being connected to the second node (N3b, fig. 13); and a fifth transistor (T4b, fig. 13) connected between the first node (N2b, fig. 13) and a second power input terminal (IV1, fig. 13), a gate electrode of the fifth transistor being connected to the second input terminal (IK1, fig. 13),
wherein the first input terminal (IC1, fig. 13) receives a start signal or a carry signal (a scan start line FLML, fig. 13) that transitions before the first transistor (T1b, fig. 13) is turned on by a first clock signal (CKL1, fig. 13) received at the second input terminal (IK1, fig. 13, Fig. 14 illustrates that a scan start line FLML changes from high to low before CK1 changes to low level from a high level to turn on transistor T1b).
As to claim 45, Lim teaches an electronic device, comprising a processor to provide image data ([0047] The timing controller 11 may receive an external input signal from an external processor. The external input signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, RGB data); and a display device to display an image based on the image data ([0047] The RGB data may be supplied in units of pixel rows in the horizontal periods in response to the data enable signal. The RGB data corresponding to one frame may be referred to as one input image), wherein the display device comprises: pixels (pixels PX, fig. 1) connected to scan lines (scan lines SL1 to SLm, fig. 1) and data lines (data lines DL1 to DLn, fig. 1); and a scan driver (scan driver 13, fig. 1) comprising a plurality of stage circuits (stage circuits, figs. 3-4) to supply scan signals to the scan lines ([0049] The scan driver 13 … generate scan signals to be provided to scan lines SL1, SL2, SL3), wherein one of the plurality of stage circuits comprises: a first transistor (T1b, fig. 13) connected between a first input terminal (IC1, fig. 13) and a second node (N3b, fig. 13), a gate electrode of the first transistor being connected to a second input terminal (IK1, fig. 13); a second transistor (T5b, fig. 13) connected between a first power input terminal (IV2, fig. 13) and an output terminal (a first output terminal OT1, fig. 13), a gate electrode of the second transistor being connected to a first node (N2b, fig. 13); a third transistor (T6b, fig. 13) connected between a third input terminal (IK3, fig. 13) and the output terminal (a first output terminal OT1, fig. 13), a gate electrode of the third transistor being connected to the second node (N3b, fig. 13); a fourth transistor (T3b, fig. 13) connected between the first node (N2b, fig. 13) and the second input terminal (IK1, fig. 13), a gate electrode of the fourth transistor being connected to the second node (N3b, fig. 13); and a fifth transistor (T4b, fig. 13) connected between the first node (N2b, fig. 13) and a second power input terminal (IV1, fig. 13), a gate electrode of the fifth transistor being connected to the second input terminal (IK1, fig. 13),
wherein the first input terminal receives a start signal or a carry signal
that transitions after the first transistor is turned off by a first clock signal
received at the second input terminal (Fig. 14 illustrates that FLM transition from high level to low level after CK1 is turned high to turn off T1b).
As to claim 46, Lim teaches the display device, wherein one of the plurality of stage circuits further comprises: a first capacitor (C1b, fig. 13) connected between the output terminal (a first output terminal OT1, fig. 13) and the second node (N3b, fig. 13); and a second capacitor (C3b, fig. 13) connected between the first power input terminal (IV2, fig. 13) and the first node (N2b, fig. 13).
As to claim 47, Lim teaches the display device, wherein the first input terminal (IC1, fig. 13) receives the start signal or the carry signal from a previous stage circuit (a scan start line FLML, fig. 13), the third input terminal (IK3, fig. 13) receives a second clock signal (CKL2, fig. 13) having a same period but a different phase than the first clock signal (CKL1, fig. 13, Fig. 14 illustrates CKL1 and CKL2 have the same period but different phases, that is, when CKL1 is high, CKL2 is low), the first power input terminal (IV2, fig. 13) receives a voltage of a first power source (VGHL, fig. 13), and the second power input terminal (IV1, fig. 13) receives a voltage of a second power source (VGLL, fig. 13) having a lower voltage than that of the first power source ([0064] A second power source voltage of the second power line VGHL may be greater than a first power source voltage of the first power line VGLL).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached at (571)272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMEN W BOGALE/ Examiner, Art Unit 2628
/NITIN PATEL/ Supervisory Patent Examiner, Art Unit 2628
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