DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 4 corresponding to fig. 8 in the reply filed on 04/07/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
1. Claim(s) 1-4 and 44-47 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (US 2019/0378458).
As to claim 1, Lee teaches a scan driver for a display device, the scan driver comprising: a stage circuit (stage PST1, fig. 6) which controls a voltage of an output terminal (an output terminal 209, fig. 6) based on voltages of a first node (node N1, fig. 6) and a second node (node N2, fig. 6), where the stage circuit comprises: a first transistor (PT1, fig. 6) connected between a first input terminal (a third input terminal 205, fig. 6) and a third node (node N3, fig. 6), a gate electrode of the first transistor being connected to a second input terminal (first input terminal 201, fig. 6); a second transistor (PT4, fig. 6) connected between a first power input terminal (VGH, fig. 6) and the output terminal (an output terminal 209, fig. 6), a gate electrode of the second transistor being connected to the first node (node N1, fig. 6); a third transistor (PT5, fig. 6) connected between a third input terminal (second input terminal 203, fig. 6) and the output terminal (an output terminal 209, fig. 6), a gate electrode of the third transistor being connected to the second node (node N2, fig. 6); a fourth transistor (PT6, fig. 6) connected between the first node (N1, fig. 6) and the second input terminal (first input terminal 201, fig. 6), a gate electrode of the fourth transistor being connected to the third node (node N3, fig. 6); and a fifth transistor (PT7, fig. 6) connected between the first node (N1, fig. 6) and a second power input terminal (VGL, fig. 6), a gate electrode of the fifth transistor being connected to the second input terminal (first input terminal 201, fig. 6), wherein the third node (N3, fig. 6) is electrically connected to the second node (N2, fig. 6) during at least a portion of a period in which the first transistor is turned on (PT1, fig. 6).
As to claim 2, Lee teaches the scan driver, further comprising: a first capacitor (C1, fig. 6) connected between the output terminal (an output terminal 209, fig. 6) and the second node (node N2, fig. 6); and a second capacitor (C2, fig. 6) connected between the first power input terminal (VGH, fig. 6) and the first node (N1, fig. 6).
As to claim 3, Lee teaches the scan driver, wherein the first input terminal (a third input terminal 205, fig. 6) receives a start signal or a carry signal from a previous stage circuit ([0093] the first stage PST1 receives the scan start signal PSSP, fig. 6), the second input terminal (first input terminal 201, fig. 6) receives a first clock signal (CLK1, fig. 6), the third input terminal (second input terminal 203, fig. 6) receives a second clock signal (CLK2, fig. 6) having a same period but a different phase than the first clock signal (Fig. 7 illustrates that CLK1 and CLK2 have the same period but different phase), the first power input terminal receives a voltage of a first power source (VGH, fig. 6), and the second power input terminal receives a voltage of a second power source (VGL, fig. 6) having a lower voltage than that of the first power source ([0098] the first voltage VGH is set to a high level, for example, a high-level voltage, [0106] the second voltage VGL is set to a low level, for example, a low-level voltage).
As to claim 4, Lee teaches the scan driver, further comprising a sixth transistor (PT8, fig. 6) connected between the second node (node N2, fig. 6) and the third node (N3, fig. 6), a gate electrode of the sixth transistor being connected to the second power input terminal (VGL, fig. 6).
As to claim 44, Lee teaches a display device comprising: pixels (a plurality of pixels PX, fig. 1) connected to scan lines ( scan lines PS1 to PSn, fig. 1) and data lines (data lines D1 to Dm, fig. 1); and a scan driver (scan driver 20, fig. 1) comprising a plurality of stage circuits ([0092] the scan driver 20 includes a plurality of stages PST1 to PSTn) to supply scan signals to the scan lines ([0054] scan driver 20 generates a plurality of scan signals ), wherein one of the plurality of stage circuits comprises: a first transistor (PT1, fig. 8) connected between a first input terminal (a third input terminal 205, fig. 8) and a second node (second node N2, fig. 8), a gate electrode of the first transistor being connected to a second input terminal (first input terminal 201, fig. 8); a second transistor (fourth transistor PT4, fig. 8) connected between a first power input terminal (VGH, fig. 8) and an output terminal (output terminal 209, fig. 8), a gate electrode of the second transistor being connected to a first node (N1, fig. 8); a third transistor (PT5, fig. 8) connected between a third input terminal (second input terminal 203, fig. 8) and the output terminal (output terminal 209, fig. 8), a gate electrode of the third transistor being connected to the second node (N2, fig. 8); a fourth transistor (PT6, fig. 8) connected between the first node (N1, fig. 8) and the second input terminal (first input terminal 201, fig. 8), a gate electrode of the fourth transistor being connected to the second node (node N2, fig. 8); and a fifth transistor (PT7, fig. 8) connected between the first node (N1, fig. 8) and a second power input terminal (VGL, fig. 8), a gate electrode of the fifth transistor being connected to the second input terminal (first input terminal 201, fig. 8).
As to claim 45, Lee teaches an electronic device, comprising a processor to provide image data ([0063] the signal controller 60 may generate the image data signal DATA through an image processing process , fig. 1); and a display device to display an image based on the image data ([0058] The data driver 30 selects a gray voltage depending on the image data signal DATA and transmits the selected gray voltage to the plurality of data lines D1 to Dm as a data signal), wherein the display device comprises: pixels (a plurality of pixels PX, fig. 1) connected to scan lines (scan lines PS1 to PSn, fig. 1) and data lines (data lines D1 to Dm, fig. 1); and a scan driver (scan driver 20, fig. 1) comprising a plurality of stage circuits ([0092] the scan driver 20 includes a plurality of stages PST1 to PSTn) to supply scan signals to the scan lines ([0054] scan driver 20 generates a plurality of scan signals ), wherein one of the plurality of stage circuits comprises: a first transistor (PT1, fig. 8) connected between a first input terminal (a third input terminal 205, fig. 8) and a second node (second node N2, fig. 8), a gate electrode of the first transistor being connected to a second input terminal (first input terminal 201, fig. 8); a second transistor (fourth transistor PT4, fig. 8) connected between a first power input terminal (VGH, fig. 8) and an output terminal (output terminal 209, fig. 8), a gate electrode of the second transistor being connected to a first node (N1, fig. 8); a third transistor (PT5, fig. 8) connected between a third input terminal (second input terminal 203, fig. 8) and the output terminal (output terminal 209, fig. 8), a gate electrode of the third transistor being connected to the second node (N2, fig. 8); a fourth transistor (PT6, fig. 8) connected between the first node (N1, fig. 8) and the second input terminal (first input terminal 201, fig. 8), a gate electrode of the fourth transistor being connected to the second node (node N2, fig. 8); and a fifth transistor (PT7, fig. 8) connected between the first node (N1, fig. 8) and a second power input terminal (VGL, fig. 8), a gate electrode of the fifth transistor being connected to the second input terminal (first input terminal 201, fig. 8).
As to claim 46, Lee teaches the display device, wherein one of the plurality of stage circuits further comprises: a first capacitor (C1, fig. 8) connected between the output terminal (209, fig. 8) and the second node (N2, fig. 8); and a second capacitor (C2, fig. 8) connected between the first power input terminal (VGH, fig. 8) and the first node (N1, fig. 8).
As to claim 47, Lee teaches the display device, wherein the first input terminal (a third input terminal 205, fig. 8) receives a start signal or a carry signal from a previous stage circuit ([0093] the first stage PST1 receives the scan start signal PSSP, fig. 8), the second input terminal (first input terminal 201, fig. 8) receives a first clock signal (CLK1, fig. 8), the third input terminal (second input terminal 203, fig. 8) receives a second clock signal (CLK2, fig. 8) having a same period but a different phase than the first clock signal (Fig. 7 illustrates that CLK1 and CLK2 have the same period but different phase), the first power input terminal receives a voltage of a first power source (VGH, fig. 8), and the second power input terminal receives a voltage of a second power source (VGL, fig. 8) having a lower voltage than that of the first power source ([0144] the first voltage VGH is set to a high level, for example, a high-level voltage, [0146] the second voltage VGL is set to a low level, for example, a low-level voltage).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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/AMEN W BOGALE/Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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