Prosecution Insights
Last updated: July 17, 2026
Application No. 19/220,616

DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME

Non-Final OA §102§103
Filed
May 28, 2025
Priority
Jul 30, 2024 — RE 10-2024-0100802
Examiner
MCLOONE, PETER D
Art Unit
2621
Tech Center
2600 — Communications
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
493 granted / 596 resolved
+20.7% vs TC avg
Minimal +3% lift
Without
With
+3.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
15 currently pending
Career history
613
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
80.7%
+40.7% vs TC avg
§102
13.7%
-26.3% vs TC avg
§112
0.5%
-39.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 596 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 5, 6, 15, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pyun et al. (US 20230186831 A1, hereafter Pyun). Regarding claim 1, Pyun teaches a display device comprising: a display panel (100) including pixels (P) (Fig. 1, [0058]); a gate driving circuit (300) which provides a gate signal to the display panel (Fig. 1, [0066]); a data driving circuit which provides a data signal to the display panel (Fig. 1, [0069]); a driving voltage supplying circuit (600) which supplies a gate driving voltage to the gate driving circuit, supplies a data driving voltage to the data driving circuit, and supplies a panel driving voltage including a first power supply voltage and a second power supply voltage lower than the first power supply voltage to the display panel (Fig. 1, [0070]-[0071], [0083], where the power voltage generator supplies driving voltages to the display panel 100, gate driver 300, and data driver 500, where the display panel is receiving high and low power voltages); and a driving control circuit (200) which controls the gate driving circuit, the data driving circuit, and the driving voltage supplying circuit (Fig. 1, [0059]-[0061], [0071]), wherein the driving control circuit determines a scale factor based on a load of input frame data, generates output frame data by applying the scale factor to the input frame data ([0079], where a scale factor SF[N+M] is determined on the basis of input image data IMG[N] of the N-th frame), and determines the first power supply voltage and an input power supply voltage for generating the first power supply voltage based on a maximum grayscale of the input frame data and a load of the output frame data ([0082]-[0083], where the maximum grayscale value calculator 240 determines the maximum grayscale value MG[N] and this value and the loa LD[N] are used by the voltage control signal generating block 250 to adjust the first power voltage ELVDD; Fig. 8, [0010], [0095]-[0096], [0105], where there is an input voltage VIN generated by the power voltage supply 650, where the operation of the power voltage supply is regulated according to load). Regarding claim 5, Pyun teaches the display device of claim 1, wherein the first power supply voltage is determined based on a power supply voltage variation graph indicating a correlation among the first power supply voltage, the load of the output frame data, and the maximum grayscale of the input frame data (Fig. 6, [0084], showing the relationship between the load LD, power voltage ELVDD’, and maximum grayscale value MG). Regarding claim 6, Pyun teaches the display device of claim 5, wherein the first power supply voltage increases as the maximum grayscale of the input frame data increases and increases as the load of the output frame data increases in the power supply voltage variation graph (Fig. 6, [0084], showing the relationship between the load LD, power voltage ELVDD’, and maximum grayscale value MG). Regarding claim 15, Pyun teaches an electronic device comprising: a processor which renders input frame data (Fig. 1, [0059], where there is an external device rendering input image data IMG); and a display device which displays an image (Fig. 1, [0055], where there is a display device with a display panel) corresponding to output frame data generated by applying a scale factor to the input frame data on a display panel ([0079], where a scale factor SF[N+M] is determined on the basis of input image data IMG[N] of the N-th frame) and varies a first power supply voltage applied to the display panel and an input power supply voltage for generating the first power supply voltage based on a maximum grayscale of the input frame data and a load of the output frame data ([0082]-[0083], where the maximum grayscale value calculator 240 determines the maximum grayscale value MG[N] and this value and the loa LD[N] are used by the voltage control signal generating block 250 to adjust the first power voltage ELVDD; Fig. 8, [0010], [0095]-[0096], [0105], where there is an input voltage VIN generated by the power voltage supply 650, where the operation of the power voltage supply is regulated according to load). Regarding claim 16, Pyun teaches the electronic device of claim 15, wherein the display device includes: the display panel (100) including pixels (P) (Fig. 1, [0058]); a gate driving circuit (300) which provides a gate signal to the display panel (Fig. 1, [0066]); a data driving circuit (500) which provides a data signal to the display panel (Fig. 1, [0069]); a driving voltage supplying circuit (600) which supplies a gate driving voltage to the gate driving circuit, supplies a data driving voltage to the data driving circuit, and supplies a panel driving voltage including the first power supply voltage and a second power supply voltage lower than the first power supply voltage to the display panel (Fig. 1, [0070]-[0071], [0083], where the power voltage generator supplies driving voltages to the display panel 100, gate driver 300, and data driver 500, where the display panel is receiving high and low power voltages); and a driving control circuit (200) which controls the gate driving circuit, the data driving circuit, and the driving voltage supplying circuit (Fig. 1, [0059]-[0061], [0071]), and wherein the driving control circuit determines the scale factor based on a load of the input frame data, generates the output frame data by applying the scale factor to the input frame data ([0079], where a scale factor SF[N+M] is determined on the basis of input image data IMG[N] of the N-th frame), and determines the first power supply voltage and the input power supply voltage based on the maximum grayscale of the input frame data and the load of the output frame data ([0082]-[0083], where the maximum grayscale value calculator 240 determines the maximum grayscale value MG[N] and this value and the loa LD[N] are used by the voltage control signal generating block 250 to adjust the first power voltage ELVDD; Fig. 8, [0010], [0095]-[0096], [0105], where there is an input voltage VIN generated by the power voltage supply 650, where the operation of the power voltage supply is regulated according to load). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Pyun et al. (US 20230186831 A1, hereafter Pyun) in view of Kim et al. (US 20250182682, hereafter Kim ‘682). Regarding claim 2, Pyun teaches the display device of claim 1, wherein the driving control circuit determines the input power supply voltage to be higher than the first power supply voltage by a predetermined voltage ([0105], where the power voltage supply 650 is a switching mode power supply that generates the first power supply voltage based on the input voltage VIN). But, Pyun does not explicitly teach the display device wherein the driving voltage supplying circuit generates the first power supply voltage by buck-converting the input power supply voltage. However, this was well known in the art as evidenced by Kim ‘682 (Fig. 4, [0065]-[0067], [0181], where the power circuit may include a buck converter). Both Pyun and Kim ‘682 teach display devices having voltages input through power circuits. Pyun explicitly teaches a switching mode power supply (SMPS), but does not specifically teach the use of a buck converter. Buck converters are a class of SMPS. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the power voltage supply of Pyun using a buck converter as taught by Kim ‘682 and such an implementation would have yielded a predictable result. Regarding claim 17, Pyun teaches the electronic device of claim 16, wherein the driving control circuit determines the input power supply voltage to be higher than the first power supply voltage by a predetermined voltage ([0105], where the power voltage supply 650 is a switching mode power supply that generates the first power supply voltage based on the input voltage VIN). But, Pyun does not explicitly teach the electronic device wherein the driving voltage supplying circuit generates the first power supply voltage by buck-converting the input power supply voltage. However, this was well known in the art as evidenced by Kim ‘682 (Fig. 4, [0065]-[0067], [0181], where the power circuit may include a buck converter). Both Pyun and Kim ‘682 teach display devices having voltages input through power circuits. Pyun explicitly teaches a switching mode power supply (SMPS), but does not specifically teach the use of a buck converter. Buck converters are a class of SMPS. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the power voltage supply of Pyun using a buck converter as taught by Kim ‘682 and such an implementation would have yielded a predictable result. Claims 7, 9, 12, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Pyun et al. (US 20230186831 A1, hereafter Pyun) in view of Kim et al. (US 20250322788 A1, hereafter Kim ‘788). Regarding claim 7, Pyun teaches a display device comprising: a display panel (100) including pixels (P) (Fig. 1, [0058]); a gate driving circuit (300) which provides a gate signal to the display panel (Fig. 1, [0066]); a data driving circuit which provides a data signal to the display panel (Fig. 1, [0069]); a driving voltage supplying circuit (600) which supplies a gate driving voltage to the gate driving circuit, supplies a data driving voltage to the data driving circuit, and supplies a panel driving voltage including a first power supply voltage and a second power supply voltage lower than the first power supply voltage to the display panel (Fig. 1, [0070]-[0071], [0083], where the power voltage generator supplies driving voltages to the display panel 100, gate driver 300, and data driver 500, where the display panel is receiving high and low power voltages); and a driving control circuit (200) which controls the gate driving circuit, the data driving circuit, and the driving voltage supplying circuit (Fig. 1, [0059]-[0061], [0071]), wherein the driving control circuit determines a scale factor based on a load of input frame data, generates output frame data by applying the scale factor to the input frame data (([0079], where a scale factor SF[N+M] is determined on the basis of input image data IMG[N] of the N-th frame). But Pyun does not explicitly teach the display device wherein the driving control circuity determines the first power supply voltage and an input power supply voltage for generating the first power supply voltage based on a brightness mode of the display panel. However, this was well known in the art as evidenced by Kim ‘788 (Fig. 2, [0028]-[0034], where there are a plurality of selectable brightness modes and where selection causes adjustment of the input power supply voltage). Both Pyun and Kim ‘788 teach display devices where driving voltages are set according to luminance information of input image data. Pyun teaches changing voltage according to a detected maximum grayscale value but does not teach a more generalized approach of modifying the power supply voltage according to a mode. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to permit direct control of the power supply voltage as taught by Kim ‘788 so as to provide the user with extra options for display operation. Regarding claim 9, the combination of Pyun and Kim ‘788 would show the display device of claim 7. Kim ‘788 in the combination further teaches the display device wherein the driving control circuit determines a first set voltage as the first power supply voltage when the brightness mode is a high-brightness mode having a first dynamic range, and determines a second set voltage lower than the first set voltage as the first power supply voltage when the brightness mode is a low-brightness mode having a second dynamic range narrower than the first dynamic range ([0028], [0031], where the brightness modes correspond to different HDR and SDR modes that have different ranges of brightness and colors). Regarding claim 12, the combination of Pyun and Kim ‘788 would show the display device of claim 9. Pyun further teaches the display device wherein the first power supply voltage is determined based on a power supply voltage variation graph indicating a correlation among the first power supply voltage, the load of the output frame data, and a luminance usage range of the brightness mode (Fig. 6, [0084], showing the relationship between the load LD, power voltage ELVDD’, and maximum grayscale value MG). Regarding claim 18, the combination of Pyun and Kim ‘788 would show the display device of claim 7. Pyun further teaches an electronic device comprising: the display device of claim 7; and a processor which renders the input frame data (Fig. 1, [0059], where there is an external device rendering input image data IMG). Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pyun et al. (US 20230186831 A1, hereafter Pyun) in view of Kim et al. (US 20250322788 A1, hereafter Kim ‘788) and Kim et al. (US 20250182682, hereafter Kim ‘682). Regarding claim 8, the combination of Pyun and Kim ‘788 would show the display device of claim 7. Pyun further teaches the display device wherein the driving control circuit determines the input power supply voltage to be higher than the first power supply voltage by a predetermined voltage ([0105], where the power voltage supply 650 is a switching mode power supply that generates the first power supply voltage based on the input voltage VIN). But, the combination does not explicitly teach the display device wherein the driving voltage supplying circuit generates the first power supply voltage by buck-converting the input power supply voltage. However, this was well known in the art as evidenced by Kim ‘682 (Fig. 4, [0065]-[0067], [0181], where the power circuit may include a buck converter). Both Pyun and Kim ‘682 teach display devices having voltages input through power circuits. Pyun explicitly teaches a switching mode power supply (SMPS), but does not specifically teach the use of a buck converter. Buck converters are a class of SMPS. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the power voltage supply of Pyun using a buck converter as taught by Kim ‘682 and such an implementation would have yielded a predictable result. Regarding claim 19, the combination of Pyun and Kim ‘788 would show the electronic device of claim 18. Pyun further teaches the electronic device wherein the driving control circuit determines the input power supply voltage to be higher than the first power supply voltage by a predetermined voltage ([0105], where the power voltage supply 650 is a switching mode power supply that generates the first power supply voltage based on the input voltage VIN). But, the combination does not explicitly teach the electronic device wherein the driving voltage supplying circuit generates the first power supply voltage by buck-converting the input power supply voltage. However, this was well known in the art as evidenced by Kim ‘682 (Fig. 4, [0065]-[0067], [0181], where the power circuit may include a buck converter). Both Pyun and Kim ‘682 teach display devices having voltages input through power circuits. Pyun explicitly teaches a switching mode power supply (SMPS), but does not specifically teach the use of a buck converter. Buck converters are a class of SMPS. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the power voltage supply of Pyun using a buck converter as taught by Kim ‘682 and such an implementation would have yielded a predictable result. Allowable Subject Matter Claims 3, 4, 10, 11, 13, and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The feature, as found in claims 3 and 10, of a display device wherein “wherein the scale factor is determined based on a net power control graph indicating a correlation between the scale factor and the load of the input frame data” is not found in the prior art along with the rest of the limitations of claims 3 and 10. The features, as found in claims 13 and 14, of a display device “wherein when the brightness mode is the high-brightness mode, the first set voltage corresponding to a maximum usage luminance of the high-brightness mode is determined as the first power supply voltage in the power supply voltage variation graph” or “wherein when the brightness mode is the low-brightness mode, the second set voltage corresponding to a maximum usage luminance of the low-brightness mode is determined as the first power supply voltage in the power supply voltage variation graph” is not found in the prior art along with rest of the limitations of claims 13 and 14. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER D MCLOONE whose telephone number is (571)272-4631. The examiner can normally be reached M-F 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 5712727764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER D MCLOONE/Primary Examiner, Art Unit 2621
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Prosecution Timeline

May 28, 2025
Application Filed
May 13, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
86%
With Interview (+3.4%)
1y 11m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 596 resolved cases by this examiner. Grant probability derived from career allowance rate.

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