DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in the Republic of Korea on 5/31/2024.
Information Disclosure Statement
The Information Disclosure Statement has been considered and placed in the record on file and is in compliance with USPTO requirements.
Drawings
The Drawings have been considered and placed in the record on file and are in compliance with USPTO requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 4, 11, 13, 16, and 17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lim et al. (US 2025/0322781 A1 hereinafter Lim).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In regards to claim 1, Lim discloses a driving circuit comprising a plurality of stages, wherein each of the plurality of stages comprises:
a first transistor connected to an input terminal, to which a start signal is input, and a first node, and comprising a gate connected to a first clock terminal, to which a first clock signal is input (see figure 5, transistor T1 connected to INS and node NQ1 and gate controlled by CLK1); and
a second transistor connected to a first output terminal and a second clock terminal, to which a second clock signal is input, and comprising a gate connected to the first node (see figure 5, transistor T10 gate connected to node NQ2 (NQ1 through T8) and to the output GW and GCLK),
wherein the second clock signal swings between a first voltage and a second voltage lower than the first voltage, and the first clock signal swings between the first voltage and a third voltage lower than the second voltage (see figure 4 and paragraph 0085, CLK1 has a low of VGL1 and GCLK2 has a low of VGL2, VGL2 is higher than the first VGL1).
In regards to claim 3, as recited in claim 1, Lim further discloses wherein each of the plurality of stages further comprises a third transistor connected to a first terminal, to which the first voltage is input, and the first output terminal, and comprising a gate connected to a second node (see figure 5, transistor T9 connected to VGH and to output GW and gate controlled by node NQB).
In regards to claim 4, as recited in claim 3, Lim further discloses wherein each of the plurality of stages further comprises:
a fourth transistor connected to the first terminal and a second output terminal, and comprising a gate connected to the second node (see figure 5, transistor T6 connected to VGH and to output CR and gate controlled by node NQB);
a fifth transistor connected to the second output terminal and a third clock terminal, to which a third clock signal is input, and comprising a gate connected to the first node (see figure 5, transistor T7 connected to CLK2 and output CR and gate controlled by NQ2); and
a first capacitor connected to the second output terminal and the first node (see figure 5, capacitor C1),
wherein the third clock signal swings between the first voltage and the third voltage and is input phase-shifted from the first clock signal by a 1/2 period (see figure 4).
In regards to claim 11, Lim discloses a driving circuit comprising a plurality of stages (see figure 3), wherein each of the plurality of stages comprises:
a control circuit which controls voltages of a first node and a second node based on a start signal input to an input terminal (see figure 5, nodes NQ1 and NQB with input terminal INS);
a first output circuit which outputs an output signal to a pixel of a display area based on the voltages of the first node and the second node (see figure 5, output GW connected to nodes NQB and NQ2); and
a second output circuit which outputs a carry signal to a next stage based on the voltages of the first node and the second node (see figure 5, output CR connected to nodes NQB and NQ2),
wherein the control circuit comprises a first transistor connected to the input terminal and the first node, and comprising a gate connected to a first clock terminal to which a first clock signal is input (see figure 5, transistor T1 connected to INS and node NQ1 and gate controlled by CLK1), the first output circuit comprises a second transistor connected to a first output terminal, which outputs the output signal, and a second clock terminal, to which a second clock signal is input, and comprising a gate connected to the first node (see figure 5, transistor T10 gate connected to node NQ2 (NQ1 through T8) and to the output GW and GCLK), and the second output circuit comprises a third transistor connected to a second output terminal, which outputs the carry signal, and a third clock terminal, to which a third clock signal is input, and comprising a gate connected to the first node (see figure 5, transistor T7 connected to CLK2 and to output CR and gate controlled by node NQ2), wherein the second clock signal swings between a first voltage and a second voltage lower than the first voltage, and the first clock signal and the third clock signal swing between the first voltage and a third voltage lower than the second voltage, wherein the third clock signal is input phase-shifted from the first clock signal by a 1/2 period (see figure 4 and paragraph 0085, CLK1 has a low of VGL1 and GCLK2 has a low of VGL2, VGL2 is higher than the first VGL1).
In regards to claim 13, as recited in claim 11, Lim further discloses wherein the first output circuit further comprises a fourth transistor connected to a first terminal, to which the first voltage is input, and the first output terminal, and comprising a gate connected to the second node (see figure 5, transistor T9 connected to VGH and to output GW and gate controlled by node NQB), and the second output circuit further comprises: a fifth transistor connected to the first terminal and the second output terminal, and comprising a gate connected to the second node (see figure 5, transistor T6 connected to VGH and to output CR and gate controlled by node NQB); and a first capacitor connected to the second output terminal and the first node (see figure 5, capacitor C1).
In regards to claim 16, Lim discloses an electronic device comprising:
a controller which outputs a plurality of clock signals (see figure 1, driving controller);
a power supply circuit which outputs a reference voltage (see figure 5, VGH, VGL1, therefore a power supply circuit); and
a driving circuit which outputs a gate signal based on the plurality of clock signals and the reference voltage, wherein the driving circuit comprises a plurality of stages (see figure 3),
wherein each of the plurality of stages comprises:
a first transistor connected to an input terminal, to which a start signal is input, and a first node and comprising a gate connected to a first clock terminal, to which a first clock signal is input (see figure 5, transistor T1 connected to INS and node NQ1 and gate controlled by CLK1); and
a second transistor connected to a first output terminal and a second clock terminal, to which a second clock signal is input, and comprising a gate connected to the first node (see figure 5, transistor T10 gate connected to node NQ2 (NQ1 through T8) and to the output GW and GCLK),
wherein the second clock signal swings between a first voltage and a second voltage lower than the first voltage, and the first clock signal swings between the first voltage and a third voltage lower than the second voltage (see figure 4 and paragraph 0085, CLK1 has a low of VGL1 and GCLK2 has a low of VGL2, VGL2 is higher than the first VGL1).
In regards to claim 17, as recited in claim 16, Lim further discloses wherein each of the plurality of stages further comprises:
a third transistor connected to a first terminal, to which the first voltage is input, and the first output terminal, and comprising a gate connected to a second node (see figure 5, transistor T9 connected to VGH and to output GW and gate controlled by node NQB);
a fourth transistor connected to the first terminal and a second output terminal, and comprising a gate connected to the second node (see figure 5, transistor T6 connected to VGH and to output CR and gate controlled by node NQB);
a fifth transistor connected to the second output terminal and a third clock terminal, to which a third clock signal is input, and comprising a gate connected to the first node (see figure 5, transistor T7 connected to CLK2 and output CR and gate controlled by NQ2); and
a first capacitor connected to the second output terminal and the first node (see figure 5, capacitor C1),
wherein the third clock signal swings between the first voltage and the third voltage and is input phase-shifted from the first clock signal by a 1/2 period (see figure 4).
Allowable Subject Matter
Claims 2, 5-10, 12, 14, 15, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER J KOHLMAN whose telephone number is (571)270-5503. The examiner can normally be reached 9-5:30.
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/CHRISTOPHER J KOHLMAN/Primary Examiner, Art Unit 2628