DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Application 19221575 and US Patent 12348382
Claim 1 is non-provisionally rejected on the ground of nonstatutory double patenting (anticipated). Limitations of the claim 1 in the instant application 19221575 “receiving updated requirements for an existing NoC topology, wherein the updated requirements results in incremental changes to initial requirements of the existing NoC topology”, and the limitation in claim 1 in the Patent 12348382 “receiving an update to an initial Network-on-Chip (NoC) topology, wherein the update results in updated requirements to initial requirements of the NoC” have similar subject matters.
Furthermore, Limitations of the claim 1 in the instant application 19221575 “modifying a portion of the existing NoC topology in order to satisfy the updated requirements and generate an incremental updated NoC topology from an incremental modification of the existing NoC topology that results in at least one of an unnecessary element and an unnecessary connection”, and the limitation in claim 1 in the Patent 12348382 “modifying a portion of the initial NoC topology that is impacted by the update in order to satisfy the update and generate an incremental updated NoC topology resulting in an incremental modification of the NoC in response to the update by changing existing components in the initial NoC topology, which becomes outdated and results in at least one of an unnecessary element and an unnecessary connection” have similar subject matters.
Furthermore, Limitations of the claim 1 in the instant application 19221575 “removing at least one of the unnecessary element and the unnecessary connection; generating an updated NoC topology that satisfies the updated requirements”, and the limitation in claim 1 in the Patent 12348382 “removing at least one of the unnecessary element and the unnecessary connection; generating an updated NoC topology that combines the initial NoC topology with the incremental updated NoC topology that satisfies the update” have similar subject matters.
Furthermore, Limitations of the claim 1 in the instant application 19221575 “providing a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from incremental modifications of the existing NoC topology”, and the limitation in claim 1 in the Patent 12348382 “providing a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from topology modifications.” have similar subject matters.
Claim 2 is non-provisionally (obviousness) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US Patent 12348382.
Limitations of the claim 2 in the instant application 19221575 “wherein components of the existing NoC topology include network components and connections between the network components”, which is not explicitly stated in claim 1 of the US Patent 12348382. It would have been obvious to a person skilled in the art before the effective filing date of the invention to modify the US Patent 12348382 in view of (“Kumar”, US 20150036536 A1) in order to represent NOC as network component and connectors (([0052-0055] Fig. 5b, Fig. 5c, Fig. 5d NoC has links and/or communication channels connecting the hosts/elements) because it would improve system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, ([0026]).
Claim 3 is non-provisionally (obviousness) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US Patent 12348382.
Limitations of the claim 3 in the instant application 19221575 “wherein the incremental modification includes at least one of eliminating a component and connection that is no longer needed.”, which is not explicitly stated in claim 1 of the US Patent 12348382. It would have been obvious to a person skilled in the art before the effective filing date of the invention to modify the US Patent 12348382 in view of (“Kumar”, US 20150036536 A1) in order to remove component and connection no longer being used in the NOC ([0094-0095] the flows can all be mapped first and relocated to alternative routes while removing the routers and channels from the earlier route if possible (e.g., no other flows are present there))) because it would improve system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, ([0026]).
Claim 4 is non-provisionally (obviousness) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US Patent 12348382.
Limitations of the claim 4 in the instant application 19221575 “adding components that are missing; and preserving names of existing components of the existing NoC topology”, which is not explicitly stated in claim 1 of the US Patent 12348382. It would have been obvious to a person skilled in the art before the effective filing date of the invention to modify the US Patent 12348382 in view of (“Kumar”, US 20150036536 A1) in order to adding components that are missing and saving the identification of the elements in the existing NOC mapping (([0084] After the router-port assignment, there may be one router per host port. In a grid based design methodology, the routers may be instantiated in a grid cell in which the ports reside. Subsequently, additional routers and NoC channels can be allocated to provide connectivity such that a more optimized NoC topology automatically forms)( ([0054-0055] Fig. 5b, Fig. 5c, Fig. 5d NoC link or communication can be redesigned to a new topology, this topology does not change the orientation of ports and/or hosts of the SoC environment, there is no SoC level change in topology and only the NoC interconnect topology is changed to allow a different and possibly more optimized route for the same traffic flows between components, on
reducing the interconnect bandwidth and latency or keeping average global communication
latency as an object function, in the modified topology in Fig. 5c and Fig. 5d all hosts and ports
kept their original names) because it would improve system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, ([0026]).
Claim 5 is non-provisionally (obviousness) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US Patent 12348382.
Limitations of the claim 5 in the instant application 19221575 “wherein preserving the names of the existing components further includes using edge clustering to combine connections.”, which is not explicitly stated in claim 1 of the US Patent 12348382. It would have been obvious to a person skilled in the art before the effective filing date of the invention to modify the US Patent 12348382 in view of (“Procopiuc”, US 20100274785 A1) in order to combine connections and paths between clusters ([0027-0029] Fig. 2, join path connecting clusters, for example join path 241 connects cluster 220 with cluster 210, join path 242 connects cluster 212 with cluster 230) because it would help re-allocate the resources among different clusters more efficiently by connecting the clusters using certain edges and connections within the clusters and would help utilize the resources within the clusters more appropriately.
Claim 6 is non-provisionally (obviousness) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US Patent 12348382.
Limitations of the claim 6 in the instant application 19221575 “using node clustering to cluster added components with existing components of the existing NoC topology to produce a clustered added component; and labelling the clustered added component using names of the existing components that formed part of the clustered added component”, which is not explicitly stated in claim 1 of the US Patent 12348382. It would have been obvious to a person skilled in the art before the effective filing date of the invention to modify the US Patent 12348382 in view of (“Stringham”, US 20150254325 A1) in order to adding nodes to the existing cluster and refer to cluster by name ([0111] adding clusters to multi-cluster database)([0038] cluster is a set of nodes), ([0046-0063] Fig. 2, Key space allocator assigns keys to each node in the cluster, assign a key to range of nodes, assign each cluster an identifier)(Fig. 3) because it helps allocate the resources among different clusters without
overloading or underloading certain clusters and would provide better manageability in utilizing the clusters/nodes more efficiently.
Claim 7 is non-provisionally (obviousness) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US Patent 12348382.
Limitations of the claim 7 in the instant application 19221575 “wherein generating the updated NoC topology includes moving existing components of the existing NoC topology to legal locations and minimizing connection lengths.”, which is not explicitly stated in claim 1 of the US Patent 12348382. It would have been obvious to a person skilled in the art before the effective filing date of the invention to modify the US Patent 12348382 in view of (“Kumar”, US 20150036536 A1) in order to moving components to certain locations within the NOC and reduce connection lengths (0028] automatically determining optimal positions, orientations, and configurations of hosts and/or ports within hosts in a SoC environment such that the optimal positions enable least latency and cost, high performance, and high bandwidth)([0061, 0063] Fig. 6 a host or a port within a host (e.g., x1) can be selected for
relocation consideration){Examiner interprets relocation as moving components to legal location based on the fact applicant has not provided any definition of legal position}, and minimizing connection lengths ([0054-0055] reduced wire length to reduce latency and interconnect bandwidth) because it would improve system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, ([0026]).
Claim 8 is non-provisionally (obviousness) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US Patent 12348382.
Limitations of the claim 8 in the instant application 19221575 “wherein generating the updated NoC topology includes updating timing of existing components of the existing NoC topology.”, which is not explicitly stated in claim 1 of the US Patent 12348382. It would have been obvious to a person skilled in the art before the effective filing date of the invention to modify the US Patent 12348382 in view of (“Gangwar”, US 20170060204 A1) in order to update timing/frequencies of component after
updating the topologies ([0027] change frequency of components in NoC when moving from one profile to another profile) because it would help synch between different hosts or layers in the NoC topologies which will reduce the latency metric when sending large traffic flows between different component and connectors.
Claim 9 is non-provisionally rejected on the ground of nonstatutory double patenting (anticipated). Limitations of the claim 9 in the instant application 19221575 “receive updated requirements for an existing NoC topology, wherein the updated requirements results in incremental changing initial requirements of the existing NoC topology”, and the limitation in claim 1 in the Patent 12348382 “receiving an update to an initial Network-on-Chip (NoC) topology, wherein the update results in updated requirements to initial requirements of the NoC” have similar subject matters.
Furthermore, Limitations of the claim 9 in the instant application 19221575 “modify a portion of the existing NoC topology in order to satisfy the updated requirements and generate an incremental updated NoC topology from an incremental modification of the existing NoC topology that results in at least one of an unnecessary element and an unnecessary connection”, and the limitation in claim 1 in the Patent 12348382 “modifying a portion of the initial NoC topology that is impacted by the update in order to satisfy the update and generate an incremental updated NoC topology resulting in an incremental modification of the NoC in response to the update by changing existing components in the initial NoC topology, which becomes outdated and results in at least one of an unnecessary element and an unnecessary connection” have similar subject matters.
Furthermore, Limitations of the claim 9 in the instant application 19221575 “remove at least one of the unnecessary element and the unnecessary connection based on the updated requirements;
generate an updated NoC topology that satisfies the updated requirements”, and the limitation in claim 1 in the Patent 12348382 “removing at least one of the unnecessary element and the unnecessary connection; generating an updated NoC topology that combines the initial NoC topology with the incremental updated NoC topology that satisfies the update” have similar subject matters.
Furthermore, Limitations of the claim 9 in the instant application 19221575 “output a computer readable format of the updated NoC topology thereby eliminating errors and minimizing delays resulting from changing a portion of the existing NoC topology.”, and the limitation in claim 1 in the Patent 12348382 “providing a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from topology modifications.” have similar subject matters.
Claim 10 is non-provisionally (obviousness) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US Patent 12348382.
Limitations of the claim 10 in the instant application 19221575 “wherein generation of the updated NoC topology includes causing the design tool to move components of the existing NoC topology to legal locations and minimizing connection lengths that satisfy the updated requirements”, which is not explicitly stated in claim 1 of the US Patent 12348382. It would have been obvious to a person skilled in the art before the effective filing date of the invention to modify the US Patent 12348382 in view of (“Kumar”, US 20150036536 A1) in order to moving components to certain locations within the NOC and reduce connection lengths (0028] automatically determining optimal positions, orientations, and configurations of hosts and/or ports within hosts in a SoC environment such that the optimal positions enable least latency and cost, high performance, and high bandwidth)([0061, 0063] Fig. 6 a host or a port within a host (e.g., x1) can be selected for relocation consideration){Examiner interprets relocation as moving components to legal location based on the fact applicant has not provided any definition of legal position}, and minimizing connection lengths ([0054-0055] reduced wire length to reduce latency and interconnect bandwidth) because it would improve system efficiency by accurately indicating the best possible positions and configurations for hosts and ports within the hosts, ([0026]).
Claim 11 is non-provisionally (obviousness) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US Patent 12348382.
Limitations of the claim 11 in the instant application 19221575 “wherein generation of the updated NoC topology includes causing the design tool to update timing of existing components of the existing NoC topology”, which is not explicitly stated in claim 1 of the US Patent 12348382. It would have been obvious to a person skilled in the art before the effective filing date of the invention to modify the US Patent 12348382 in view of (“Gangwar”, US 20170060204 A1) in order to update timing/frequencies of component after updating the topologies ([0027] change frequency of components in NoC when moving from one profile to another profile) because it would help synch between different hosts or layers in the NoC topologies which will reduce the latency metric when sending large traffic flows between different component and connectors.
Application 19221575 and US Patent 11956127
Claim 1 is non-provisionally rejected on the ground of nonstatutory double patenting (anticipated). Limitations of the claim 1 in the instant application 19221575 “receiving updated requirements for an existing NoC topology, wherein the updated requirements results in incremental changes to initial requirements of the existing NoC topology”, and the limitation in claim 1 in the Patent 11956127 “receive an initial Network-on-Chip (NoC) topology that satisfies and is based on initial requirements, wherein the initial NoC topology includes elements and connections, and receive an update to the initial requirements, wherein the update results in updated requirements;” have similar subject matters.
Furthermore, Limitations of the claim 1 in the instant application 19221575 “modifying a portion of the existing NoC topology in order to satisfy the updated requirements and generate an incremental updated NoC topology from an incremental modification of the existing NoC topology that results in at least one of an unnecessary element and an unnecessary connection”, and the limitation in claim 1 in the Patent 11956127 “make incremental modifications to a portion of the initial NoC topology that is impacted by the updated requirements in order to satisfy the updated requirements and generate an incremental updated NoC topology, each incremental modification is in response to the update and changes existing components in the initial NoC topology, wherein the incremental modifications result in the initial NoC topology being outdated resulting in at least one of an unnecessary element and an unnecessary connection” have similar subject matters.
Furthermore, Limitations of the claim 1 in the instant application 19221575 “removing at least one of the unnecessary element and the unnecessary connection; generating an updated NoC topology that satisfies the updated requirements, providing a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from incremental modifications of the existing NoC topology”, and the limitations in claim 1 in the Patent 11956127 “remove at least one of the unnecessary element and the unnecessary connection, generate a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from topology modifications, wherein minimizing changes includes preserving names of the existing components from the initial NoC topology in the updated NoC topology” have similar subject matters.
Claim 2 is non-provisionally (anticipated) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of US Patent 11956127.
Limitations of the claim 2 in the instant application 19221575 “wherein components of the existing NoC topology include network components and connections between the network components”, and limitations in claim 3 of US Patent 11956127 “wherein the existing components include network components and connections between the network components” have similar subject matter.
Claim 3 is non-provisionally (anticipated) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of US Patent 11956127.
Limitations of the claim 3 in the instant application 19221575 “wherein the incremental modification includes at least one of eliminating a component and connection that is no longer needed.”, and limitations in claim 4 of US Patent 11956127 “wherein the incremental modifications include eliminating a component and/or connection that is no longer needed.” have similar subject matter.
Claim 4 is non-provisionally (anticipated) rejected on the ground of nonstatutory double patenting as being unpatentable over claims 5 of US Patent 11956127.
Limitations of the claim 4 in the instant application 19221575 “adding components that are missing; and preserving names of existing components of the existing NoC topology”, and limitations in claims 5 of US Patent 11956127 “wherein the incremental modifications include adding components that are missing and preserving the names” have similar subject matter.
Claim 5 is non-provisionally (anticipated) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of US Patent 11956127.
Limitations of the claim 5 in the instant application 19221575 “wherein preserving the names of the existing components further includes using edge clustering to combine connections.”, and limitations in claims 6 of US Patent 11956127 “wherein preserving the names of the existing components further includes using edge clustering to combine connections” have similar subject matter.
Claim 6 is non-provisionally (anticipated) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of US Patent 11956127.
Limitations of the claim 6 in the instant application 19221575 “using node clustering to cluster added components with existing components of the existing NoC topology to produce a clustered added component; and labelling the clustered added component using names of the existing components that formed part of the clustered added component”, and limitations in claims 5 of US Patent 11956127 “using node clustering to cluster the added components with the existing components to produce a clustered added components, and refer to the clustered added components by the existing components' names that formed part of the clustered added components” have similar subject matter.
Claim 7 is non-provisionally (anticipated) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of US Patent 11956127.
Limitations of the claim 7 in the instant application 19221575 “wherein generating the updated NoC topology includes moving existing components of the existing NoC topology to legal locations and minimizing connection lengths”, and limitations in claims 7 of US Patent 11956127 “wherein generating the updated NoC topology includes moving the existing components to legal locations, and minimizing connection lengths” have similar subject matter.
Claim 8 is non-provisionally (anticipated) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of US Patent 11956127.
Limitations of the claim 8 in the instant application 19221575 “wherein generating the updated NoC topology includes updating timing of existing components of the existing NoC topology” and the limitations in claims 8 of US Patent 11956127 “wherein generating the updated NoC topology includes updating timing of the existing components.” have similar subject matter.
Claim 9 is non-provisionally (anticipated) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US Patent 11956127.
Limitations of the claim 9 in the instant application 19221575 “receive updated requirements for an existing NoC topology, wherein the updated requirements results in incremental changing initial requirements of the existing NoC topology”, and the limitation in claim 1 in the Patent 11956127 “receive an initial Network-on-Chip (NoC) topology that satisfies and is based on initial requirements, wherein the initial NoC topology includes elements and connections; receive an update to the initial requirements, wherein the update results in updated requirements” have similar subject matters.
Furthermore, Limitations of the claim 9 in the instant application 19221575 “modify a portion of the existing NoC topology in order to satisfy the updated requirements and generate an incremental updated NoC topology from an incremental modification of the existing NoC topology that results in at least one of an unnecessary element and an unnecessary connection”, and the limitation in claim 1 in the Patent 11956127 “make incremental modifications to a portion of the initial NoC topology that is impacted by the updated requirements in order to satisfy the updated requirements and generate an incremental updated NoC topology, each incremental modification is in response to the update and changes existing components in the initial NoC topology, wherein the incremental modifications result in the initial NoC topology being outdated resulting in at least one of an unnecessary element and an unnecessary connection” have similar subject matters.
Furthermore, Limitations of the claim 9 in the instant application 19221575 “remove at least one of the unnecessary element and the unnecessary connection based on the updated requirements;
generate an updated NoC topology that satisfies the updated requirements, output a computer readable format of the updated NoC topology thereby eliminating errors and minimizing delays resulting from changing a portion of the existing NoC topology”, and the limitation in claim 1 in the Patent 11956127 “remove at least one of the unnecessary element and the unnecessary connection, generate a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from topology modifications, wherein minimizing changes includes preserving names of the existing components from the initial NoC topology in the updated NoC topology” have similar subject matters.
Claim 10 is non-provisionally (anticipated) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of US Patent 11956127.
Limitations of the claim 10 in the instant application 19221575 “wherein generation of the updated NoC topology includes causing the design tool to move components of the existing NoC topology to legal locations and minimizing connection lengths that satisfy the updated requirements”, and limitations in claims 7 of US Patent 11956127 “wherein generating the updated NoC topology includes moving the existing components to legal locations, and minimizing connection lengths” have similar subject matter.
Claim 11 is non-provisionally (anticipated) rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of US Patent 11956127.
Limitations of the claim 11 in the instant application 19221575 “wherein generating the updated NoC topology includes updating timing of existing components of the existing NoC topology” and the limitations in claims 8 of US Patent 11956127 “wherein generating the updated NoC topology includes updating timing of existing components” have similar subject matter.
Allowable Subject Matter
Claims 1-11 would be allowable if overcoming the double patenting rejection set forth in this office action.
The following is the reason for allowable subject matter in claim 1, and 9.
With regards to claims 1 and 9, the instant claims require receiving updated requirements for an existing NoC topology, wherein the updated requirements results in incremental changes to initial requirements of the existing NoC topology; modifying a portion of the existing NoC topology in order to satisfy the updated requirements and generate an incremental updated NoC topology from an incremental modification of the existing NoC topology that results in at least one of an unnecessary element and an unnecessary connection; removing at least one of the unnecessary element and the unnecessary connection; generating an updated NoC topology that satisfies the updated requirements; and providing a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from incremental modifications of the existing NoC topology.
Meanwhile, the closest prior arts of record (“Kumar”, US 20150036536 A1) fails to fairly teach or suggest determine the first network on chip topology and mapping based on first conditions, wherein the NOC mapping includes the components and connections, determine a change to the first conditions which requires an update to the first condition, modify gradually a part of the NOC mapping in order to meet the updated conditions and produce a new incremental NOC mapping, the updated gradually mapping is a response to update or changes of existing components in the first mapping, wherein the first mapping is outdated due to unnecessary component and connector and remove that unnecessary component and connector, generate an updated NOC mapping that meets the updated requirements by minimizing the delays and costs resulting from the mapping modification.
For example, (“Kumar”, US 20150036536 A1) teaches receive an initial Network-on-Chip (NoC) topology that satisfies and is based on initial requirements, wherein the initial NoC topology includes elements and connections; receive an update to the initial requirements, wherein the update results in updated requirements; make incremental modifications to a portion of the initial NoC topology that is impacted by the updated requirements in order to satisfy the updated requirements and generate an incremental updated NoC topology, each incremental modification is in response to the update and changes existing components in the initial NoC topology, automatically generate an updated NoC topology that combines the initial NoC topology with the incremental updated NoC topology that satisfies the update; and wherein minimizing changes includes preserving names of the existing components from the initial NoC topology in the updated NoC topology, but does not teach wherein the incremental modifications result in the initial NoC topology being outdated resulting in at least one of an unnecessary element and an unnecessary connection; remove at least one of the unnecessary element and the unnecessary connection and generate a computer readable format of the updated NoC topology thereby minimizing delays and costs resulting from topology modifications.
Thus, no other prior art of record fairly teaches or suggests the instant claim, as a whole.
Conclusion
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/FADI HAJ SAID/Primary Examiner, Art Unit 2444
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