DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The amendment filed on 8/25/2025 has been entered. In the amendment, Applicant cancelled claim 1 and added new claims 2-20. Currently claims 2-20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425). Although the claims at issue are not identical, they are not patentably distinct from each other because
Claim 2 of this application
claim 1 of U.S. Patent No. 11,783,757
2. A display device comprising a pixel, the pixel comprising:
a display element comprising a micro light-emitting diode;
a first transistor comprising an oxide semiconductor in a channel formation region;
a second transistor comprising silicon in a channel formation region; and
a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one terminal of the capacitor, and
wherein one of a source and a drain of the second transistor is electrically connected to the other terminal of the capacitor.
1. A display device comprising a pixel, the pixel comprising:
a display element comprising a micro light-emitting diode;
a first transistor comprising an oxide semiconductor in a channel formation region;
a second transistor comprising silicon in a channel formation region;
a third transistor comprising silicon in a channel formation region; and
a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one terminal of the capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the other terminal of the capacitor, and
wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor and a gate of the third transistor.
As can be seen from the above comparison, claim 1 of U.S. Patent No. 11,783,757 anticipates each feature of claim 2 of this instant application.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425).
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425).
Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425).
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425).
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425). Although the claims at issue are not identical, they are not patentably distinct from each other because
Claim 7 of this application
claim 1 of U.S. Patent No. 11,783,757
7. A display device comprising a pixel, the pixel comprising:
a display element comprising a micro light-emitting diode;
a first transistor comprising a first material in a channel formation region; and
a second transistor comprising a second material in a channel formation region,
wherein the first material is different from the second material.
1. A display device comprising a pixel, the pixel comprising:
a display element comprising a micro light-emitting diode;
a first transistor comprising an oxide semiconductor in a channel formation region;
a second transistor comprising silicon in a channel formation region;
a third transistor comprising silicon in a channel formation region; and
a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one terminal of the capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the other terminal of the capacitor, and
wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor and a gate of the third transistor.
As can be seen from the above comparison, claim 1 of U.S. Patent No. 11,783,757 anticipates each feature of claim 7 of this instant application.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425).
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425).
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425).
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425).
Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425) in view of Vahid Far et al. (US Patent No. 10,395,589).
Regarding claim 12, claim 1 of U.S. Patent No. 11,783,757 teaches the feature “wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor”, but does not teach the feature “wherein the one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor”.
In the same field of endeavor, Vahid Far teaches in Fig. 4 wherein the one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor (Fig. 4: one of a source and a drain of switching transistor 308 is electrically connected to a source and a drain of driver transistor 406A/406B via capacitor 310 at Vdd terminal).
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to combine the technique Vahid Far with the invention of claim 1 of U.S. Patent No. 11,783,757 as an obvious matter of design choice.
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425).
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425) in view of Vahid Far et al. (US Patent No. 10,395,589).
Claim 14 of this instant application
claim 1 of U.S. Patent No. 11,783,757
14. A display device comprising a pixel, the pixel comprising:
a display element comprising a micro light-emitting diode;
a first transistor comprising a first material in a channel formation region; and
a second transistor comprising a second material in a channel formation region,
wherein the first material is different from the second material,
wherein the first transistor is an n-channel transistor, and
wherein the second transistor is a p-channel transistor.
1. A display device comprising a pixel, the pixel comprising:
a display element comprising a micro light-emitting diode;
a first transistor comprising an oxide semiconductor in a channel formation region;
a second transistor comprising silicon in a channel formation region;
a third transistor comprising silicon in a channel formation region; and
a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one terminal of the capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the other terminal of the capacitor, and
wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor and a gate of the third transistor.
As can be seen from the above comparison, claim 1 of U.S. Patent No. 11,783,757 teaches each feature of this instant claim except the following ones
wherein the first transistor is an n-channel transistor, and
wherein the second transistor is a p-channel transistor.
However the features are not new in the related art.
Vahid Far, for instance, teaches in Fig. 4 a pixel circuit
wherein the first transistor is an n-channel transistor (Fig. 4: oxide transistor 308 is an n-channel transistor), and
wherein the second transistor is a p-channel transistor (Fig. 4A: drive transistor 406A is a p-channel transistor; Fig. 4B: driver transistor 406B is a p-channel transistor).
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to combine the technique of Vahid Far with the invention of claim 1 of U.S. Patent No. 11,783,757 to optimize the performance of the pixel circuit by ensuring a low leakage for a low voltage device having higher mobilities.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425) in view of Vahid Far et al. (US Patent No. 10,395,589).
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425) in view of Vahid Far et al. (US Patent No. 10,395,589).
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425) in view of Vahid Far et al. (US Patent No. 10,395,589).
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425) in view of Vahid Far et al. (US Patent No. 10,395,589).
Claim 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425) in view of Vahid Far et al. (US Patent No. 10,395,589) for substantially the same rationale as applied to claim 12..
Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 11,783,757 (resulting from App. 17/562,425) in view of Vahid Far et al. (US Patent No. 10,395,589).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by in view of Vahid Far et al. (US Patent No. 10,395,589).
Regarding claim 2, Vahid Far teaches a display device (Figs. 1, 2) comprising a pixel (Fig. 1: each micro-LED 115 and its corresponding pixel driving circuit form a pixel; Fig. 4: exemplary pixel circuits; Examiner’s Note: as shown in Figs. 4A and 4B, an exemplary pixel includes a hybrid microdriver and a micro-LED, wherein a hybrid microdriver includes a μDriver chiplet circuit 404A/404B fabricated separately on a μDriver substrate and sample/hold circuit 402 that is part of TFT backplane 412 and fabricated directly on a display substrate), the pixel comprising:
a display element comprising a micro light-emitting diode (Fig. 4: each of micro-LEDs 410A, 410B as a display element);
a first transistor (Fig. 2: an oxide transistor in sample/hold circuit located in LTPS/Oxide TFT backplane 212; Fig. 4: oxide transistor 308, which is part of exemplary sample/hold circuit formed of a switching transistor 308 and a storage capacitor 310 on TFT backplane 412; Examiner’s Note: TFT backplane 412 in Fig. 4 is equivalent to TFT backplane 212 in Fig. 2) comprising an oxide semiconductor in a channel formation region (Examiner’s Note: an oxide transistor inherently comprise an oxide semiconductor in a channel formation region);
a second transistor (Fig. 4A: drive transistor 406A in μD chiplet circuit 404A; Fig. 4B: driver transistor 406B in μD chiplet circuit 404B) comprising silicon in a channel formation region (Fig. 4: transistors 406A and 406B use crystalline silicon according to last five lines of column 8); and
a capacitor (Fig. 4: storage capacitor 310),
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and one terminal of the capacitor (Fig. 4: one of a source and a drain of switching transistor 308 is electrically connected to a gate of driver transistor 406A/406B and lower terminal of storage capacitor 310), and
wherein one of a source and a drain of the second transistor is electrically connected to the other terminal of the capacitor (Fig. 4: one of a source and a drain of driver transistor 406A/406B is electrically connected to upper terminal of storage capacitor 310, because both are connected to Vdd).
Regarding claim 3, Vahid Far further teaches the display device according to claim 2, wherein the first transistor is stacked over the second transistor (Figs. 2 and 4: switch transistor 308 is located on TFT backplane 212/412, drive transistor 406A/406B is located on µDriver chiplet equivalent to µIC 110; Examiner’s Note: because µIC 110 and TFT backplane 212 are stacked over each other, switch transistor 308 on TFT backplane 212 and drive transistor 406A/406B on µDriver chiplet equivalent to µIC 110 are also stacked over each other in view of BRI).
Regarding claim 4, Vahid Far further teaches the display device according to claim 2,
wherein the micro light-emitting diode is transferred from a first substrate (Fig. 16: micro LED substrate 1610) to a second substrate (Fig. 16: display substrate 1630),
wherein the first substrate is a carrier substrate provided with the micro light-emitting diode (Fig. 16), and
wherein the second substrate is a transistor substrate provided with the first transistor and the second transistor (Fig. 16; Examiner’s Note: once both micro LED devices and microdriver devices are transferred onto display substrate, display substrate 1630 is a transistor substrate provided with the first transistor and the second transistor).
Regarding claim 5, Vahid Far further teaches the display device according to claim 2, wherein the first transistor and the second transistor are included in a constant current circuit (Fig. 6; Col. 9, ll. 27-30, “A constant current can be used to drive the light emitting elements, where the length in which the current is supplied determines the duty cycle of the light emitting element”; Col. 10, ll. 7-11, “Described herein are several analog hybrid microdriver circuit designs and associated output waveforms. Each design provides for constant current driving of a light-emitting device using pulse width modulation”; Examiner’s Note; both first transistor and second transistor interpreted in claim 1 are used for providing a constant current; therefore, it is justified that they are included in a constant current circuit).
Regarding claim 6, Vahid Far further teaches an electronic device (Abstract: “apparatuses for controlling an emission of the light emitting devices”) comprising the display device according to claim 2.
Regarding claim 7, Vahid Far teaches a display device (Figs. 1, 2) comprising a pixel (Fig. 1: each micro-LED 115 and its corresponding pixel driving circuit form a pixel; Fig. 4: exemplary pixel circuits; Examiner’s Note: as shown in Figs. 4A and 4B, an exemplary pixel includes a hybrid microdriver and a micro-LED, wherein a hybrid microdriver includes a μDriver chiplet circuit 404A/404B fabricated separately on a μDriver substrate and sample/hold circuit 402 that is part of TFT backplane 412 and fabricated directly on a display substrate), the pixel comprising:
a display element comprising a micro light-emitting diode (Fig. 4: each of micro-LEDs 410A, 410B as a display element);
a first transistor (Fig. 2: oxide transistor in sample/hold circuit located in LTPS/Oxide TFT backplane 212; Fig. 4: oxide transistor 308, which is part of exemplary sample/hold circuit formed of a switching transistor 308 and a storage capacitor 310 on TFT backplane 412; Examiner’s Note: TFT backplane 412 in Fig. 4 is equivalent to TFT backplane 212 in Fig. 2) comprising a first material in a channel formation region (Examiner’s Note: an oxide transistor inherently comprise an oxide semiconductor as a first material in a channel formation region); and
a second transistor (Fig. 4A: drive transistor 406A in μD chiplet circuit 404A; Fig. 4B: driver transistor 406B in μD chiplet circuit 404B) comprising a second material in a channel formation region (Fig. 4: transistors 406A and 406B use crystalline silicon as a second material according to last five lines of column 8),
wherein the first material is different from the second material (oxide semiconductor is different from crystalline silicon).
Regarding claim 8, Vahid Far further teaches the display device according to claim 7,
wherein the first material is an oxide semiconductor (see claim 7), and
wherein the second material is silicon (see claim 7).
Claim 9 is rejected for the same rationale as applied to claim 3.
Claim 10 is rejected for the same rationale as applied to claim 4.
Claim 11 is rejected for the same rationale as applied to claim 5.
Regarding claim 12, Vahid Far further teaches the display device according to claim 7,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor (Fig. 4: one of a source and a drain of switching transistor 308 is electrically connected to a gate of driver transistor 406A/406B and lower terminal of storage capacitor 310), and
wherein the one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor (Fig. 4: one of a source and a drain of switching transistor 308 is electrically connected to a source and a drain of driver transistor 406A/406B via capacitor 310 at Vdd terminal).
Regarding claim 13, Vahid Far further teaches an electronic device (Abstract: “apparatuses for controlling an emission of the light emitting devices”) comprising the display device according to claim 7.
Regarding claim 14, Vahid Far teaches a display device (Figs. 1, 2) comprising a pixel (Fig. 1: each micro-LED 115 and its corresponding pixel driving circuit form a pixel; Fig. 4: exemplary pixel circuits; Examiner’s Note: as shown in Figs. 4A and 4B, an exemplary pixel includes a hybrid microdriver and a micro-LED, wherein a hybrid microdriver includes a μDriver chiplet circuit 404A/404B fabricated separately on a μDriver substrate and sample/hold circuit 402 that is part of TFT backplane 412 and fabricated directly on a display substrate), the pixel comprising:
a display element comprising a micro light-emitting diode (Fig. 4: each of micro-LEDs 410A, 410B as a display element);
a first transistor (Fig. 2: oxide transistor in sample/hold circuit located in LTPS/Oxide TFT backplane 212; Fig. 4: oxide transistor 308, which is part of exemplary sample/hold circuit formed of a switching transistor 308 and a storage capacitor 310 on TFT backplane 412; Examiner’s Note: TFT backplane 412 in Fig. 4 is equivalent to TFT backplane 212 in Fig. 2) comprising a first material in a channel formation region (Examiner’s Note: an oxide transistor inherently comprise an oxide semiconductor as a first material in a channel formation region); and
a second transistor (Fig. 4A: drive transistor 406A in μD chiplet circuit 404A; Fig. 4B: driver transistor 406B in μD chiplet circuit 404B) comprising a second material in a channel formation region (Fig. 4: transistors 406A and 406B use crystalline silicon as a second material according to last five lines of column 8),
wherein the first material is different from the second material (oxide semiconductor is different from crystalline silicon),
wherein the first transistor is an n-channel transistor (Fig. 4: oxide transistor 308 is an n-channel trasistor), and
wherein the second transistor is a p-channel transistor (Fig. 4A: drive transistor 406A is a p-channel transistor; Fig. 4B: driver transistor 406B is a p-channel transistor).
Regarding claim 15, Vahid Far further teaches the display device according to claim 14,
wherein the first material is an oxide semiconductor (see claim 7), and
wherein the second material is silicon (see claim 7).
Regarding claim 16, Vahid Far further teaches the display device according to claim 14, wherein the first transistor is stacked over the second transistor (Figs. 2 and 4: switch transistor 308 is located on TFT backplane 212/412, drive transistor 406A/406B is located on µDriver chiplet equivalent to µIC 110; Examiner’s Note: because µIC 110 and TFT backplane 212 are stacked over each other, switch transistor 308 on TFT backplane 212 and drive transistor 406A/406B on µDriver chiplet equivalent to µIC 110 are also stacked over each other in view of BRI).
Regarding claim 17, Vahid Far further teaches the display device according to claim 14,
wherein the micro light-emitting diode is transferred from a first substrate (Fig. 16: micro LED substrate 1610) to a second substrate (Fig. 16: display substrate 1630),
wherein the first substrate is a carrier substrate provided with the micro light-emitting diode (Fig. 16), and
wherein the second substrate is a transistor substrate provided with the first transistor and the second transistor (Fig. 16; Examiner’s Note: once both micro LED devices and microdriver devices are transferred onto display substrate, display substrate 1630 is a transistor substrate provided with the first transistor and the second transistor).
Regarding claim 18, Vahid Far further teaches the display device according to claim 14, wherein the first transistor and the second transistor are included in a constant current circuit (Fig. 6; Col. 9, ll. 27-30, “A constant current can be used to drive the light emitting elements, where the length in which the current is supplied determines the duty cycle of the light emitting element”; Col. 10, ll. 7-11, “Described herein are several analog hybrid microdriver circuit designs and associated output waveforms. Each design provides for constant current driving of a light-emitting device using pulse width modulation”; Examiner’s Note; both first transistor and second transistor interpreted in claim 1 are used for providing a constant current; therefore, it is justified that they are included in a constant current circuit).
Regarding claim 19, Vahid Far further teaches the display device according to claim 14,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor (Fig. 4: one of a source and a drain of switching transistor 308 is electrically connected to a gate of driver transistor 406A/406B and lower terminal of storage capacitor 310), and
wherein the one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor (Fig. 4: one of a source and a drain of switching transistor 308 is electrically connected to a source and a drain of driver transistor 406A/406B via capacitor 310 at Vdd terminal).
Regarding claim 20, Vahid Far further teaches an electronic device (Abstract: “apparatuses for controlling an emission of the light emitting devices”) comprising the display device according to claim 14.
Response to Latest Submission
Applicant’s submission on 3/26/2026 has been considered. The amended claims 2-20 on 8/25/2026 are entered.
Conclusion
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/XUEMEI ZHENG/Primary Examiner, Art Unit 2629
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