DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the instant application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/02/2025 is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “the first thin-film transistor comprises a first semiconductor layer having a first area in a plan view, the second thin-film transistor comprises a second semiconductor layer having a second area in the plan view, and the first area is less than the second area” (claims 15 and 19) and “wherein the first thin-film transistor comprises a first semiconductor layer comprising a first active area, the second thin-film transistor comprises a second semiconductor layer comprising a second active area, and a first width of the first active area is less than a second width of the second active area” (claim 16) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-16 and 19 are objected to because of the following informalities:
Claim 1, line 10, recites “the gate electrode”. To correct antecedent issues, examiner suggest “a gate electrode”.
Claim 3, line 2, recites “a gate electrode of the first thin-film transistor”. Since the term previously appears in claim 1, examiner suggest “the gate electrode of the first thin-film transistor”.
Claim 3, lines 2-3, recites “a gate electrode of the second thin-film transistor”. Since the term previously appears in claim 1, examiner suggest “the gate electrode of the second thin-film transistor”.
Claim 10, line 2, recites “a gate electrode of the first thin-film transistor”. Since the term previously appears in claim 1, examiner suggest “the gate electrode of the first thin-film transistor”.
Claim 10, lines 2-3, recites “a gate electrode of the second thin-film transistor”. Since the term previously appears in claim 1, examiner suggest “the gate electrode of the second thin-film transistor”.
Claim 10, lines 1-4, recites “the scan driver further comprises a node electrically connecting a gate electrode of the first thin-film transistor to a gate electrode of the second thin-film transistor which corresponds to the gate electrode of the second thin-film transistor”. To clarify the claim language and to correct antecedent issues, examiner suggests “the scan driver further comprises a node electrically connecting the gate electrode of the first thin-film transistor to the gate electrode of the second thin-film transistor”.
Claim 11, recites “the third high-level section has a voltage higher than the first high-level section”. To clarify the claim language, examiner suggest “the third high-level section has a voltage higher than a voltage of the first high-level section”.
Claim 13, lines 2-3, recites “the second fall section and has a voltage lower than the third high-level section”. To clarify the claim language, examiner suggests “the second fall section and has a voltage lower than the voltage of the third high-level section”.
Claim 19, line 3, recites “in the plan view”. To correct antecedent issues, examiner suggest “in plan view”.
Claim 19, line 9, recites “terminal,;”. Examiner suggest ”terminal;” to correct punctuation issues.
Claim 19, line 10, recites “terminal,;”. Examiner suggest ”terminal;” to correct punctuation issues.
Claim 19, line 12, recites “terminal,;”. Examiner suggest ”terminal;” to correct punctuation issues.
Claim 19, line 15, recites “electrode,;”. Examiner suggest ”electrode;” to correct punctuation issues.
Claim 19, line 16, recites “the gate electrode”. To correct antecedent issues, examiner suggest “a gate electrode”.
Claim 19, line 22, recites “a the gate electrode”. To correct grammatical issues, examiner suggest “the gate electrode”.
Claim 19, line 27, recites “athe source electrode”. To correct grammatical issues, examiner suggest “the source electrode”.
Claims 2, 4-9, 12, and 14-16 depend directly or indirectly from an objected claim therefore are also objected.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “wherein another electrode of the bootstrap capacitor is electrically connected to a drain electrode of the second thin-film transistor and the second output terminal”. However, claim 1 recites “a bootstrap capacitor electrically connected to the gate electrode of the first thin-film transistor and the first output terminal”. It is unclear how the bootstrap capacitor can be connected to the first output terminal and the first thing film transistor and at the same time to the second output terminal and the second thing-film transistor. Based on applicants’ disclosure “another electrode of the bootstrap capacitor is electrically connected to a drain electrode of the first thin-film transistor and the first output terminal” (see Fig. 5, BC1). Claim 5 is going to be examined as best understood by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20230169926 A1, hereinafter referenced as Kim) in view of Seo et al. (US 20230186825 A1, hereinafter referenced as Seo).
Regarding Claim 1, Kim teaches a display apparatus (see Fig. 1, display apparatus 10, para. [0051]-[0052]) comprising:
an organic light-emitting diode (see Fig. 2, para. [0065]. Referring to FIG. 2, each pixel PX may include a pixel circuit PC and an organic light-emitting diode OLED connected to the pixel circuit PC as a display element);
a scan driver (see Fig. 1, scan driver 130, Fig. 4, Fig. 6) comprising:
a first output terminal (see Fig. 6, a first output terminal OUT1);
a second output terminal (see Fig. 6, second output terminal OUT2);
a first thin-film transistor electrically connected to the first output terminal (see Fig. 6, and para. [0106]. The fourth transistor T4 may be connected between the first clock input terminal CLK1 and the first output terminal OUT1);
a second thin-film transistor electrically connected to the second output terminal (see Fig. 6 and para. [0110] The sixth transistor T6 may be connected between the second clock input terminal CLK2 and the second output terminal OUT2) and comprising:
a gate electrode (see Fig. 6, and para. [0110]. A gate of the sixth transistor T6 may be connected to the first control node Q); and
a bootstrap capacitor electrically connected to the gate electrode of the first thin-film transistor and the first output terminal (see Fig. 1, first capacitor C1, para. [0108]. The first capacitor C1 may be connected between the first output node N1 and the first control node Q. The fourth transistor T4 may be turned on when the first control node is charged to have a high voltage, the first clock signal SC_CK having a high voltage is output as a high voltage of the first scan signal SC, and in this case, the voltage of the first control node Q may be bootstrapped by the first capacitor C1);
a driving thin-film transistor (see Figs. 2-3, T1, para. [0065]. The pixel circuit PC includes a first transistor (T1, a driving transistor).) electrically connected to the organic light-emitting diode (see Figs. 2-3, T1, para. [0065]-[0066]. The first transistor T1 may control a driving current flowing in the organic light-emitting diode OLED from the driving power line PL, according to a voltage stored in the capacitor Cst) and comprising:
a gate electrode (see Figs. 2-3, T1, para. [0066]. A gate electrode of the first transistor T1 may be connected to a first node Na); and
a source electrode (see Figs. 2-3, T1, para. [0066]. The first transistor T1 may include a first electrode connected to a driving power line PL configured to provide a driving voltage ELVDD);
a switching thin-film transistor (see Figs. 2-3, T2, para. [0065]. a second transistor (T2, a switching transistor)) electrically connected to the gate electrode of the driving thin-film transistor (see Fig. 2, T2, para. [0066]-[0067]. The second transistor T2 may include a gate electrode connected to a first scan line SCL, a first electrode connected to the data line DL, and a second electrode connected to the first node Na. A gate electrode of the first transistor T1 may be connected to a first node Na) and comprising:
a switching gate electrode electrically connected to the first output terminal (see Figs. 2-3, T2, first scan line SCL, Fig. 6, OUT1 outputs first scan signal SC, para. [0067], para. [0106]-[0107]. The second transistor T2 may be turned on in response to a first scan signal SC input through the first scan line SCL); and
an initialization thin-film transistor (see Figs. 2-3, third transistor T3, para. [0068], para. [0075]. The third transistor T3 may include a gate electrode connected to a second scan line SSL, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the sensing line SL. The first switching device SW1 may be connected between the sensing line SL and an initialization voltage source. The first switching device SW1 may be turned on in response to a first control signal S1 provided from the controller 160 and may provide an initialization voltage Vint from the initialization voltage source to the sensing line SL) electrically connected to the organic light-emitting diode and the source electrode of the driving thin-film transistor (see Figs. 2-3, T3, para. [0068]. As depicted in Figures 2-3, a first electrode of the third transistor T3 is connected to OLED and the second electrode of the first transistor) and comprising:
an initialization gate electrode electrically connected to the second output terminal (see Figs. 2-3, second scan line SSL, Fig. 6, OUT 2 outputs second scan signal SS para. [0068], para. [0110]-[011]. [0068] The third transistor T3 may include a gate electrode connected to a second scan line SSL. The third transistor T3 may be turned on in response to a second scan signal SS provided through the second scan line SSL),
Kim does not explicitly disclose wherein the gate electrode of the second thin-film transistor and the second output terminal are not electrically connected to each other.
However, Seo teaches wherein the gate electrode of the second thin-film transistor and the second output terminal are not electrically connected to each other (see Fig. 5, Fig. 7, second scan pull-up transistor Tu2, para. [0122]-[0123], para. [0132]. As depicted in figure 7 the first scan pull-up transistor has a boosting capacitor Cb1 electrically connecting the gate electrode of the first pull-up transistor Tu1 with the second terminal of the first pull-up transistor Tu1. However, the second pull-up transistor Tu2 does not have a boosting capacitor, therefore the gate electrode of the second pull-up transistor Tu2 is not electrically connected to the second terminal of the second pull-up transistor Tu2).
Kim and Seo and scan driving circuits and display, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the scan driver disclosed by Kim with Seo’s teachings of having the gate electrode of the second thin-film transistor and the second output terminal not electrically connected to each other, since it would have aided in reducing the size of the gate driving circuit GD, and thus to realize the narrow bezel with easiness (Seo para. [0132]).
Regarding Claim 2, Kim and Seo teach the display apparatus of claim 1.
Kim further teaches wherein the first output terminal outputs a first signal for turning on or off the switching thin-film transistor (see Figs. 2-3, T2, first scan line SCL, Fig. 6, OUT1 outputs first scan signal SC, para. [0067], para. [0106]-[0107]. The second transistor T2 may be turned on in response to a first scan signal SC input through the first scan line SCL), and the second output terminal outputs a second signal for turning on or off the initialization thin-film transistor (see Figs. 2-3, second scan line SSL, Fig. 6, OUT 2 outputs second scan signal SS para. [0068], para. [0110]-[011]. [0068] The third transistor T3 may include a gate electrode connected to a second scan line SSL. The third transistor T3 may be turned on in response to a second scan signal SS provided through the second scan line SSL).
Regarding Claim 3, Kim and Seo teach the display apparatus of claim 1,
Kim further teaches wherein the scan driver further comprises a node (see Fig. 6, First control node Q) electrically connecting a gate electrode of the first thin-film transistor to a gate electrode of the second thin-film transistor (see Fig. 6, para. [0106]-[0110]. A gate of the fourth transistor T4 may be connected to the first control node Q. The fourth transistor T4 may be a first pull-up transistor. The fourth transistor T4 may be turned on when the first control node Q is set to have a high voltage and may output the first clock signal SC_CK having a high voltage as a high voltage of the first scan signal SC. A gate of the sixth transistor T6 may be connected to the first control node Q. The sixth transistor T6 may be turned on or off according to the voltage of the first control node Q. The sixth transistor T6 may be a second pull-up transistor. The sixth transistor T6 may be turned on when the first control node Q is set to have a high voltage and may output the second clock signal SS_CK having a high voltage as a high voltage of the second scan signal SS).
Regarding Claim 4, Kim and Seo teach the display apparatus of claim 3.
Kim further teaches wherein the node is electrically connected to an electrode of the bootstrap capacitor (see Fig. 1, first capacitor C1, para. [0108]. The first capacitor C1 may be connected between the first output node N1 and the first control node Q. The fourth transistor T4 may be turned on when the first control node is charged to have a high voltage, the first clock signal SC_CK having a high voltage is output as a high voltage of the first scan signal SC, and in this case, the voltage of the first control node Q may be bootstrapped by the first capacitor C1).
Regarding Claim 5, Kim and Seo teach the display apparatus of claim 4.
Kim further teaches wherein another electrode of the bootstrap capacitor is electrically connected to a drain electrode of the second thin-film transistor and the second output terminal (see Fig. 6, C1. As depicted in figure 6 the first capacitor is connected to the second electrode of the fourth transistor T4 and the first output terminal OUT1).
Regarding Claim 6, Kim and Seo teach the display apparatus of claim 2,
Kim further teaches wherein the first signal (see Fig. 6, OUT 1 outputs first scan signal SC, Fig. 7A, SC_C Fig. 7B, first scan signal SC, para. [0127]) comprises a first rise section (see Figs. 7A-7B, para. [0120], para. [0127]. A pulse of the first clock signal SC_CK may have a first falling time TF1. As illustrated in FIG. 7B, waveforms of the first scan signal SC may be identical to those of the first clock signal SC_CK. As depicted in annotated Fig. 7B the first scan signal has a first rise time from t1-t2), a first maintain section after the first rise section (see Figs. 7A-7B, para. [0120], para. [0127]. A pulse of the first clock signal SC_CK may have a first on time TO1. As illustrated in FIG. 7B, waveforms of the first scan signal SC may be identical to those of the first clock signal. As depicted in annotated Fig. 7B the first scan signa SC has a maintain section from t2-t3), and a first fall section after the first maintain section (see Figs. 7A-7B, para. [0120], para. [0127]. A pulse of the first clock signal SC_CK may have a first falling time TF1,. As illustrated in FIG. 7B, waveforms of the first scan signal SC may be identical to those of the first clock signal SC_CK. As depicted in annotated Fig. 7B the first scan signa SC has a first falling section from t3-t4) , and
the second signal comprises a second rise section (see Figs. 7A-7B, para. [0120], para. [0127. A pulse of the second clock signal SS_CK may have a second rising time TR2. As illustrated in FIG. 7B, waveforms of the second scan signal SS may be identical to those of the second clock signal SS_CK. As depicted in annotated Fig. 7B the second scan signal SS has a second rise section from t1-t2), a second maintain section after the second rise section (see Figs. 7A-7B, para. [0120], para. [0127. A pulse of the second clock signal SS_CK may have a second pulse width TW2 of a second rising time TR2, a second falling time TF2, and a second on time TO2. As illustrated in FIG. 7B, waveforms of the second scan signal SS may be identical to those of the second clock signal SS_CK. As depicted in annotated Fig. 7B the second scan signal SS has a maintain section from t2-t3), and a second fall section after the second maintain section (see Figs. 7A-7B, para. [0120], para. [0127. A pulse of the second clock signal SS_CK may have a second pulse width TW2 of a second rising time TR2, a second falling time TF2, and a second on time TO2. As illustrated in FIG. 7B, waveforms of the second scan signal SS may be identical to those of the second clock signal SS_CK. As depicted in annotated Fig. 7B the second scan signal SS has second fall section from t3-t5).
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Regarding Claim 7, Kim and Seo teach the display apparatus of claim 6.
Kim further teaches wherein the first rise section and the second rise section start simultaneously with each other (see annotated Fig. 7B above. As depicted in annotated Fig. 7B the first rise section of the first scan signa SC starts simultaneously with the second rise section of the second scan signal SS at time t1).
Regarding Claim 17, Kim teaches a display apparatus (see Fig. 1, display apparatus 10, para. [0051]-[0052]) comprising:
an organic light-emitting diode (see Fig. 2, para. [0065]. Referring to FIG. 2, each pixel PX may include a pixel circuit PC and an organic light-emitting diode OLED connected to the pixel circuit PC as a display element);
a scan driver (see Fig. 1, scan driver 130, Fig. 4, Fig. 6) comprising:
a first output terminal (see Fig. 6, a first output terminal OUT1);
a second output terminal (see Fig. 6, second output terminal OUT2);
a first thin-film transistor electrically connected to the first output terminal (see Fig. 6, and para. [0106]. The fourth transistor T4 may be connected between the first clock input terminal CLK1 and the first output terminal OUT1) and comprising:
a gate electrode (see Fig. 4, T4, para. [0106]. A gate of the fourth transistor T4 may be connected to the first control node Q);
a second thin-film transistor electrically connected to the second output terminal (see Fig. 6 and para. [0110] The sixth transistor T6 may be connected between the second clock input terminal CLK2 and the second output terminal OUT2) and comprising:
a gate electrode (see Fig. 6, and para. [0110]. A gate of the sixth transistor T6 may be connected to the first control node Q); and
a first bootstrap capacitor electrically connected to the gate electrode of the first thin-film transistor and the first output terminal (see Fig. 1, first capacitor C1, para. [0108]. The first capacitor C1 may be connected between the first output node N1 and the first control node Q. The fourth transistor T4 may be turned on when the first control node is charged to have a high voltage, the first clock signal SC_CK having a high voltage is output as a high voltage of the first scan signal SC, and in this case, the voltage of the first control node Q may be bootstrapped by the first capacitor C1);
a driving thin-film transistor (see Figs. 2-3, T1, para. [0065]. The pixel circuit PC includes a first transistor (T1, a driving transistor)) electrically connected to the organic light-emitting diode (see Figs. 2-3, T1, para. [0065]-[0066]. The first transistor T1 may control a driving current flowing in the organic light-emitting diode OLED from the driving power line PL, according to a voltage stored in the capacitor Cst) and comprising:
a source electrode (see Figs. 2-3, T1, para. [0066]. The first transistor T1 may include a first electrode connected to a driving power line PL configured to provide a driving voltage ELVDD);
a switching thin-film transistor (see Figs. 2-3, T2, para. [0065]. a second transistor (T2, a switching transistor)) electrically connected to a gate electrode of the driving thin-film transistor (see Fig. 2, T2, para. [0066]-[0067]. The second transistor T2 may include a gate electrode connected to a first scan line SCL, a first electrode connected to the data line DL, and a second electrode connected to the first node Na. A gate electrode of the first transistor T1 may be connected to a first node Na) and comprising:
a switching gate electrode electrically connected to the first output terminal (see Figs. 2-3, T2, first scan line SCL, Fig. 6, OUT1 outputs first scan signal SC, para. [0067], para. [0106]-[0107]. The second transistor T2 may be turned on in response to a first scan signal SC input through the first scan line SCL); and
an initialization thin-film transistor (see Figs. 2-3, third transistor T3, para. [0068], para. [0075]. The third transistor T3 may include a gate electrode connected to a second scan line SSL, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the sensing line SL. The first switching device SW1 may be connected between the sensing line SL and an initialization voltage source. The first switching device SW1 may be turned on in response to a first control signal S1 provided from the controller 160 and may provide an initialization voltage Vint from the initialization voltage source to the sensing line SL) electrically connected to the organic light-emitting diode and the source electrode of the driving thin-film transistor (see Figs. 2-3, T3, para. [0068]. As depicted in Figures 2-3, a first electrode of the third transistor T3 is connected to OLED and the second electrode of the first transistor) and comprising:
an initialization gate electrode electrically connected to the second output terminal (see Figs. 2-3, second scan line SSL, Fig. 6, OUT 2 outputs second scan signal SS para. [0068], para. [0110]-[011]. [0068] The third transistor T3 may include a gate electrode connected to a second scan line SSL. The third transistor T3 may be turned on in response to a second scan signal SS provided through the second scan line SSL).
Kim does not explicitly disclose the scan driver non-including a second bootstrap capacitor electrically connected between the gate electrode of the second thin-film transistor and the second output terminal.
However, Seo teaches the scan driver non-including a second bootstrap capacitor electrically connected between the gate electrode of the second thin-film transistor and the second output terminal (see Fig. 5, Fig. 7, second scan pull-up transistor Tu2, para. [0122]-[0123], para. [0132]. As depicted in figure 5 the second scan pull-up transistor Tu2 has a boosting capacitor C2 electrically connecting the gate electrode of the second pull-up transistor Tu2 with the second terminal of thesecond pull-up transistor Tu2. However, as depicted in figure 7 the second pull-up transistor Tu2 does not have a boosting capacitor, therefore the gate electrode of the second pull-up transistor Tu2 is not electrically connected to the second terminal of the second pull-up transistor Tu2).
Kim and Seo and scan driving circuits and display, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the scan driver disclosed by Kim with Seo’s teachings of having the gate electrode of the second thin-film transistor and the second output terminal not electrically connected to each other, since it would have aided in reducing the size of the gate driving circuit GD, and thus to realize the narrow bezel with easiness (Seo para. [0132]).
Regarding Claim 18, Kim and Seo teach the display apparatus of claim 17.
Seo further teaches wherein a capacity of the first bootstrap capacitor is greater than a capacity of the second bootstrap capacitor, and wherein the capacity of the first bootstrap capacitor is twice the capacity of the second bootstrap capacitor (see para. [0115]. The first boosting capacitor Cb1 may have a larger capacitance than the second boosting capacitor Cb2. For example, the first boosting capacitor Cb1 may have a capacitance greater than that of the second boosting capacitor Cb2 and may have a capacitance equal to or less than twice the capacitance of the second boosting capacitor Cb2. For example, the first boosting capacitor Cb1 may be set to 5 pF, and the second boosting capacitor Cb2 may be set to 2.5 pF).
Kim and Seo and scan driving circuits and display, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the scan driver disclosed by Kim and Seo with Seo’s teachings of providing the capacity of the first bootstrap capacitor to be twice the capacity of the second bootstrap capacitor, since it would have provided a first boosting capacitor Cb1 that is set to have sufficient capacitance to increase the bootstrapping time of the first node Q in order to improve the rising time of the (n)th scan signal SC[n] which is firstly output from the scan output circuit (Seo para. [0120]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20230169926 A1, hereinafter referenced as Kim) in view of Seo et al. (US 20230186825 A1, hereinafter referenced as Seo), further in view of Kim et al. (US 20240161701 A1, hereinafter referenced as Kim-701).
Regarding Claim 20, Kim teaches an apparatus (see Fig. 1, The display apparatus 10) comprising:
a memory which stores data information (see para. [0058]. The controller 160 may control the operations of the scan driver 130, the sensor 140, and the data driver 150. Also, the controller 160 may store, in a memory, sensing data from the sensor 140, compensate for data that is input from the outside by using the stored sensing data, and output the compensated data DATA to the data driver 150);
a “controller” which generates data signals and/or control signals based on the data information (see Fig. 1, controller 170, first control signal CON1, third control signal CON3, para. [0053]-[0055], para. [0058]. The scan driver 130 may be connected to scan lines SCL and SSL, generate scan signals in response to a first control signal CONT1 from the controller 160, and thus sequentially provide the scan signals to the scan lines SCL and SSL. The data driver 150 may be connected to a plurality of data lines DL and provide data signals to the data lines DL during the data period, in response to a third control signal CONT3 from the controller 160. The controller 160 may control the operations of the scan driver 130, the sensor 140, and the data driver 150. Also, the controller 160 may store, in a memory, sensing data from the sensor 140, compensate for data that is input from the outside by using the stored sensing data, and output the compensated data DATA to the data driver 150. According to some embodiments, the data DATA and the sensing data may be digital signals); and
a display apparatus which operates based on the data signals and/or the control signals (see Fig. 1, para. [0058], para. [0061] The display apparatus 10 may include the display panel, and the display panel may include a substrate. The controller 160 may control the operations of the scan driver 130, the sensor 140, and the data driver 150. Also, the controller 160 may store, in a memory, sensing data from the sensor 140, compensate for data that is input from the outside by using the stored sensing data, and output the compensated data DATA to the data driver 150. According to some embodiments, the data DATA and the sensing data may be digital signals), wherein the display apparatus comprising:
an organic light-emitting diode (see Fig. 2, para. [0065]. Referring to FIG. 2, each pixel PX may include a pixel circuit PC and an organic light-emitting diode OLED connected to the pixel circuit PC as a display element);
a scan driver (see Fig. 1, scan driver 130, Fig. 4, Fig. 6) comprising:
a first output terminal (see Fig. 6, a first output terminal OUT1),;
a second output terminal (see Fig. 6, second output terminal OUT2),;
a first thin-film transistor electrically connected to the first output terminal (see Fig. 6, and para. [0106]. The fourth transistor T4 may be connected between the first clock input terminal CLK1 and the first output terminal OUT1),;
a second thin-film transistor electrically connected to the second output terminal (see Fig. 6 and para. [0110] The sixth transistor T6 may be connected between the second clock input terminal CLK2 and the second output terminal OUT2) and comprising:
a gate electrode (see Fig. 6, and para. [0110]. A gate of the sixth transistor T6 may be connected to the first control node Q),; and
a bootstrap capacitor electrically connected to a the gate electrode of the first thin-film transistor and the first output terminal (see Fig. 1, first capacitor C1, para. [0108]. The first capacitor C1 may be connected between the first output node N1 and the first control node Q. The fourth transistor T4 may be turned on when the first control node is charged to have a high voltage, the first clock signal SC_CK having a high voltage is output as a high voltage of the first scan signal SC, and in this case, the voltage of the first control node Q may be bootstrapped by the first capacitor C1);
a driving thin-film transistor (see Figs. 2-3, T1, para. [0065]. The pixel circuit PC includes a first transistor (T1, a driving transistor)) electrically connected to the organic light-emitting diode (see Figs. 2-3, T1, para. [0065]-[0066]. The first transistor T1 may control a driving current flowing in the organic light-emitting diode OLED from the driving power line PL, according to a voltage stored in the capacitor Cst) and comprising:
a gate electrode (see Figs. 2-3, T1, para. [0066]. A gate electrode of the first transistor T1 may be connected to a first node Na); and
a source electrode (see Figs. 2-3, T1, para. [0066]. The first transistor T1 may include a first electrode connected to a driving power line PL configured to provide a driving voltage ELVDD);
a switching thin-film transistor (see Figs. 2-3, T2, para. [0065]. a second transistor (T2, a switching transistor)) electrically connected to a the gate electrode of the driving thin-film transistor (see Fig. 2, T2, para. [0066]-[0067]. The second transistor T2 may include a gate electrode connected to a first scan line SCL, a first electrode connected to the data line DL, and a second electrode connected to the first node Na. A gate electrode of the first transistor T1 may be connected to a first node Na) and comprising:
a switching gate electrode electrically connected to the first output terminal (see Figs. 2-3, T2, first scan line SCL, Fig. 6, OUT1 outputs first scan signal SC, para. [0067], para. [0106]-[0107]. The second transistor T2 may be turned on in response to a first scan signal SC input through the first scan line SCL); and
an initialization thin-film transistor (see Figs. 2-3, third transistor T3, para. [0068], para. [0075]. The third transistor T3 may include a gate electrode connected to a second scan line SSL, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the sensing line SL. The first switching device SW1 may be connected between the sensing line SL and an initialization voltage source. The first switching device SW1 may be turned on in response to a first control signal S1 provided from the controller 160 and may provide an initialization voltage Vint from the initialization voltage source to the sensing line SL) electrically connected to the organic light- emitting diode and athe source electrode of the driving thin-film transistor (see Figs. 2-3, T3, para. 90068]. As depicted in Figures 2-3, a first electrode of the third transistor T3 is connected to OLED and the second electrode of the first transistor) and comprising:
an initialization gate electrode electrically connected to the second output terminal (see Figs. 2-3, second scan line SSL, Fig. 6, OUT 2 outputs second scan signal SS para. [0068], para. [0110]-[011]. [0068] The third transistor T3 may include a gate electrode connected to a second scan line SSL. The third transistor T3 may be turned on in response to a second scan signal SS provided through the second scan line SSL),
Kim does not explicitly disclose the “apparatus” is an electronic apparatus and the “controller” is a processor; wherein the gate electrode of the second thin-film transistor and the second output terminal are not electrically connected to each other.
However, Seo teaches wherein the gate electrode of the second thin-film transistor and the second output terminal are not electrically connected to each other (see Fig. 5, Fig. 7, second scan pull-up transistor Tu2, para. [0122]-[0123], para. [0132]. As depicted in figure 7 the first scan pull-up transistor has a boosting capacitor Cb1 electrically connecting the gate electrode of the first pull-up transistor Tu1 with the second terminal of the first pull-up transistor Tu1. However, the second pull-up transistor Tu2 does not have a boosting capacitor, therefore the gate electrode of the second pull-up transistor Tu2 is not electrically connected to the second terminal of the second pull-up transistor Tu2).
Kim and Seo and scan driving circuits and display, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the scan driver disclosed by Kim with Seo’s teachings of having the gate electrode of the second thin-film transistor and the second output terminal not electrically connected to each other, since it would have aided in reducing the size of the gate driving circuit GD, and thus to realize the narrow bezel with easiness (Seo para. [0132]).
Kim and Seo do not explicitly disclose the “apparatus” is an electronic apparatus and the “controller” is a processor.
However, Kim-701 teaches the “apparatus” is an electronic apparatus (see Figs. 16-17, para. [0187]-[0188], para. [0195]. The electronic device 1000) comprising a “controller” that is a processor (see Fig. 16, processor 1010, para. [0189]-[0190]. The electronic device 1000 may include a processor 1010. The processor 1010 may perform various computing functions).
Kim, Seo and Kim-701 are related to display devices, thus one of ordinary skill in the art, before the effective filing date of the claimed invention, would have recognized the obviousness of modifying the display device disclosed by Kim and Seo to be included in an electronic apparatus in which a controller is a processor, since it would have been obvious to try from a finite number of options electronic options know in the art that would have yield the same predictable results of displaying.
Allowable Subject Matter
Claims 8-16 and 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi et al. - US 20200184898 A1- Shift register comprising a first output terminal (SS(k));a second output terminal (SC(k));a first thin-film transistor electrically connected to the first output terminal (T20);a second thin-film transistor electrically connected to the second output terminal (T18); and a bootstrap capacitor electrically connected to a gate electrode of the first thin-film transistor and the first output terminal (C4); and wherein the gate electrode of the second thin-film transistor and the second output terminal are not electrically connected to each other (T18). A pixel circuit comprising a driving thin-film transistor electrically connected to and organic light-emitting diode (M1); a switching thin-film transistor electrically connected to a gate electrode of the driving thin-film transistor (M2) wherein a switching gate electrode of the switching thin-film transistor is electrically connected to the second output terminal (M2 and SCi); and an initialization thin-film transistor electrically connected to the organic light-emitting diode and a source electrode of the driving thin-film transistor (M3); wherein an initialization gate electrode of the initialization thin-film transistor is electrically connected to the first output terminal (M3 and SSi).
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Feng et al. - US 20210201753 A1 - Shift register comprising a first output terminal (OP_2);a second output terminal (OP_3);a first thin-film transistor electrically connected to the first output terminal (T3);a second thin-film transistor electrically connected to the second output terminal (T4); and a bootstrap capacitor electrically connected to a gate electrode of the first thin-film transistor and the first output terminal (C2); and wherein the gate electrode of the second thin-film transistor and the second output terminal are not electrically connected to each other (T4).
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/IM/Examiner, Art Unit 2626
/TEMESGHEN GHEBRETINSAE/ Supervisory Patent Examiner, Art Unit 2626 1/29/26