DETAILED ACTION
This Office Action is in response to the application filed on 06/03/2025, wherein claims 1-20 have been examined and are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 5 and 15 recite “numbers of the form
k
2
q
for k ϵ [0,
2
l
]”. “q” and “l” are not specified, so it is unclear what they are.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
1. Claims 1-4, 7-8, 10-11, 13-14, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Aishurafa et al. (U.S. 2021/0067694) hereinafter Aishurafa, in view of Lee et al. (U.S. 2019/0020879) hereinafter Lee.
Regarding claims 1 and 11, Aishurafa discloses a wearable image capture and compression device, and a method of capturing, obfuscating, and compressing images, comprising:
a visible imager that captures image data within a field of view, the image data forming a series of image frames, each image frame including a plurality of pixel blocks (Aishurafa [0005], [0025]: capturing, with a camera, first video of a scene in the forms of first image frames);
a non-visible imager that captures signals outside the human-visible spectrum from objects within the field of view (Aishurafa [0005], [0025]: capturing, with an infrared sensor, second video of the scene in the form of second image frames);
a processor that generates an obfuscation mask, based on the signals captured by the non- visible imager, marking each pixel block in the image frame for either obfuscating or passing the pixel block (Aishurafa [0005], [0031]: analyzing, by a processor in communication with the camera and infrared sensor, the second video captured by the infrared sensor to identify a foreground and a background of the scene. Obfuscating, by the processor and based on the identification of the foreground and the background, one or more portions of the scene to block sensitive imagery; [0024]: image obfuscation can be software system that removes privacy sensitive background information (e.g. bystanders, faces, etc.) from video while retaining important egocentric foreground activity of interest; Claim 4: obfuscate the portions of the scene by blurring or masking the portions; [0036]: the image obfuscation involves extraction of the foreground, creation of an obfuscated image using or more obfuscation techniques (blur, mask) and overlaying of the foreground onto the obfuscated image; [0042], [0057]: any obfuscation method can be incorporated including mask (set pixels to zero); [0070]: most common obfuscation is masking a portion of the scene, which provides no information about the obfuscated part); and
Aishurafa broadly discloses an obfuscation-aware compressor that obfuscates and compresses each image frame by: buffering a subset of the pixel blocks included in image frame; obfuscating the pixel blocks marked for obfuscating by the obfuscation mask; and compressing the pixel blocks marked for passing by the obfuscation mask (Aishurafa [0027], [0033], Claims 13-14: buffer can be used to buffering image frames; [0066]: compressed images).
Lee discloses generates an obfuscation mask, based on the signals captured by the imager, marking each pixel block in the image frame for either obfuscating or passing the pixel block; an obfuscation-aware compressor that obfuscates and compresses each image frame by: buffering a subset of the pixel blocks included in image frame; obfuscating the pixel blocks marked for obfuscating by the obfuscation mask; and compressing the pixel blocks marked for passing by the obfuscation mask (Lee [0052], [0075]: buffers for image data; [0039]: encoder to compress image data which can generate obscured data as in [0067]; [0065], Fig. 4: the system receives mask data 403, i.e. obfuscation mask, which informs the system of the frames and sections which are to be obscured such as macroblocks indices of the section that is intended to be obscured. Pixels coordinates of specific locations on the mask may be used to determine the region to be masked. Mask data can be auto-generated based on analysis of the input frame. If the system determines at 412 that a section does not need to be obscured then it proceeds to encode the section 414 as normal. Hence, compressing the pixel blocks marked for passing the obfuscation mask; [0066]-[0069]: if it is determined that the section is to be obscured then the system, the system perform obfuscation which can be done by setting Quantization Parameter QP to maximum and forced encoding as Intra-section or by calculating Discrete Cosign Transform DCR and setting all of the coefficient creating by DCT of intra-prediction to 0).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the system, as disclosed by Aishurafa, and further incorporate generating an obfuscation mask, marking each pixel block in the image frame for either obfuscating or passing the pixel block; an obfuscation-aware compressor that obfuscates and compresses each image frame by: buffering a subset of the pixel blocks included in image frame; obfuscating the pixel blocks marked for obfuscating by the obfuscation mask; and compressing the pixel blocks marked for passing by the obfuscation mask, as taught by Lee, to visually pleasing obscuring in region of interest without modifying the original content (Lee [0079]).
Regarding claim 2, Aishurafa and Lee disclose all the limitations of claim 1.
Aishurafa broadly discloses each image frame comprises M pixel blocks; and the hardware image compressor sequentially buffers, obfuscates, and compresses N pixel blocks, where M > N (Aishurafa [0005], [0031]: analyzing, by a processor in communication with the camera and infrared sensor, the second video captured by the infrared sensor to identify a foreground and a background of the scene. Obfuscating, by the processor and based on the identification of the foreground and the background, one or more portions of the scene to block sensitive imagery; [0024]: image obfuscation can be software system that removes privacy sensitive background information (e.g. bystanders, faces, etc.) from video while retaining important egocentric foreground activity of interest. Hence, buffers, obfuscates N pixel blocks wherein M>N and M is pixel blocks of the image frame).
Lee also discloses each image frame comprises M pixel blocks; and the hardware image compressor sequentially buffers, obfuscates, and compresses N pixel blocks, where M > N (Lee [0052], [0075]: buffers for image data; [0066]-[0070]: obfuscation a section to be obscured and then encode the data as in [0069]. A section or sections of the image are obscured, hence, N pixel blocks wherein M>N and M is pixel blocks of the image frame).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the system, as disclosed by Aishurafa and Lee, and further incorporate having each image frame comprises M pixel blocks; and the hardware image compressor sequentially buffers, obfuscates, and compresses N pixel blocks, where M > N, as taught by Lee, to visually pleasing obscuring in region of interest without modifying the original content (Lee [0079]).
Regarding claims 3 and 13, Aishurafa and Lee disclose all the limitations of claims 1 and 11, respectively.
Aishurafa does not explicitly disclose the obfuscation-aware compressor compresses each pixel block by performing a discrete cosine transform (DCT) to calculate a plurality of DCT coefficients; and the obfuscation-aware compressor obfuscates the pixel blocks marked for obfuscating by the obfuscation mask by setting some or all of the DCT coefficients to 0.
Lee discloses the obfuscation-aware compressor compresses each pixel block by performing a discrete cosine transform (DCT) to calculate a plurality of DCT coefficients; and the obfuscation-aware compressor obfuscates the pixel blocks marked for obfuscating by the obfuscation mask by setting some or all of the DCT coefficients to 0 (Lee [0067]-[0068]: obfuscation can be achieved by calculating Discrete Cosign Transform DCR and setting all of the coefficient creating by DCT of intra-prediction to 0)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the system and method, as disclosed by Aishurafa and Lee, and further incorporate having the obfuscation-aware compressor compresses each pixel block by performing a discrete cosine transform (DCT) to calculate a plurality of DCT coefficients; and the obfuscation-aware compressor obfuscates the pixel blocks marked for obfuscating by the obfuscation mask by setting some or all of the DCT coefficients to 0, as taught by Lee, to visually pleasing obscuring in region of interest without modifying the original content (Lee [0079]).
Regarding claims 4 and 14, Aishurafa and Lee disclose all the limitations of claims 3 and 13, respectively.
Aishurafa does not explicitly disclose wherein the obfuscation-aware compressor further compresses each pixel block by performing quantization and Huffman encoding.
Lee discloses wherein the obfuscation-aware compressor further compresses each pixel block by performing quantization (Lee [0029], [0067]: quantization which Quantization Parameter QP is performed for compression).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the system and method, as disclosed by Aishurafa and Lee, and further incorporate having disclose wherein the obfuscation-aware compressor further compresses each pixel block by performing quantization, as taught by Lee, to visually pleasing obscuring in region of interest without modifying the original content (Lee [0079]).
Regarding claims 7 and 17, Aishurafa and Lee disclose all the limitations of claims 1 and 11, respectively.
Aishurafa broadly discloses wherein the processor generates the obfuscation mask in accordance with the signals captured by the non-visible imager by executing a mask generation function (Aishurafa [0005], [0031]: analyzing, by a processor in communication with the camera and infrared sensor, the second video captured by the infrared sensor to identify a foreground and a background of the scene. Obfuscating, by the processor and based on the identification of the foreground and the background, one or more portions of the scene to block sensitive imagery; [0024]: image obfuscation can be software system that removes privacy sensitive background information (e.g. bystanders, faces, etc.) from video while retaining important egocentric foreground activity of interest; Claim 4: obfuscate the portions of the scene by blurring or masking the portions; [0036]: the image obfuscation involves extraction of the foreground, creation of an obfuscated image using or more obfuscation techniques (blur, mask) and overlaying of the foreground onto the obfuscated image; [0042], [0057]: any obfuscation method can be incorporated including mask (set pixels to zero); [0070]: most common obfuscation is masking a portion of the scene, which provides no information about the obfuscated part).
Lee discloses the processor generates the obfuscation mask in accordance with the signals captured by the imager by executing a mask generation function (Lee [0065], Fig. 4: the system receives mask data 403, i.e. obfuscation mask, which informs the system of the frames and sections which are to be obscured such as macroblocks indices of the section that is intended to be obscured. Pixels coordinates of specific locations on the mask may be used to determine the region to be masked. Mask data can be auto-generated based on analysis of the input frame).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the system, as disclosed by Aishurafa and Lee, and further incorporate having the processor generates the obfuscation mask in accordance with the signals captured by the non-visible imager by executing a mask generation function, as taught by Lee, to visually pleasing obscuring in region of interest without modifying the original content (Lee [0079]).
Regarding claims 8 and 18, Aishurafa and Lee disclose all the limitations of claims 1 and 11, respectively.
Aishurafa discloses wherein the processor is a microcontroller (Aishurafa [0026]-[0027]: microcontroller can be used).
Regarding claims 10 and 20, Aishurafa and Lee disclose all the limitations of claims 1 and 11, respectively.
Aishurafa discloses wherein the non-visible imager is an infrared thermal imager or a time-of-flight depth camera (Aishurafa [0005], [0025]: capturing, with an infrared sensor, second video of the scene in the form of second image frames).
2. Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Aishurafa et al. (U.S. 2021/0067694) hereinafter Aishurafa, in view of Lee et al. (U.S. 2019/0020879) hereinafter Lee, further in view of Kumar et al. (U.S. 12,585,818) hereinafter Kumar.
Regarding claims 6 and 16, Aishurafa and Lee disclose all the limitations of claims 1 and 11, respectively.
Aishurafa does not explicitly disclose wherein the obfuscation-aware compressor is a field- programmable gate array (FPGA).
Kumar discloses obfuscation-aware compressor is a field- programmable gate array (FPGA) (Kumar Col. 3, lines 50-65, Col. 12, lines 4-16: obscure sensitive data of image; Col. 9, lines 43-62: image data processor can perform compression, wherein FGPA can be used).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the system and method, as disclosed by Aishurafa and Lee, and further incorporate having the obfuscation-aware compressor is a field- programmable gate array (FPGA), as taught by Kumar, to perform various image processing enhancement operations of the image (Kumar Col. 9, lines 43-62).
3. Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Aishurafa et al. (U.S. 2021/0067694) hereinafter Aishurafa, in view of Lee et al. (U.S. 2019/0020879) hereinafter Lee, further in view of Da Veiga et al. (U.S. 2024/0404177) hereinafter Da Veiga.
Regarding claims 9 and 19, Aishurafa and Lee disclose all the limitations of claims 1 and 11, respectively.
Aishurafa does not explicitly disclose wherein the processor provides functionality for users to specify or modify the mask generation function.
However, Da Veiga discloses wherein the processor provides functionality for users to specify or modify the mask generation function (Da Veiga [0071]: blurring a region of image, such as wall hanging 150 in Fig. 8D; [0078]: a privacy module that may be based on one or more user setting that control the amount of blurring or masking particular areas of the background data of image).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the system and method, as disclosed by Aishurafa and Lee, and further incorporate having wherein the processor provides functionality for users to specify or modify the mask generation function, as taught by Da Veiga, to obfuscate image data based on user’s desire (Da Veiga [0078]).
4. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Aishurafa et al. (U.S. 2021/0067694) hereinafter Aishurafa, in view of Lee et al. (U.S. 2019/0020879) hereinafter Lee, further in view of Ramesh et al. (U.S. 2025/0078511) hereinafter Ramesh.
Regarding claim 12, Aishurafa and Lee disclose all the limitations of claim 11.
Aishurafa does not explicitly disclose wherein obfuscating and compressing each image frame comprises obfuscating and compressing a plurality of pixel blocks in parallel.
However, Ramesh discloses wherein obfuscating image frame wherein the system can process a plurality of blocks in parallel (Ramesh Figs. 5-6, [0053], [0056], [0060], [0094], [0101]: obscuring portions of video data; [0122]: GPU may have parallel structure that is efficient for parallel processing of large blocks of data).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the system and method, as disclosed by Aishurafa and Lee, and further incorporate having obfuscating and compressing each image frame comprises obfuscating and compressing a plurality of pixel blocks in parallel, as taught by Ramesh, to obfuscate image data based on user’s desire (Ramesh [0078]).
Allowable Subject Matter
Claims 5 and 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claim.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 5 and 15, the prior arts of record, taken individually or in combination fail to explicitly teach or render obvious within the context of the claims the feature of the obfuscation-aware compressor performs quantization using a 16x8-bit divider that allows for division by numbers of the form
k
2
q
for k ϵ [0,
2
l
] as cited in claims 5 and 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATHLEEN V NGUYEN whose telephone number is (571)270-0626. The examiner can normally be reached on M-F 9:00am-6:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jamie Atala can be reached on 571-272-7384. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KATHLEEN V NGUYEN/Primary Examiner, Art Unit 2486
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